library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity adder1 is
port (A0,A1,A2,A3,A4:in STD_LOGIC;
B0,B1,B2,B3,B4:in STD_LOGIC;
S0,S1,S2,S3,S4:out STD_LOGIC

);
end adder1;

architecture Behavioral of adder1 is

CIN=0;
Component FADDER is
port(A,B,C:in STD_LOGIC;
SUM,CARRY:out STD_LOGIC);
end component;

SIGNAL C1,C2,C3,C4,C5:STD_LOGIC;

begin

U0:FADDER PORT MAP(A0,B0,CIN,S0,C1);

U1:FADDER PORT MAP(A1,B1,C1,S1,C2);
U2:FADDER PORT MAP(A2,B2,C2,S2,C3);
U3:FADDER PORT MAP(A3,B3,C3,S3,C4);
U4:FADDER PORT MAP(A4,B4,C4,S4,C5);

end Behavioral;