Experiment No.

12
IMPLEMENTATION OF SISO, SIPO, PISO AND PIPO
SHIFT REGISTER
OBJECTIVE
 Designing of SISO, SIPO, PISO and PIPO shift register using D flip flop.

EQUIPMENT
 PC installed with Proteus
 2 resisters 1K ohm
 Connecting wires

COMPONENTs
 IC Type 7400 Quadruple 2-input NAND gates
 IC Type 7474 Dual D-Type flip-flops

THEORY
A register capable of shifting its binary information either to the right or to the left is called a
shift register. An n-bit shift register consists of n-FFs and the gates control the shift operation.
Shift registers are used in a digital system for temporary information storage and data
manipulation and transferring.
SISO type of shift register accepts data serially that is, one bit at a time on a single line. It
produces the stored information on its output also in serial form.
SIPO is used in order to shift the data in parallel, it is necessary to have all the data available
outputs at the same time. Once the data are stored, each bit appear on its respective output line
and all bits are available simultaneously, rather on a bit-by-bit basis as with the serial output.
PIPO type of register data can be shifted either into or out of the register in parallel.
PISO shift register the data is entered simultaneously into the respective stages, but the data bits
are transferred out of the register serially, i.e. is bit-by-bit basis over a single line.

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CONNECTION DIAGRAM

Figure 12.1: Serial in serial out

F
Figure 12.2: Serial in parallel out

Figure 12.3: Parallel in serial out

Digital Logic Design Lab Manual 50

 Figure 12.4: Parallel in parallel out

PROCEDURE

1. Connect the RIMS Trainer to the 220V AC supply.

2. Verify all gates 74LS00.
3.For SISO make connections as shown in Figure 12.1.
4.For SIPO make connections as shown in Figure 12.2.
5.For PISO make connections as shown in Figure 12.3.
6.For PIPO make connections as shown in Figure 12.4.

CONCLUSION
1. -------------------------------------------------------------------------------------------
2. -------------------------------------------------------------------------------------------
3. --------------------------------------------------------------------------------------------

Digital Logic Design Lab Manual 51