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Chapt08PP 120121 PDF
Chapt08PP 120121 PDF
CHAPTER 8
P.P.8.1
10 i a vL
+
+ + i
+ +
2 v 24V
2 vC 50mF
24V
(a) (b)
(c) As t approaches infinity, the capacitor is replaced by an open circuit and the
inductor is replaced by a short circuit.
5 a 5 b
4A +
iR iL + vR +
vC 10 F vL
6A 2H
6A
(a) (b)
Since v R = 5i R , dv R /dt = 5di R /dt = 5di L /dt. But Ldi L /dt = v L , di L /dt = v L /L.
5
4A iL
6A
P.P.8.3
P.P.8.4 For t < 0, the inductor is connected to the voltage source and when the
circuit reaches steady state, the inductor acts like a short circuit.
1
o 1 LC 1 1x 3
9
i(0) = 10 = A 1
A 2 = –15.076
0 1 LC 1 0.4 x 25 x10 3 10
o 1 LC 1 10 x 4 x10 3 = 5
A 1 = –150, A 2 = 150
P.P.8.7 The initial capacitor voltage is obtained when the switch is in position a.
When the switch is in position b, we have the RLC circuit with the voltage source.
= R/(2L) = 10/(2x2.5) = 2
o 1 LC 1 (5 / 2) x (1 / 40) = 4
Since < o , we have an underdamped case.
where v f = v() = 15, the final capacitor voltage. We now impose the initial
conditions to get A 1 and A 2 .
v(0) = 12 = 15 + A 1 leads to A 1 = –3
The initial capacitor current is the same as the initial inductor current.
v R (t) = (3.464sin(3.464t)e–2t) V
Ldi(0)/dt = v(0) = 0
But di/dt = –A 1 0.25sin(0.25t) + A 2 0.25cos(0.25t)
For t > 0, the switch is closed. We have the equivalent circuit as in Figure (a).
iC i iC i
10 4 10 4
3A + 3A
(1/20)F v
2H
(a) (b)
–3 + i C + i = 0 (3)
Next we find the network response by turning off the current source as shown in
Figure (c).
iC i
10 4
i
+
(1/20)F
v 2H
(c)
Applying KVL gives –v – 10i C + 4i + 2di/dt = 0 (6)
or (d2v/dt2) + 7(dv/dt) + 10 = 0
dv(0)/dt = 60 = –2A – 5B
2A + 5B = –60 (10)
(a) (b)
i 1 = C 1 dv 1 /dt, or dv 1 /dt = i 1 /C 1 ; likewise dv 2 /dt = i 2 /C 2
dv 2 (0+)/dt = 0 (2b)
Next we obtain the network response by considering the circuit in Figure (c).
1 1
v1 v2
0.5F (1/3)F
(c)
v 2 = v 2n + v 2f = 20 + (Ae-t + Be-6t)
dv 2 (0) = 0 = –A – 6B (7)
(R 1 R 2 C 1 C 2 ) = 104x104x20x10-6x100x10-6 = 2x10-2
1/(R 1 R 2 C 1 C 2 ) = 5
0 = 10 + A + B (8)
0 = –A – 5B or A = –5B (9)
(a)
With the switch in position b, the schematic is as shown in Figure (b). A voltage marker
is inserted to display the capacitor voltage. When the schematic is saved and run, the
output is as shown in Figure (c).
(b)
P.P.8.14 The dual circuit is obtained from the original circuit as shown in
Figure (a). It is redrawn as shown in Figure (b).
3H
3F
50mA
4H
10
+
0.1 4 F
50mV
(a)
3H
0.1
+ 4F
50mV
(b)
P.P.8.15 The dual circuit is obtained in Figure (a) and redrawn in Figure (b).
5
0.2F 4H
0.2
4F
0.2 H
2A +
1/3 3 20 V
+ 20A
2V
(a)
1/3
0.2 H 4F
+ 0.2 20A
2V
(b)
P.P.8.16 Since 12 = 4i + v L + v C or v C = 12 – 4i - v L
(a)
(a)