SISO

Module siso(si,clk,q);
input si,clk;
output q;
wire s0,s1,s2;
dff dff1(s0,si,clk);
dff dff2(s1,s0,clk);
dff dff3(s2,s1,clk);
dff dff4(q,s2,clk);
end module

module dff(out1,in1,clk);
input in1,clk;
output reg out1;
always@(posedge clk)
begin
out1=in1;
end;
endmodule

SIPO

Module sipo(s0,clk,s1,s2,s3,s4);
input s0,clk;
inout s1,s2,s3;
output s4;
dff dff1(s1,s0,clk);
dff dff2(s2,s1,clk);
dff dff3(s3,s2,clk);
dff dff4(s4,s3,clk);
end module

module dff(out1,in1,clk);
input in1,clk;
output reg out1;
always@(posedge clk)
begin
out1=in1;
end;
endmodule