PLL are widely used circuit used in clock generation and distribution however in many cases are

not easily explain or understood. PLL’S can be found in various system applications where an
entity or data needs to be clocked this can include DSP, FPGA, processors, and microcontrollers.
Data converters as well as certain memory subsystem and surtees in simple terms a PLL is a
feedback system that generates a signal that has a fixed relation to the phase of an incoming
reference signal the simplest of PLL’s consists of a phase detector and a voltage controlled
oscillator (VCO). The purpose of a phase detector is to perform a comparative evaluation of the
signals applied to its to inputs. a reference frequency is fed into one input while the output of the
VCO is fed back into the second input of the phase detector. This is commonly known as the
feedback loop if the phase of the feedback input lags the phase of the reference input the phase
detector in combination with a charge pump and low pass filter will ouput a higher DC voltage to
speed up the VCO. If the reverse is a true a lower DC voltage is output to slow down the VCO in
the end the output of the VCO will mirror input reference signal to the phase detector. This output
can be used to distribute multiple copies of clocks with the same phase and frequency more
commonly known as a zero delay. PLL can also be used for clock generation. Two commont types
of PLL are integer PLL and fractional PLL. This PLL can include additional functional blocks
called the reference divider and feedback divider. The variable R and the reference divider is a
programable parameter and is sometime known as a pre scalar once set the reference divider,
divides the signal represented on the reference input with this program will value. The variable in
the feedback divider is also a programable parameter and is sometimes known as the encounter or
divider. For integer PLL, the value of n is set as an integer value. For fractional PLL, the value of
n can be a non integer value. The relationship between the the value of r and n has a direct impact
on the ouput frequency of the VCO and the PLL circuit. Simply put the output frequency is equal
n divided by r multiplied the reference input frequency when providing different values of r and
n, the output frequencies can generated that either are integer or fractional variations of the
reference input.