electronics

Article
A Nonisolated Three-Port DC–DC Converter with
Continuous Input and Output Currents Based on Cuk
Topology for PV/Fuel Cell Applications
Balaji Chandrasekar 1, * , Chellammal Nallaperumal 1 and Subranshu Sekhar Dash 2
1 Department of Electrical and Electronics Engineering, SRM IST, Kattankulathur, Chennai,
Tamilnadu PIN-603203, India; chellavenkat09@gmail.com
2 Department of Electrical and Electronics Engineering, Government College of Engineering, Keonjhar,
Odisha PIN-758002, India; subhransudash_fee@gcekjr.ac.in
* Correspondence: balaji2work@gmail.com; Tel.: +91-9176056974




Received: 14 January 2019; Accepted: 10 February 2019; Published: 15 February 2019


Abstract: A nonisolated three-port DC–DC converter based on Cuk topology (NI-TPC) to handle
the renewable sources (RS) is proposed in this paper. This converter includes two unidirectional
input ports accommodating both a fuel cell (FC) and photovoltaic (PV) cell; and one output port
with DC load. Due to the inductors at all the ports, it claims the advantage of continuous input and
output currents. Additionally, it uses less number of switches, diodes and inductors compared with
conventional ‘n-1’ separate Cuk converters. Synthesis procedure for a generalized n-port DC–DC
structure is explained. The derivation law based on conventional Cuk converter, operating principle,
design calculation, and analysis are presented in detail, and then the analysis is validated through
simulation and a 100W prototype, verifying the performance of the proposed NI-TPC converter.

Keywords: DC–DC; Nonisolated; Three-port; Cuk; PV/Fuel cell; Continuous current

1. Introduction
Fast and society-threatening global warming and health hazards due to the combustion of fossil
fuels have triggered the research and development of more efficient and cleaner renewable sources
(RS) namely solar, wind, fuel cell etc. Many DC–DC converters with a single inductor, for example,
buck and boost converters and two inductor converters, such as Sepic, Cuk, and zeta converters, have
been used to connect RS and load [1,2]. However, the stochastic and time-varying characteristics of
these sources and unpredictable demand at load side necessitate the backup source for continuous
power flow to the load. This condition forces the system to have at least two input ports; one for RS
and another for a backup source such as fuel cell/wind/battery.
In the recent past, new converter topologies called multiport converters (MPC) have been
proposed to integrate these RS, which ensure the continuous power flow to the load. The structure
of conventional and MPC system is shown in Figure 1. The MPCs enhance the utilization of power
sources based on their V–I characteristics, availability and cost [3]. Multiport converters (MPC) which
claim the advantage of component sharing are acknowledged as one of the promising topologies to
integrate the RS to cater the future energy generation requirements. Moreover, compact structure and
lesser conversion stages are the reasons to adopt MPC for numerous applications such as hybrid
power system [4], renewable energy integration [5], hybrid vehicles [6], aerospace applications,
and uninterrupted power supplies. This MPC, in particular, the three-port converter (TPC) can
be divided into three groups: (1) the isolated DC–DC converter; (2) semi-isolated DC–DC converter;
and (3) nonisolated converter topologies. The isolated TPC uses a transformer with a high-frequency

Electronics 2019, 8, 214; doi:10.3390/electronics8020214 www.mdpi.com/journal/electronics

 Electronics
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2019, 214 PEER REVIEW
x FOR 2 of
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nonisolated converter topologies. The isolated TPC uses a transformer with a high-frequency to
to provide magnetic coupling and electrical isolation between the source and load [6–8]; partially
provide magnetic coupling and electrical isolation between the source and load [6–8]; partially
isolated converters use a common DC bus along with magnetic coupling [9]. A nonisolated TPC uses
isolated converters use a common DC bus along with magnetic coupling [9]. A nonisolated TPC uses
common DC bus and finds applications where the isolation is not needed between the ports [10–12].
common DC bus and finds applications where the isolation is not needed between the ports [10–12].

(a) (b)

Figure 1. (a) Structure of the conventional system, (b) Proposed multiport converter (MPC) system.
Figure 1. (a) Structure of the conventional system, (b) Proposed multiport converter (MPC) system.
TPCs can be configured in two topologies based on the nature of the input sources: series and
TPCs can be configured in two topologies based on the nature of the input sources: series and
parallel. In the series topology, the output voltage regulation becomes challenging if one of the
parallel. In the series topology, the output voltage regulation becomes challenging if one of the input
input sources reduces (e.g., in PV shading condition) [13]. Assumptions and conditions to design
sources reduces (e.g., in PV shading condition) [13]. Assumptions and conditions to design the
the converters with multiple input–single output (MISO) from the conventional single input–single
converters with multiple input–single output (MISO) from the conventional single input–single
output (SISO) structures are explained [14]. The systematic way of synthesizing MISO converters is
output (SISO) structures are explained [14]. The systematic way of synthesizing MISO converters is
detailed in Reference [15]. Topology generation methods and principles for developing a family of
detailed in Reference [15]. Topology generation methods and principles for developing a family of
NI-TPC are proposed [16]. These TPCs are developed by introducing a SISO model in an existing dual
NI-TPC are proposed [16]. These TPCs are developed by introducing a SISO model in an existing
input or two output converters. In Reference [17], an approach to systematically derive MPCs with DC
dual input or two output converters. In Reference [17], an approach to systematically derive MPCs
link inductor concept and with two input and two output converters is proposed. This procedure has
with DC link inductor concept and with two input and two output converters is proposed. This
developed numerous TPC topologies. A novel nonisolated TPC with single inductor is proposed for
procedure has developed numerous TPC topologies. A novel nonisolated TPC with single inductor
RS [18]. This converter features the integration and control of bidirectional load, compactness, single
is proposed for RS [18]. This converter features the integration and control of bidirectional load,
stage power conversion between any two ports, and seven possible operational modes. The design of a
compactness, single stage power conversion between any two ports, and seven possible operational
NI-TPC using one switch for a standalone PV power system integrating energy storage is proposed in
modes. The design of a NI-TPC using one switch for a standalone PV power system integrating
Reference [19]. A synchronous switch with a pair of diodes has been utilized instead of two individual
energy storage is proposed in Reference [19]. A synchronous switch with a pair of diodes has been
switches. However, the converters in both the stages must operate synchronously. The inherent
utilized instead of two individual switches. However, the converters in both the stages must operate
buck–boost characteristics of the Cuk converter provide flexibility for standalone and grid-tied
synchronously. The inherent buck–boost characteristics of the Cuk converter provide flexibility for
applications when the output voltage required is more or less than the input voltage. Continuous
standalone and grid-tied applications when the output voltage required is more or less than the input
current at the input and output ports and the identical switching voltage waveforms appearing across
voltage. Continuous current at the input and output ports and the identical switching voltage
the inductors are the salient features of the Cuk converter [20]. New topologies with high voltage
waveforms appearing across the inductors are the salient features of the Cuk converter [20]. New
ratio have been proposed using Cuk converter in Reference [21] for renewable power applications.
topologies with high voltage ratio have been proposed using Cuk converter in Reference [21] for
In Reference [9], A TPC is presented by integrating a Cuk converter with bidirectional power flow
renewable power applications. In Reference [9], A TPC is presented by integrating a Cuk converter
and a full-bridge (FB) rectifier circuit for renewable energy applications. It used a transformer with
with bidirectional power flow and a full-bridge (FB) rectifier circuit for renewable energy
high frequency. This converter consists of two nonisolated and one isolated ports. A nonisolated
applications. It used a transformer with high frequency. This converter consists of two nonisolated
DC–DC TPC using integrated boost-cuk topology with high voltage gain is proposed [22]. An isolated
and one isolated ports. A nonisolated DC–DC TPC using integrated boost-cuk topology with high
TPC depending on Cuk converter is presented in Reference [23] by incorporating the inductor and
voltage gain is proposed [22]. An isolated TPC depending on Cuk converter is presented in Reference
transformers on a single core. Three winding transformer used in the above converter increases the
[23] by incorporating the inductor and transformers on a single core. Three winding transformer used
size. Moreover, it uses more number of switches. The three-port Cuk converter to solve the zero-ripple
in the above converter increases the size. Moreover, it uses more number of switches. The three-port
problem is presented by designing a single integrated magnetic core having all the magnetics on it [24].
Cuk converter to solve the zero-ripple problem is presented by designing a single integrated
Methods based on circuit theory and the structure of the core are used to analyze the ripples. However,
magnetic core having all the magnetics on it [24]. Methods based on circuit theory and the structure
these converters are the isolated type and use bulky transformers and inductors. In Reference [25],
of the core are used to analyze the ripples. However, these converters are the isolated type and use
a DC–DC converter combining a SEPIC and Cuk converter is proposed for bipolar DC microgrid
bulky transformers and inductors. In Reference [25], a DC–DC converter combining a SEPIC and Cuk
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Electronics 2019, 8, x FOR PEER REVIEW 3 of 20

applications. A single switch shared by both converters is an added advantage. However, the number
converter
of is proposed
power components for bipolar DC microgrid applications. A single switch shared by both
is greater.
converters is an added advantage.
However, the TPCs mentioned However, the number
above fail to provideof power
a highcomponents is greater. ratio and
voltage conversion
However, the TPCs mentioned
continuous current at all the ports. above fail to provide a high voltage conversion ratio and
continuous current atfeatures
The outstanding all the ports.
of the proposed converter are
The outstanding features of the proposed converter are
• Both•the Both
inputthe
ports
inputshare common
ports output inductor,
share common hence minimizing
output inductor, the component
hence minimizing count.
the component
• Continuous count.
current with less ripple in all the ports (the input and output ports).
• • Continuous
Delivered power from current with can
each input less be
ripple in all the ports
independently (the input and output ports).
controlled
• • Delivered
Buck–boost output power
voltages from
caneach input can be independently controlled
be obtained.
• Buck–boost output voltages can be obtained.
To
Tothe
thebest
bestof
ofthe
theauthor’s
author’s knowledge,
knowledge, the the design
design andand development
developmentof of NI-TPC
NI-TPC converter
converterhashasnot
not
been
been reported earlier in literature. In this paper, the design, development, and extensive analysis of
reported earlier in literature. In this paper, the design, development, and extensive analysis of
the
the proposed
proposedconverter
converterhave
havebeen
beencarried
carriedoutouttotovalidate
validatethe
theperformance
performanceof ofthe
theconverter.
converter.
Generally,
Generally, the energy flow flowcontrol
controlmodes
modesand andcircuit
circuit analysis
analysis procedure
procedure areare common
common sense
sense and
and
wellwell discussed
discussed in many
in many other
other papers
papers [4,26–31].However,
[4,26–31]. However,the theDC–DC
DC–DCstructure
structure of
of the Cuk-Cuk
Cuk-Cuk
converter
converterused
usedforforthe
thesystem
systemthat thatintegrates
integratesthetheinput
inputports
ports(1(1and
and2)
2)to
to DC
DC Bus
Bus (Port
(Port 3)
3) is
is new,
new, which
which
increases the novelty of the paper.
increases the novelty of the paper.

2.
2. Proposed
Proposed Converter
Converter Structure
Structure

2.1. Synthesis of the NI-TPC Converter

2.1. Synthesis of the NI-TPC Converter
This section presents the illustration of synthesizing the proposed NI-TPC converter from a
This section presents the illustration of synthesizing the proposed NI-TPC converter from a
classical Cuk converter. Based on the fundamentals, the structure of the classical Cuk converter can be
classical Cuk converter. Based on the fundamentals, the structure of the classical Cuk converter can
deduced to the input section, output section, and an energy buffer section that connects both, as shown
be deduced to the input section, output section, and an energy buffer section that connects both, as
in Figure 2. The capacitor acts as a voltage buffer and transfers energy from input to output section
shown in Figure 2. The capacitor acts as a voltage buffer and transfers energy from input to output
without consuming any energy. The input with voltage buffer and output sections are separated and
section without consuming any energy. The input with voltage buffer and output sections are
connected as represented in Figure 2 to form the generalized n-port structure.
separated and connected as represented in Figure 2 to form the generalized n-port structure.

Figure 2.
Figure 2. Structure
Structure of
of classical
classical Cuk
Cuk converter.
converter.

The resulting
The resulting structure
structure of
of the
the proposed
proposed ‘n’
‘n’ port
port converter
converter consists
consists of ‘n-1’ input sources, ‘n’
inductors, ‘n’
inductors, ‘n’ capacitors,
capacitors, ‘n-1’
‘n-1’ switches
switches and
and aa single
single diode
diode is
is presented
presented in
in Figure
Figure 3.
3. Table
Table 11 gives
gives aa
comparison of the circuit elements used in the proposed and conventional structures.
comparison of the circuit elements used in the proposed and conventional structures.
A three-port converter with two input ports and a load port is taken for better understanding
as shown in Figure 4. One can understand that it is based on the integration of two classical Cuk
converters. The proposed TPC consists of three inductors (L1 , L2 , and L0 ), three capacitors (C1 , C2 ,
and C0 ), two switches (S1 –S2 ), and one diode (D0 ). Power sources V1 and V2 are connected to the
unidirectional input ports.
Electronics 2019, 8, 214 4 of 18
Electronics 2019, 8, x FOR PEER REVIEW 4 of 20

Figure 3. Generalized structure of the proposed ‘n’ port converter.

Table 1. Comparison of circuit elements.

Circuit Elements Proposed n-Port Cuk-Cuk Converter (n-1) Individual Cuk Converters
Inductors n 2(n-1)
Capacitors n 2(n-1)
Figure3.
Figure 3. Generalized
Generalized structure
structureof
ofthe
theproposed
proposed‘n’
‘n’port
portconverter.
converter.
Switch n-1 n
Diode 1
Table 1. Comparison of circuit elements. 2(n-1)
Table 1. Comparison of circuit elements.

ACircuit
Circuit Elements
Elements
three-port converter Proposed
Proposed
with two n-Port
n-Port
input Cuk-Cuk
Cuk-Cuk
ports Converter
Converter
and is(n-1)
a load port(n-1) Individual
Individual
taken Cuk
Cuk
for better Converters
Converters as
understanding
shown in Figure 4. One can understand nthat
Inductors
Inductors n it is based on the integration2(n-1)of two classical Cuk
2(n-1)
Capacitors
Capacitors
converters. n n inductors (L1, L2, and L0), three2(n-1)
The proposed TPC consists of three 2(n-1)
capacitors (C1, C2, and
Switch n-1 n
C0), two Switch
switches (S1–S2), and one diode n-1 (D0). Power sources V1 and V2 are n connected to the
Diode 1 2(n-1)
unidirectional
Diodeinput ports. 1 2(n-1)

A three-port converter with two input ports and a load port is taken for better understanding as
shown in Figure 4. One can understand that it is based on the integration of two classical Cuk
converters. The proposed TPC consists of three inductors (L1, L2, and L0), three capacitors (C1, C2, and
C0), two switches (S1–S2), and one diode (D0). Power sources V1 and V2 are connected to the
unidirectional input ports.

Figure 4. Proposed three-port converter.

Figure 4. Proposed three-port converter.

2.2. Operating Principles

onthe
Based on theavailability
availability of of power
power sources,
sources, the the proposed
proposed TPC TPC can function
can function in twoin two different
different modes:
modes:
the SISOthe
andSISO
dualandinputdual input
single single
output output
(DISO) (DISO)Either
modes. modes. Either
of the of ports
input the input portstocan
can cater cater
load to
in the
load in the
absence absence
of the otherofinthe
SISOother in SISO
mode. mode.
In DISO In DISO
mode, bothmode, both
sources sources contribute
contribute power
power to load to load
when the
when thepower
primary primary power
source source Figure
is insufficientis to 4.meet
Proposed
insufficient three-port
to
the loadmeet the
demand.converter.
load
The demand.
proposedThe proposed
NI-TPC NI-TPC
converter can
converterincan
function all function
these modesin allthrough
these modes through
appropriate appropriate control.
control.
2.2. Operating Principles
2.2.1. Based
SISO Mode on the availability of power sources, the proposed TPC can function in two different
modes: the
Figure 5a SISO
showsandthe
shows dual
the input single
Equivalent
Equivalent output
circuit
circuit when
when (DISO) modes.
operating
operating Either
ininSISO of the
SISOmode.
mode. Theinput
The ports can
equivalent
equivalent cater of
circuits
circuits to
load
of
statestate1inand
1the
and absence
state
state 2of
2 are the
are other
shown
shown inin in SISO5b,5c,
Figure
Figure mode. In DISO mode,
5b,c,respectively.
respectively. Theboth
The sources are
waveforms
waveforms contribute
are not power
not shown sinceto load
it is
when the primary power
similar to the classical Cuk converter. source
converter. is insufficient to meet the load demand. The proposed NI-TPC
converter can function in all these modes through appropriate control.
State
State 11:
2.2.1. SISO Mode
In
In this
this mode,
mode, switch
switch SS11 is
is ON,
ON, but but the
the diode
diode isis not
not conducting.
conducting. Voltage
Voltage source
source V magnetizes the
V11 magnetizes the
inductor
inductor Figure L11.. 5a
L The
The shows the voltage
positive
positive Equivalent
voltage on the
on circuit
the whenmakes
inductor
inductor operating
makes in SISO mode.
the inductor
the inductor The
current
current L1equivalent
iiL1 increasecircuits
toincrease
to linearly.
linearly. of
The capacitor C11 is assumed precharged and discharging its energy to the load through the inductoris
state
The 1 and
capacitor state
C 2
is are shown
assumed in Figure
precharged 5b,5c,
and respectively.
discharging itsThe waveforms
energy to the are
load not shown
through the since
inductorit
Lsimilar
L 00.. Hence,
Hence, to the
theclassical
the inductorCuk
inductor converter.
current
current iiL2 increaseslinearly.
L2 increases linearly. In
In addition,
addition, itit charges
charges the
the output
output capacitor
capacitor C C00..
Various
Various currentscurrents and and voltages
voltages cancan be beexpressed
expressedby by(1).
(1).
State 1:
In this mode, switch S1 is ON, but the diode is not conducting. Voltage source V1 magnetizes the
inductor L1. The positive voltage on the inductor makes the inductor current iL1 to increase linearly.
The capacitor C1 is assumed precharged and discharging its energy to the load through the inductor
L0. Hence, the inductor current iL2 increases linearly. In addition, it charges the output capacitor C0.
Various currents and voltages can be expressed by (1).
Electronics 2019, 8, 214 5 of 18

Electronics 2019, 8, x FOR PEER REVIEW  5 of 20

VL1 = V1 , 


VL0 = VC1 − VC0 
VL1==iV (1)
iC1 L01
, 


V = V −V 

iC0 = i L0 − i 0

L0 C1 C0
 (1)
State 2 iC1 = iL 0 
i 0 =diode 
iL 0 − iconducts
In this state, switch S1 is OFF while Cthe 0 and freewheels. The voltage source
V1 together with the energy stored in the inductor L1 , charge the capacitor C1 through diode D0 .
The
Statecurrent
2 in the inductor iL1 decreases linearly. The output inductor L0 is demagnetized and its
energy flows to the load through diode D0 . Equation (2) is valid in this mode:
In this state, switch S1 is OFF while the diode conducts and freewheels. The voltage source V1

together with the energy stored in the inductor
VL1 = V1L1− , charge
VC1 , the capacitor C1 through diode D0. The
current in the inductor iL1 decreases linearly. The output inductor L0 is demagnetized and its energy

VL0 = −VC0 
flows to the load through diode D0. Equation (2)
iC1 =(2)i L1is valid inthis mode:


iC0 = i L0 − i0
VL1 = V1 − VC1 , 


V0 V
V1 = L0−=1−−DVD1 C 0  
1
 (2)


IL1iC= =P1
i
1 V1 L1
, I L0 = VP00
 (3)
R Li = =VP00i − i 
2 

C0 L0 0 

(a)

(b) (c)
Figure
Figure 5.5. (a)
(a)Single
Singleinput–single
input–singleoutput
output(SISO)
(SISO)mode
modeofofthe proposed
the converter:
proposed (b)(b)
converter: State 1 and
State (c)
1 and
State 2.
(c) State 2.

2.2.2. DISO Mode

VO D1 
Better utilization of power sources needs= a− suitable control technique to achieve the regulated
V1 1 − D1 
output power. The appropriate switching pattern in various modes depends on the time multiplexing
P1 P0 
of switching signals. I L1 = , I L 0 =  (3)
V1 V0 
Selection of switching sequence can be done in many ways based on whether power is catered
VO 2 
individually or simultaneously. A left-aligned
RL =switching pattern
 as shown in Figure 6 has been chosen
P
in this work for analysis of the proposed converter.O 

2.2.2. DISO Mode

Better utilization of power sources needs a suitable control technique to achieve the regulated
output power. The appropriate switching pattern in various modes depends on the time multiplexing
of switching signals.
 Figure 6. Left-aligned switching pattern.

Electronics 2019, 8, x FOR PEER REVIEW 6 of 20

State 1
Selection of switching
During this state,sequence can beSdone
both switches 1 andin
S2many ways
are ON, butbased on whether
the diode remainspower is catered The
nonconducting.
individually
Electronics 2019, 8,or
voltage simultaneously.
sources
214 A left-aligned
V1and V2 magnetize switching
the inductors pattern
L1 and as shown in
L2 respectively. TheFigure 6 has
positive 6been
voltage
of 18on
the
chosen in this work
inductors makesforthe
analysis of the
inductor proposed
currents converter.
increase linearly. Capacitors C1 and C2 are assumed precharged
and to be discharging energy. The load is catered by the capacitors discharge through the inductor
L0. The corresponding equivalent circuit is illustrated in Figure 7a. The corresponding equations have
been presented in (4).

VL1 = V1 , VL 2 = V2 
VL 0 = V0 − VC1 
 (4)
iC1 + iC 2 = iL 0 
iC 0 = switching 
iL 0 − i0 pattern.
Figure 6.
Figure 6. Left-aligned
Left-aligned switching pattern.

State 1
State 2
During this
this state,
state, both
bothswitches
switchesS1Sand
1 and S2 S are2 are
ON,ON, but butthe the
diodediode remains
remains nonconducting.
nonconducting. The
In this interval, switch S1 is OFF and switch S2 is ON, but the diode stays nonconducting due to
The voltage sources V and V magnetize the inductors L and L respectively.
voltage sources V1and V2 magnetize the inductors L1 and L2 respectively. The positive voltage on the
1 2 1 2 The positive voltage
the voltage across capacitor C2. The voltage source V1 together with the energy stored in the inductor
on the inductors
inductors makes the makes the inductor
inductor currentscurrents increase Capacitors
increase linearly. linearly. Capacitors C1 assumed
C1 and C2 are and C2 are assumed
precharged
L1, charges the capacitor C1. V2 continues to discharge and magnetize the inductor L2. Due to the
precharged and to be discharging
and to be discharging energy. The energy. The load
load is catered byisthe catered by the
capacitors capacitors
discharge discharge
through through
the inductor
positive and constant voltage on inductor L2, its current raises linearly. The capacitor C2 continues to
the inductor L .
L0. The corresponding
0 The corresponding equivalent circuit is illustrated in Figure 7a.
equivalent circuit is illustrated in Figure 7a. The corresponding equations haveThe corresponding
discharge as in Mode 1, and the load is catered by it through the inductor L0. The corresponding
equations have been
been presented in (4).presented in (4).
equivalent circuit is presented in Figure 7b. Equation (5) is derived for this mode.
VVL1L1V== V V=11,,V
V = V 

L 2−=
VL2 V
1 VC 1 +  VC 2 
2
2


L1

VVL0 ==VV0 −− V V  

C1
Li 2 == i2L0VL 0 =V 0 − VC 2 
L 0V 0 V ,C 1 (4)
iC1 + (4)
i +
C2
i = i  (5)

iL1i,0Li0C 2 = iL

C=2 −
iC0C1= iC1i L0 0 − iC 1 


iC 0 i= iL=0 i− i0− i  
C0 L0 0

State 2
In this interval, switch S1 is OFF and switch S2 is ON, but the diode stays nonconducting due to
the voltage across capacitor C2. The voltage source V1 together with the energy stored in the inductor
L1, charges the capacitor C1. V2 continues to discharge and magnetize the inductor L2. Due to the
positive 2019,
Electronics and constant voltage
8, x FOR PEER on inductor L2, its current raises linearly. The capacitor C2 continues
REVIEW 7 of to
20
(a) (b)
discharge as in Mode 1, and the load is catered by it through the inductor L0. The corresponding
equivalent circuit is presented in Figure 7b. Equation (5) is derived for this mode.

VL1 = V1 − VC1 + VC 2 
VL 2 = V2 , VL 0 = V0 − VC 2 
 (5)
iC1 = iL1 , iC 2 = iL 0 − iC1 
iC 0 = iL 0 − i0 
(c)

Figure 7. Equivalent circuits: (a) State 1, (b) State 2, and (c) State 3.

State 32
State
In this
In this interval, switch
state, both S1 is OFF
switches andSswitch
S1 and 2 are OFF
S2 iswhile
ON, butthe the diode
diode stays nonconducting
conducts and freewheels. due to
The
the voltage across capacitor
voltage sources V1 and V2 together C 2 . The voltage source
with the energy stored V 1 together with the energy stored in the inductor
in the inductors L1 and L2, charge capacitors
L11 ,and
charges (a) C . V continues to discharge and magnetize
the capacitor (b) the inductor L2 . Due to the
C C2 respectively. 1
The current 2 in the inductors iL1 and iL2 decreases linearly. The output inductor
positive and constant
L0 discharges voltage
and the load on inductor
is catered L2 , its current
by it through the Diode raises
D0. linearly. The capacitor
The equivalent C2this
circuit of continues
state is
to discharge as in Mode 1, and the load is catered by it through
illustrated in Figure 7c. Various currents and voltages can be expressed as in (6). the inductor L 0 . The corresponding
equivalent circuit is presented in Figure 7b. Equation (5) is derived for this mode.
VL1 = V1 − VC1 
VL 2 = V2 − VC 2 , VL 0 = V0 
 (6)
iC1 = iL1 , iC 2 = iL 2 
iC 0 = iL 0 − i0 

Ideal operating conditions with Steady state and continuous conduction mode (CCM) is
assumed to derive the expressions of the output voltage and voltage gain.
Electronics 2019, 8, 214 7 of 18


VL1 = V1 − VC1 + VC2 


VL2 = V2 , VL0 = V0 − VC2 
(5)
iC1 = i L1 , iC2 = i L0 − iC1 


iC0 = i L0 − i0


State 3
In this state, both switches S1 and S2 are OFF while the diode conducts and freewheels. The voltage
sources V1 and V2 together with the energy stored in the inductors L1 and L2 , charge capacitors C1
and C2 respectively. The current in the inductors iL1 and iL2 decreases linearly. The output inductor L0
discharges and the load is catered by it through the Diode D0 . The equivalent circuit of this state is
illustrated in Figure 7c. Various currents and voltages can be expressed as in (6).

VL1 = V1 − VC1 


VL2 = V2 − VC2 , VL0 = V0 
(6)
iC1 = i L1 , iC2 = i L2 


iC0 = i L0 − i0


Ideal operating conditions with Steady state and continuous conduction mode (CCM) is assumed
to derive the expressions of the output voltage and voltage gain.

3. Modeling and Analysis of the Converter

The derivation of various parameters and modeling of the proposed NI-TPC converter are
presented in this section.

3.1. Voltage Gain

The analytical expression for the output voltage has been obtained by applying volt second
balance theory on inductors.
V1 = Vc1 (1 − δ1 ) − Vc2 (δ2 − δ1 ) (7)
V2
Vc2 = (8)
(1 − δ2 )
V0 = δ1 Vc1 + δ2 Vc2 (9)

The expression of the output voltage can be derived from Equations (7)–(9). The voltage equation
in terms of duty cycles is

δ1 δ2 (δ2 − δ1 )
V0 = V + V2 = GV1 ·V1 + GV2 ·V2 (10)
(1 − δ1 ) 1 (1 − δ1 )(1 − δ2 )

From (10), one can understand that the proposed converter operating in DISO mode has the
same voltage gain compared with classical Cuk converter, which is plotted in Figure 8. Considering
V1 = V2 = V, the output voltage of the proposed converter is presented in (11). Selecting the same duty
ratio for both the switches leads to the output voltage equal to the one in classical Cuk converter as
derived in (12). The voltage gain for an n-port DC–DC Cuk-Cuk converter with the proposed topology
can be derived as in (13).

δ1 δ2 (δ2 − δ1 )
V0 = V1 + V2 = GV1 ·V1 + GV2 ·V2 (11)
(1 − δ1 ) (1 − δ1 )(1 − δ2 )

Taking δ1 = δ2 = δ
δ
V0 = V (12)
1−δ
 δ1 δ (δ − δ )
V0 = V1 + 2 2 1 V2 = GV 1.V 1 + GV 2.V 2 (11)
(1 − δ1 ) (1 − δ1 )(1 − δ 2 )
Taking δ1= δ2= δ

Electronics 2019, 8, 214 δ 8 of 18

VO = V (12)
1− δ
For an n-port converter,
converter,

 δδ1 1 nn δδii(δ −δδ11)) 

(δii −
" #
VV
0 O
= = 11− +
+ 
∑ VVi
)(1−−δδi )i ) i
(13)
(13)
 − δδ11 ii==2 ((11 −−δδ11)(1

Figure 8. Voltage
Voltage gain Vs Duty cycle of NI-TPC converter.
converter.

Applying the charge-sec balance

balance principle
principle on
on capacitors,
capacitors, the
the following
following equations
equations are
are obtained.
obtained.
dV1 iL 0
I C1 = C
dV i= δ +i δ +i δ
h IC1 i = C1 11
= L0 dt
dt δ1 +1i L1 δLe 1+ei L1 δLo1f f off
dt dt
δδ11
iiL1 = iiL 0 (14)
22((δδ11−− 11)) L0
L1 = (14)

dV2 i
=2 L0 iδL10+ (i L0 − i L1 )δe + i L2 δo f f
dV
h IC2 i = C2
I C 2 = Cdt2 =2 δ1 + ( iL 0 − iL1 ) δ e + iL 2δ off
dt 2 !
δ1 δ2 δ12 δ i L0
i L2 = − − δ2 + 1 (15)
 2(δδ11δ−21) 2(δδ1 1−
2
1) 
δ21 (1i−L0δ2 )
iL 2 =  − − δ 2 +  (15)
 2 (δ1 − 1) 2 (δ1 − 1) 2  (1 − δ 2 )
3.2. Current Ripples of Inductors
Current ripples and inductor volt-second balance (IVSB) principle are used to design inductors.
3.2. Current
The inductorRipples
currentof ripple
Inductors
equations are modified to obtain equations for inductor values (16)–(18).
Current ripples and inductor volt-second balance (IVSB))principle are used to design inductors.
The inductor current ripple equations are = V12L
δ1 TS
∆i L1modified V1 δ1
= 2L
1 to obtain
1 f S equations for inductor values (16)–(18).
V1 δ1 (16)
L1 = 2∆i f
V1L1δ1TS Vδ 
ΔiL1 = S
= 1)1 
∆i L2 2=L1 V22L δ2 T2 S L1 f S 
2  (16)
(17)
V δ1 2 2V δ

L1 =L2 =1 2∆i f

L2 S
2ΔiL1 f S 
δ1 (1−δ2 ) V1 TS δ2 (δ2 −δ1 ) V2 TS
∆i L0 = (1−δ ) L0 + (1−δ ) L0 
δ (1−δ2 ) V1 V2δ δ22T(Sδ2
1 1 (18)
−δ1 ) V2
L0 = 1(1−δ Δ i = +
1 ) ∆i
2 L2 1
(1−δ ) ∆i L0 f S

L 2L0 f S

The values of the inductors can be found, if output voltage, (17)

source voltages, desired ripples,
V2δ 2 
switching frequency and duty cycle are known. L2 =
2ΔiL 2 f S 
3.3. Voltage Ripples of Capacitors
Voltage ripples and the capacitor charge-second balance (CCSB) principle are used to design
capacitors. The voltage ripple equations are modified to obtain equations for capacitor values (19)–(21).

(1−δ1 ) TS 2(δ1 −1)

)
∆V1 = C1 δ1 R V0
(1−δ1 ) 2(δ1 −1) (19)
C1 = ∆V1 f S δ1 R V0
Electronics 2019, 8, 214 9 of 18

 
(1−δ2 ) TS δ12
∆V2 = RC2 (1−δ1 )
δ1 δ2
2(δ1 −1)
− 2(δ1 −1)
− δ2 + δ1
2 V0
  (20)
(1−δ2 ) δ1 δ2 δ12
C2 = R∆V2 f S (1−δ1 ) 2(δ1 −1)
− 2(δ1 −1)
− δ2 + δ21 V0

Output capacitor can be determined from the output voltage ripple.

∆i L0 TS
∆V0 = 8C0
∆i L0 (21)
C0 = 8∆V0 f S

The values of the capacitors can be found if the output voltage, source voltages, desired ripples,
switching frequency and duty cycle are known. A 5% current ripples in inductors, 5% voltage ripples
in buffer capacitor C1 and 4% voltage ripples in output capacitor C0 have been considered to design the
parameters listed in Table 2. The converter is simulated and various current and voltage waveforms
are presented in Figure 9a–j.

Table 2. Components of the proposed converter.

Sl.No Component Symbol Simulation Hardware

1 Inductors L1 and L2 0.8 & 1.51 mH 1 & 1.5 mH
2 Capacitors C1 and C2 46.3 µF & 63 µF 50 µF, 63 V & 72 µF, 50 V
3 Output Inductor L0 2 mH 2 mH
4 Output Capacitor C0 1.7 µF 2.2 µF, 35 V
5 Load Resistance R 5.76 Ω 6Ω
6 Switching Frequency fsw 20 kHz 20 kHz
Electronics 2019, 8, x FOR PEER REVIEW 10 of 20

Figure 9. Waveforms of various voltages and currents during mode 2 (a,f) Gate signal to S1, (b,g) Gate
Figure 9. Waveforms of various voltages and currents during mode 2 (a,f) Gate signal to S1 , (b,g) Gate
signal to S2, (c) Voltage across capacitor C1, (d) Voltage across capacitor C2 (e) Current through the
signal to S2 , (c) Voltage across capacitor C1 , (d) Voltage across capacitor C2 , (e) Current through the
inductor i3 (h) Output voltage (i) Current through the inductor L1 (j) Current through the inductor L2.
inductor i3 , (h) Output voltage (i) Current through the inductor L1 , (j) Current through the inductor L2 .
3.4. Small-Signal Modeling
Voltage regulation should be maintained in spite of the changes in input and output parameters
in any power converter, which necessitates a design of feedback controller. Modeling plays a good
role in providing information about the dynamic behavior of the converter and in deriving a feedback
control system. Numerous modeling methods have been proposed for power electronic converters.
The State-Space Averaging (SSA) method is the most commonly used method to design control loops
and to investigate the transient and steady state response of the converter. This modeling method has
Electronics 2019, 8, 214 10 of 18

3.4. Small-Signal Modeling

Voltage regulation should be maintained in spite of the changes in input and output parameters
in any power converter, which necessitates a design of feedback controller. Modeling plays a good
role in providing information about the dynamic behavior of the converter and in deriving a feedback
control system. Numerous modeling methods have been proposed for power electronic converters.
The State-Space Averaging (SSA) method is the most commonly used method to design control loops
and to investigate the transient and steady state response of the converter. This modeling method has
three steps: (1) writing the state-space equations for all states in a switching cycle; (2) derivation of
average state-space equation; and (3) applying perturbations to the averaged equation to derive the
linear first order small-signal equations, from which different transfer functions relating the inputs
and outputs can be obtained. Then, matrices A and B are formed, which describe the converter model.
The derived model fits in the following form (22).
. )
X = AX + BU
(22)
Y = CX + DU
.
where X, U, Y and x = dx/dt represent the state vector, the input or control vector, the output vector and
the derivative of X respectively. Matrices A, B, C and D are the system, control, output and feed-forward
matrices respectively. A and B are used to extract various transfer functions of the system.
h iT
X= i L1 i L2 i L3 vC1 vC2 v0 (23)

h iT
U= V1 V2 (24)

Y = [V0 ] (25)

From the Equation (4) in Section 2 and according to circuit theory, the dynamic equations
representing state-1 can be written as follows

L1 didtL1 = V1 , L2 didtL2 = V2



L0 didtL0 = V0 − VC1


(26)
C1 dvdtC1 + C2 dvdtC2 = i L0 

C0 dv

dt = i L0 − i0
0


The derived dynamic equations representing state-2 and state-3 are given in (27) and (28) respectively.

L1 didtL1 = V1 − VC1 + VC2




L2 didtL2 = V2 , L0 didtL0 = V0 − VC2


(27)
C1 dvdtC1 = i L1 , C2 dvdtC2 = i L0 − iC1 

C0 dv

dt = i L0 − i0
0


L1 didtL1 = V1 − VC1



L2 didtL2 = V2 − VC2 , L0 didtL0 = V0


(28)
C1 dvdtC1 = i L1 , C2 dvdtC2 = i L2 

C0 dv

dt = i L0 − i0
0

Electronics 2019, 8, 214 11 of 18

The obtained state space model in matrix form is given in (29).

 
di L1  δ1 −1 (δ2 −δ1 )
 0 0 0 L L 0 
i L1
  1
0

dt 1 1 L1
di L2 
 −(1−δ2 )  1
 dt
 0 0 0 0 L2 0  i L2   0 L2

di L3  −δ1 −(δ2 −δ1 )
      
− 1 


dt
 0 0 0 L L L
i L0   0  V1
0 
dvC1  = 
   0 0 0  +
1−δ1 −δ1 vC1
0 0 0 0 0  V2
0 
   
dt
 −(δC2 −1 δ1 ) 1−δ2 δ2 −δ12C1 δ1
     
dvC2  vC2 0 0 
C2 − 2C2

0 0 0 
  
dt  C2 C2
dv0 1 −1 v0 0 0
dt 0 0 C0 0 0 RC0
 
i L1
# i L2  "
 
" # " #" #
V0 0 0 0 0 0 1  i L0   0 0 V1
= + (29)

I0 0 0 0 0 0 R1  vC1  0 0 V2

 
Electronics 2019, 8, x FOR PEER REVIEW  VC2  12 of 20
V0
Using (29) with the obtained model, the transfer functions are derived and shown in (30)–(32).
Using (29) with the obtained model, the transfer functions are derived and shown in (30)–(32).
T = C [ SI − A] B + D
−1
(30)
−1
T = C [SI − A ] B+D (30)
V0 −8.889 × 1010 s 2 − 9.877 ×1019
= 6 (31)
V0 V1 s + 41.67 s 5 + 9.406 × 107 −
s 48.889
+ 3.919
× 10 10 s92s−
× 10 3
+9.877 101915 s 2 + 8.711× 1016 s + 3.951× 101
2.092××10
= (31)
V1 s6 + 41.67s5 + 9.406 × 107 s4 + 3.919 × 109 s3 + 2.092 × 1015 s219+ 8.711 × 1016 s + 3.951 × 1019
12 2
V 1.333 ×10 s − 3.556 ×10
V0 0
= 1.333 × 1012 s29 −3 3.556 × 101915 2 (32)
= V62 s 6 + 41.67 s 5
+ 9.406 × 10 7 4
s + 3.919 ×10 s + 2.092 × 10 s + 8.711×1016 s + 3.951× 1019 (32)
V2 s + 41.67s5 + 9.406 × 107 s4 + 3.919 × 109 s3 + 2.092 × 1015 s2 + 8.711 × 1016 s + 3.951 × 1019
These transfer functions are evaluated using MATLAB commands to eliminate manual mistakes,
These transfer
and the step functionsisare
data analysis evaluated
obtained. using
Figure 10 MATLAB
illustratescommands to eliminate
the response manual
of the plant mistakes,
to a unit step
and the
input. step data analysis is obtained. Figure 10 illustrates the response of the plant to a unit step input.

(a) (b)
Figure10.
Figure 10.Step
Stepresponse
responseof
ofopen
open loop
loop system
system (a)
(a) with V11 source
sourceand
and(b)
(b)with
withVV2 2source.
source.

Figure 10a,b
Figure 10a, 10b depicts
depicts thethe
stepstep response
response ofofthe
theconverter
converterwith
withstep
step change
change in input
input sources
sourcesVV1 1
andVV22 respectively.
and respectively. It
It is
is clear
clear that
that the
the response
response isis inverted
inverted as
as the
the Cuk
Cuk converter
converterhashasananinverted
inverted
output.The
output. Thesteady
steady state
state value
value settles
settles at
at −
−0.6674
0.6674ininFigure
Figure10a
10aand
andhashasananerror
errorofof33.26%
33.26%with
withaapeak
peak
overshoot of 62.7284%. In Figure 10b,
overshoot of 62.7284%. In Figure 10b, the the response settles at −0.9993
−0.9993 and has an error of 0.7% withaa
and has an error of 0.7% with
peakovershoot
peak overshootof of62.64644%.
62.64644%.

4.4.Design
Designof
ofController
Controller
The
Themost
mostpopular
popular proportional
proportional plus integral (PI) controller
integral (PI) controller has
has been
beendesigned
designedto
toeliminate
eliminatethe
the
steadystate
steady state error
error pointed
pointed in Figure
Figure.10.
10. One
One can obtain the proportional
proportional and
andthe
theintegral
integraloutput
outputasas
givenin
given in(30).
(30).
Ztt
out ==KK pee(( tt )),,IIout =
PPout out = K i  e ( t )dt
Ki e(t)dt (33)
p (33)
00

Ziegler–Nichols PI tuning was adopted to obtain the values of the proportional gain Kp and
integral time Ti. The S-shaped waveform can be defined by two parameters, delay time L and time
constant T as illustrated in Figure 11a.
Electronics 2019, 8, 214 12 of 18

Ziegler–Nichols PI tuning was adopted to obtain the values of the proportional gain Kp and
integral time Ti . The S-shaped waveform can be defined by two parameters, delay time L and time
Electronics 2019, 8, x FOR PEER REVIEW 13 of 20
constant T as 8,illustrated
Electronics 2019, x FOR PEERinREVIEW
Figure 11a. 13 of 20

(a) (b)
(a) (b)
Figure 11.(a)
(a) Sshaped
shaped curve.(b)
(b)Control
Controlwith
with PIcontroller.
controller.
Figure 11. (a) S
Figure 11. S shaped curve.
curve. (b) Control with PI
PI controller.

The designed
The designed PI controller has
controllerhas been
hasbeen incorporated
beenincorporated
incorporated with
with the plant as as
shown in Figure 11b. The
The designed PI controller with thethe
plantplant
as shownshown in Figure
in Figure 11b. 11b.
The
parameters
The of the
parameters of controller
the cancan
controller be obtained
be as given
obtained as in (34)
given in (34)
parameters of the controller can be obtained as given in (34)
 11  TT L L 
  
PIcontroller ==KK  1 T L 
= Kppp11++TTi SS,,KK
PIcontroller 1+ , K P P==0.90.9 =i =
, Ti, T (34)
(34)
PIcontroller = 0.9L , T =
L i 0.30.3 (34)
 Ti Si  0.3 
P
L
Figure 12a,b show the step response of the converter with PI controller for the step change in
Figure 12a, 12b show the step response of the converter with PI controller for the step change in
inputFigure
sources 12a,
V 12b
andshow the step response
V respectively. of the
The steady converter
state error is with PI controller
reduced for theof
and overshoots step change
0.0013% in
and
input sources V1 1 and V22 respectively. The steady state error is reduced and overshoots of 0.0013% and
input sources V and V respectively. The steady state error is reduced and overshoots
0.0068% are achieved. To make both sources work effectively, with the magnitude of input voltage
1 2 of 0.0013% and
0.0068% are achieved. To make both sources work effectively, with the magnitude of input voltage
0.0068%
V > V , theare duty
achieved.
cycle To make bothas
is considered sources
δ < δ work
. effectively, with the magnitude of input voltage
V1 1 > V22, the duty cycle is considered as δ11< δ2.2
V1 > V2, the duty cycle is considered as δ1 < δ2.

(a) (b)
(a) (b)
Figure 12. Step response of the system in closed loop (a) with V1 source and (b) with V2 source.
Figure12.
Figure 12. Step
Step response
responseof
ofthe
thesystem
systemin
inclosed
closedloop
loop(a)
(a)with
withVV11 source and (b)
(b) with
with V
V22 source.
source.

5. Resultsand
5. and Discussion
5. Results
Results and Discussion
Discussion
AA 100W, W, 20kHzkHz NI-TPCconverter
converter usingMOSFET
MOSFET switcheswas was fabricatedininthe the laboratory
A 100
100 W, 2020 kHz NI-TPC
NI-TPC converter usingusing MOSFET switches
switches was fabricated
fabricated in the laboratory
laboratory
(Figure
(Figure 13.) with the designed values. The whole system consists of the developed converter, two DC
(Figure 13.) with the designed values. The whole system consists of the developed converter, two
13.) with the designed values. The whole system consists of the developed converter, two DC
DC
power sourcesrepresenting
power representing therenewable
renewable energysources
sources suchasasPV PV andfuelfuel cell,aaFPGA
FPGA spartan6
power sources
sources representing the the renewable energy
energy sources such
such as PV and and fuel cell,
cell, a FPGA spartan6
spartan6
controller board,
controller and a resistive load. Triggering signals for the switches and the controller are
controller board,
board,andanda resistive
a resistiveload. Triggering
load. signals
Triggering for the
signals forswitches and theand
the switches controller are realized
the controller are
realized
using FPGAusing FPGA
Spartan Spartan 6 controller board. The specifications of components used are listed in
realized using FPGA6Spartan
controller board. The
6 controller specifications
board. of components
The specifications used are listed
of components in Table
used are listed2.in
Table 2.
Table 2.
Electronics 2019, 8, 214 13 of 18
Electronics 2019, 8, x FOR PEER REVIEW 14 of 20

Electronics 2019, 8, x FOR PEER REVIEW 14 of 20

Figure13.
Figure 13. Hardware
Hardware setup.
setup.

Experiments
Experiments have havebeenbeen conducted
conducted Figure
using13. the
using Hardware
the proposed
proposed setup.NI-TPC
NI-TPC converter
converter with an 18
with anV18input V input
voltage. Duty ratios of 60% and 40% were chosen for the boost
voltage. Duty ratios of 60% and 40% were chosen for the boost and buck operations respectively.and buck operations respectively. The
Experiments
results are shownhave been 14
in Figures conducted
and 15. Also, usingthethe
testproposed NI-TPC converter
has been performed with 12 Vwith
input anvoltage
18 V inputand
The voltage.
results areDuty
shown in Figures 14 and 15. Also, the test has been performed withrespectively.
12 V input The voltage
observed thatratios of 60% and 40%
the performance were chosen
is satisfying for the boost
the theoretical and buck
analysis. operations
However, these results are not
and results
observed that
are shown the performance is satisfying the theoretical analysis. However,
in Figures 14 and 15. Also, the test has been performed with 12 V input voltage and these results are not
provided in this paper.
provided
observedin this
Figure paper.
that14atheshows
performance
the current is satisfying the theoretical
through inductors L1, L2analysis.
and the loadHowever,
current these results
I0 along with aregate
not
Figure
provided 14a shows
in this
signal applied paper.
under the current
boost operation.through
It caninductors
be seen thatL1the , Lcurrent
2 and the loadofcurrent
ripples inductors I0 Δi
along with
L1, ΔiL2 and gate
signalload
applied
Figure
current under
14a areboost
Δi0shows theoperation.
current
in between It can
(5.9 through
A, 5.3 be seen
A, 3.4that
A),inductors
(4.3 L
A) Lthe
1, and2 andcurrent
(4.2 the ripples
load
A, 3.4 A) current of Iinductors
0 along
respectively. Thewith ∆igate
averageL1 , ∆iL2
signal
and load applied
valuescurrent ∆i0 are in
under
and ripples boost operation.
inclose
between It can be
(5.9 A, 5.3
approximation seen
with that the
A),the(4.3
5.55A,current
A,3.4
3.71A)ripples
A, and of inductors
(4.2AA,
and 3.6 Δi ,
3.4 A) from
calculated L1 Δi and
respectively.
L2 (2)
The load
andcurrent
average TheΔivoltage
(3). values 0 are
andinripples
between
across the
are(5.9inA, 5.3 A),
capacitors
close C1(4.3
andA, C23.4
approximation A) and
along with(4.2
with A,5.55
gate
the 3.4 A)
signal respectively.
A, are
3.71shown
A, and The
in 3.6 Aaverage
Figure 14b.
calculated
fromvalues
From and
(2) andFigureripples
(3). Theare
14b, theinaverage
voltage close approximation
acrossvoltages acrosswith
the capacitors thethe 5.55 A, 3.71
Ccapacitors are A,
44 and
V and3.6 −26.2V
A calculated
1 and C2 along with gate signal are shown in
whichfrom are in (2)
agreement
and (3). The with the
voltage theoretical
across the calculations
capacitors C1 from
and C(1) and
2 along (2).
withThe generated
gate
Figure 14b. From Figure 14b, the average voltages across the capacitors are 44 V and −26.2 V which are signal gate
are signal
shown in and source
Figure 14b.
and output
From Figurevoltages
14b, theare 15V, 18V,
average and −26.2V,
voltages acrossrespectively,
the capacitors as shown
are 44inVFigure
and 14c.
−26.2V which are in
in agreement with the theoretical calculations from (1) and (2). The generated gate signal and source
agreement with the theoretical calculations from (1) and (2). The generated gate signal and source
and output voltages are 15 V, 18 V, and −26.2 V, respectively, as shown in Figure 14c.
and output voltages are 15V, 18V, and −26.2V, respectively, as shown in Figure 14c.

(a)

(a)

(b) (c)
Figure 14. Various voltage and current measurements from experiments during Mode 1 with source
(b)signal, inductor currents through L1, L2 and Load current
1 (Boost mode): (a) Gate (c) (CH 1–4); (b) Gate
signal and capacitor voltages across C1 and C2 (CH 1–3); (c) Gate signal, source voltages and output
Figure
Figure 14. 14.
voltage Various
Various
(CH voltage
voltage
1–3). andand currentmeasurements
current measurements from
from experiments
experiments during
duringMode
Mode1 with
1 withsource
source 1
1 (Boost mode): (a) Gate signal, inductor currents through L1, L2 and Load current (CH 1–4); (b) Gate
(Boost mode): (a) Gate signal, inductor currents through L1 , L2 and Load current (CH 1–4); (b) Gate
signal
signal andand capacitor
capacitor voltages
voltages acrossCC1and
across and C
C2 (CH 1–3); (c) Gate signal, source voltages and output
1 2 (CH 1–3); (c) Gate signal, source voltages and output
voltage (CH 1–3).
voltage (CH 1–3).
A, under step down mode, which are closer to 1.39 A, 2.08 A, and 2.08 A calculated from (2) and (3).
The corresponding ripples ΔiL1, ΔiL2 and Δi0are within (1.55, 1.25 A), (2.4 and 2.0 A) and (2.3 and 2.1
A) respectively. It is found that the ripples are slightly more than the designed value of 5%. The
voltage ripples of the capacitor are shown in Figure 15b. It can be seen that the ripples of capacitors
are within
Electronics (28.8,
2019, 29.55 V) for C1 and (11.0 to 11.4 V) for C2. The gate signal, source and output voltages
8, 214 14 of 18
are 15V, 18V and −11.2V respectively, as shown in Figure 15c.

(a)

(b) (c)
Figure 15. Various voltage
voltage and
and current
currentmeasurements
measurementsfromfromexperiments
experimentsduring
duringMode
Mode1 1with
withsource
source1
1 (Buckmode):
(Buck mode):(a)
(a)Gate
Gatesignal,
signal,inductor
inductorcurrents throughLL1 ,1,LL22 and
currentsthrough and load current (CH 1–4); (b) Gate
signal and capacitor voltages across C11 and
and C
C22 (CH
(CH 1–3);
1–3); (c)
(c) Gate
Gate signal,
signal, source voltages and output
voltage (CH 1–3).

Figure
The 15a showsofthe
performance thecurrent
converterthrough the inductors
was tested L1, L2 and
in DISO mode andtheload current 1.4 A,voltage
corresponding 2.2 A and
2.17 A, under
current signalsstep down mode,
are shown in Figure which are current
16. The closer tothrough
1.39 A,the2.08inductors
A, and 2.08 A calculated
L1 and L3 with gate from (2)
signal
and (3). The corresponding ripples
applied to both the switches are shown ∆i , ∆i and
L1in Figure
L2 ∆i are within (1.55, 1.25 A), (2.4 and 2.0
16a.0 The inductor currents iL2 and i0 are shown in A) and
(2.3
Figureand16b.
2.1 It
A)can
respectively.
be observed It is found
that that theinductor
the average ripples are slightly
currents aremore than the
matching withdesigned value(3),
results from of
5%. and
(14) The voltage
(15) andripples
ripplesofaretheslightly
capacitormore arethan
showntheindesigned
Figure 15b.
value It can be seen
of 5%. that the across
The voltage ripplesthe
of
capacitors C are within
1 and (28.8,
C2 are 40 V29.55
andV) 34for C1 and (11.0as
V respectively toshown
11.4 V)infor C2 . The
Figure 16c.gate signal,
It can source
be seen thatand
the
output voltages
ripples are 15
of capacitors areV, within
18 V and −11.2
(36.5 V respectively,
V, 44.5 V) for C1 and as(31.5
shown to in
39 Figure
V) for C15c.
2. The obtained voltage

ripplesThe(approximately
performance of10%) the converter
are more was thantested in DISO value
the designed mode (5%).
and the corresponding
However, voltage
it can be and
observed
current
that the signals
currentare shown
of all in Figure
the ports, 16.and
IL1, IL2 TheI0current throughwith
are continuous the inductors L1 and L3 with gate signal
less ripples.
applied to both the switches are shown in Figure 16a. The inductor currents iL2 and i0 are shown
in Figure 16b. It can be observed that the average inductor currents are matching with results from
(3), (14) and (15) and ripples are slightly more than the designed value of 5%. The voltage across the
capacitors C1 and C2 are 40 V and 34 V respectively as shown in Figure 16c. It can be seen that the
ripples of capacitors are within (36.5 V, 44.5 V) for C1 and (31.5 to 39 V) for C2 . The obtained voltage
ripples (approximately 10%) are more than the designed value (5%). However, it can be observed that
the current of all the ports, IL1 , IL2 and I0 are continuous with less ripples.
The response of the converter during transient load condition is shown in Figure 17. The load is
varied to increase the load current from 0.6 A to 3.8 A. Approximately 20 s later, the load decreased to
0.8 A from 3.8 A. In both the cases, it is observed that the load voltage is regulated at 23.9 V which is
closer to the desired value of 24 V. The load voltage magnitude is shown positive by using the probe
with opposite polarity.
Electronics 2019, 8, 214 15 of 18
Electronics 2019, 8, x FOR PEER REVIEW 16 of 20

(a) (b)

(a) (b)

(c)

Figure 16. Various voltage and current measurements from experiments during Mode 2 with both
sources: (a) Gate pulses of both switches and inductor currents through L1 and L3 (CH 1–4); (b) Gate
pulses of switches, inductor currents through L2 and L0 (CH 1–4); (c) Gate signals of S1 and S2, and
capacitor voltages across C1 and C2 (CH 1–4).

(c)
The response of the converter during transient load condition is shown in Figure 17. The load is
varied Figure
Figure 16.16.
to increase Various voltage
thevoltage
Various load andcurrent
current
and current measurements
frommeasurements
0.6 A to 3.8 fromfrom experiments
experimentsduring
A. Approximately Mode
Mode2 2with
20 seconds
during both
later,
with the load
both
sources:
decreased to (a)
0.8 Gate
A pulses
from 3.8of
A.both
In switches
both theand inductor
cases, it is currents
observed through
that L
the1 and L
load3 (CH 1–4);
voltage
sources: (a) Gate pulses of both switches and inductor currents through L1 and L3 (CH 1–4); (b) Gate (b)
is Gate
regulated at
pulses
23.9 pulses
V which of
of is switches
switches , inductor currents through L2 and L0 (CH 1–4); (c) Gate signals of S1 and S2, and
closer, to the desired
inductor value
currents of 24 L
through V.2 The
and L load voltage magnitude is shown positive
S2 , by
0 (CH 1–4); (c) Gate signals of S1 and
capacitor
usingand
the probevoltages
capacitor with across
opposite
voltages C1 and
across C2 (CH
polarity.
C1 and 1–4).1–4).
C2 (CH

The response of the converter during transient load condition is shown in Figure 17. The load is
varied to increase the load current from 0.6 A to 3.8 A. Approximately 20 seconds later, the load
decreased to 0.8 A from 3.8 A. In both the cases, it is observed that the load voltage is regulated at
23.9 V which is closer to the desired value of 24 V. The load voltage magnitude is shown positive by
using the probe with opposite polarity.

Figure 17.
Figure 17. Voltages
Voltages and
and currents
currentsfrom
fromthe
the experiment
experimentduring
duringtransient
transientcondition.
condition. Input
Input voltage,
voltage, input
input
current, load
current, load voltage
voltageand
andcurrent
current(CH
(CH1–4).
1–4).

Figure 18a,b
Figure 18a, present
18b present the comparison
the comparison plot the
plot between between the simulation
theoretical, theoretical,andsimulation and
experimental
experimental absolute values of voltage gains as a function of duty ratio for SISO and
absolute values of voltage gains as a function of duty ratio for SISO and DISO modes, respectively. DISO modes,
Figure 17. Voltages and currents from the experiment during transient condition. Input voltage, input
respectively.
It is obvious It is obvious
that both thethat both theand
theoretical theoretical and experimental
experimental voltage gainsvoltage gains are increasing
are increasing as
as the duty
current, load voltage and current (CH 1–4).
ratio increases. In addition, the voltage gain obtained from the experiment closely approximates
the theoretical and the
Figure 18a, 18bsimulation results
present the between plot
comparison 0.3 and 0.5, whereas
between a slight deviation
the theoretical, hasand
simulation been
observed in the duty ratio beyond 0.5 with increasing voltage difference. It is worth mentioning
experimental absolute values of voltage gains as a function of duty ratio for SISO and DISO modes, that
thisrespectively.
difference isIt due to the component
is obvious that both thelosses.
theoretical and experimental voltage gains are increasing as
Electronics 2019, 8, x FOR PEER REVIEW 17 of 20

the duty ratio increases. In addition, the voltage gain obtained from the experiment closely
approximates the theoretical and the simulation results between 0.3 and 0.5, whereas a slight
Electronics
deviation has8, 214
2019, 16 of
been observed in the duty ratio beyond 0.5 with increasing voltage difference. It 18
is
worth mentioning that this difference is due to the component losses.

(a) (b)

Figure 18. Voltage gain as

Voltage gain as aa function
function of
of duty
duty cycle
cycle (a)
(a) SISO
SISO mode
mode (b)
(b) DISO
DISO mode.
mode.

Thus,
Thus, the results
results validate
validate the
the theoretical
theoretical analysis
analysis and
and show
show thethe good
good feasibility
feasibility of
of expected
expected
operation. Several tests
operation. Several tests are conducted and the maximum efficiency between the modes modes hashas been
been
compared
comparedand andplotted
plottedinina graph
a graphas as
shown
shownin Figure 19, and
in Figure 19, the
andobserved
the observedefficiencies for Mode
efficiencies for 1Mode
(SISO)1
with
(SISO)V1 with
and VV2 1sources
and Vare 92.74%are
2 sources and92.74%
91.15% respectively,
and 91.15% and for Mode 2and
respectively, is 90.43%.
for ModeComparing with
2 is 90.43%.
efficiencies
Comparingobtained through simulation,
with efficiencies obtained efficiencies for Mode 1 efficiencies
through simulation, (SISO) with individual
for Mode contribution
1 (SISO) with of
V 1 and V2 sources
individual are 94.13%
contribution of V1 and
and 93.66%, respectively,
V2 sources are 94.13% and
andfor93.66%,
Mode 2respectively,
is 92.21%. Table
and3forpresents
Mode the
2 is
comparison
92.21%. Table of various TP-NI
3 presents theconverters
comparison with
of the proposed
various TP-NIone. It is clearwith
converters that the proposed
proposed converter
one. It is
provides
clear that continuous
the proposed current at all the
converter ports with
provides a reduction
continuous in components.
current at all the ports with a reduction in
Electronics 2019, 8, x FOR PEER REVIEW 18 of 20
components.
Table 3. Comparison of converters.

The
Circuit
[5] [10] [22] [30] [31] Proposed
Elements
Converter
Nonisolate Nonisolate Nonisolate Nonisolate Nonisolate Nonisolate
Topology
d d d d d d
Inductors 2 3 2 2 2 coupled 3
Capacitors 3 4 3 1 3 3
Active
4 3 3 4 5 2
switches
Diodes 2 Figure 19.
Figure 19. Maximum efficiency
1 Maximum efficiency
4 for various
for various modes.
2 modes. Nil 1
Common Table 3. Comparison
6. Conclusion Yes Yes Yes of converters. Yes Yes Yes
ground
In this paper a NI-TPC ThetoProposed
Continuou
Circuit Elements [5]converter is [10]synthesized[22]using conventional
[30] Cuk [31]
converters interface
Converter
RS like Fuel
s current at cell and PV source. The operational modes and analysis of the converter are discussed
Topology No Yes No No No Yes
in detail.
all the Fewer active Nonisolated
and passive Nonisolated
components Nonisolated
and a sharedNonisolated
output inductorNonisolated Nonisolated
are the advantages of
Inductors 2 3 2 2 2 coupled 3
this ports
converter.
Capacitors The continuous3 input and 4 output currents
3 are achieved
1 owing 3 to the presence
3 of
Active switches
inductors.
Prototype 4
Therefore, this converter 3
is appropriate for3FC power supplies 4 5
that necessitates 2
continuous
Diodes 400 W 2 1.2 kW 1 200 W4 1 kW 2 200NilW 100
1 W
current
rating
Common
withground
low ripple. The
Yes
simulationYes and experimental
Yes
results Yes
are providedYes to verify the feasibility
Yes
ofSwitching
the proposed
Continuous converter.
current at
No 100 kHzYes No No 50 No 20Yes
all the ports 100 kHz 40 kHz 20 kHz kHz kHz
frequency
Author Contributions:
Prototype rating Formal
400 W Analysis, B.C.;
1.2 kW Investigation,
200 W B.C.; Methodology,
1 kW B.C.;
200 W Resources,
100 W C.N.;
Maximum
Supervision, C.N.; Validation,
Switching frequency C.N.; Writing—Original
100 kHz 100 kHz Draft,
40 kHzB.C.; Writing—Review
20 kHz 50&kHz
Editing, B.C., C.N., and
20 kHz
Maximum efficiency96% 96%
efficiency
S.S.D.
93.5%93.5% 92.7%92.7% 95.5%
95.5% 90.1%
90.1% 94.13%
94.13%

Funding: This research received no external funding.

Acknowledgements: The authors would like to thank SRM IST, Kattankulathur, India for the financial support
in executing this work successfully. This work has been carried out as a part of research work in the Department
of Electrical and Electronics Engineering, SRM IST, Kattankulathur, India.

Conflicts of Interest: The authors declare no conflicts of interest.

References
Electronics 2019, 8, 214 17 of 18

6. Conclusions
In this paper a NI-TPC converter is synthesized using conventional Cuk converters to interface
RS like Fuel cell and PV source. The operational modes and analysis of the converter are discussed in
detail. Fewer active and passive components and a shared output inductor are the advantages of this
converter. The continuous input and output currents are achieved owing to the presence of inductors.
Therefore, this converter is appropriate for FC power supplies that necessitates continuous current
with low ripple. The simulation and experimental results are provided to verify the feasibility of the
proposed converter.

Author Contributions: Formal Analysis, B.C.; Investigation, B.C.; Methodology, B.C.; Resources, C.N.; Supervision,
C.N.; Validation, C.N.; Writing—Original Draft, B.C.; Writing—Review & Editing, B.C., C.N., and S.S.D.
Funding: This research received no external funding.
Acknowledgments: The authors would like to thank SRM IST, Kattankulathur, India for the financial support in
executing this work successfully. This work has been carried out as a part of research work in the Department of
Electrical and Electronics Engineering, SRM IST, Kattankulathur, India.
Conflicts of Interest: The authors declare no conflicts of interest.

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