Verilog HDL Basics What is Verilog? IEEE industry standard Hardware Description Language (HDL) used to describe a ital system 1 Use in both hardiare simulation & synthase Course Outline '=Verlog HOL Overview ‘Basie Stucture ofa Verlog HOL Model ‘= Componenis ofa Vetiog HDL Module ‘Assnng Vales and Nunbars Opernore 1+ Tesks and Functions facet sa. Verilog History + Induced in 1984 by Gateway Design Automation 11980 Cadence purchased Gateway (Veriog-XL simulator) +1990 Cadence released Verlog to the publc + Open Verlog Intemational (OV) was formed to contr the language specications 11995 OVI weased version 20 11905 IEEE accepted OVI Verlog asa standard, Verilog 1364 12001 IEEE revised standard 112008 IEEE accepted new revision for the standartVerilog HDL Terminology “HDL: A text based programming language that is used to moda a pece of hardware ' Behavior Modeling: A components described by its Inputiouput response 1 Structural Modeling: A component is descibad by interconnecting lower-level componentsiprmitives Structural Modeling 1 Functionality and stucture ofthe eruit ' Callout the specie hardware Behavior Modeling ‘Onl the functionality ofthe ccuit, no strecture 1 Synthesis tol creates corec loge ++ More Terminology 1 Register Transfer Level (RTL) A type of behavioral modioing, forthe purpose of synthesis. ~ Hardware is implied or inferred - Syihesizable 1 Syste: Translating HDL to cult and then optimizing the represontod cut S| RTL Synthesis: Translating a RTL mode of hardware ito ‘an optimized technology specific gate level implementationRTL Synthesis Verilog HDL Basics Typical RTL Synthesis & RTL Simulation Flows sas sd a — Ss = = sansa, log - Basic Modeling Structure es et ‘+ Taming spetieaon efor