INDEX

SWITCHING THEORY & LOGIC DESIGN

COURSE FILE

2018-19

Department of Electronics & Communications Engineering

SREYAS Institute of Engineering & Technology
Tattiannaram, Hyderabad.
 INDEX
CONTENTS OF COURSE FILE

S.NO TITLE REMARKS

1 Vision & Mission statements of Institute / Department/PEOs

2 POs & PSOs
3 Syllabus
4 Text books & Reference books/ WEB/ Journals/ Beyond Gaps
5 Course Objectives, Course Outcomes, CO-PO Mapping
6 Academic Calendar
7 Course schedule/Time Table
8 Course Plan
9 Question bank Mid
10 Tutorial
11 Assignments
12 Guest Lectures/Seminar/Field Visits
13 Remedial / Special Classes
14 List of Weak Students
15 Course Review/Completion Certificate
16 Course Material
17 Tutorial – Solutions – Evidence
18 Previous Question papers
19 Mid Question Papers (PDF) – Solution Samples
20 Assignment – solutions – sample scripts
21 Results Analysis
22 Course Assessment
 COURSE DESCRIPTION
Faculty Name Dr. Shaik . Fairooz
Designation Associate Professor
Department ECE
Batch 2017-21
Academic Year 2018-19
Year & Semester II-II
Section A, B

Course title SWITCHING THEORY AND LOGIC DESIGN

Course code EC401ES
Regulation R16
Course Duration 16 weeks
Lectures Tutorials Practical Credits
Course structure
3 0 0 3
Domain Lead Dr. Shaik. Fairooz
Team of Dr. Shaik Fairooz Mr G.Ramachandra -
instructors Kumar

Prerequisites Graduation Level Credits Periods/Week

1. Basic Engineering UG 4 4
Mathematics
2. Sets and Relations UG 4 4

Evaluation Scheme:
S.N Component Duration Marks
o
1 I - mid exam Descriptive – answer any 2 of 4 – (10) 80 Min 20
Objective –answer all 20 Questions–
(10)
2 I - Assignment - 05
3 II - Mid exam Descriptive – answer any 2 of 4 – (10) 80 Min 20
Objective –answer all – (10)
4 II - Assignment - 5
5 External exam 3 Hours 75

CO1-T CO2-T CO3-T CO4-T CO5-T CO6-T

Course Outcomes - Target
 VISION & MISSION
Institute Vision :

To be a centre of excellence in technical education to empower

the young talent through quality education and innovative
engineering for well being of the society.

Institute Mission :

1. Provide quality education with innovative methodology and

Intellectual human capital.
2. Provide conducive environment for research and
developmental activities.
3. Inculcate holistic approach towards nature, society and
human
ethics with lifelong learning attitude.

Department Vision :

To excel in Electronics & Communication Engineering education

with the knowledge of innovation, research and ethics.

Department Mission:

1. To provide academic environment that promotes student

centric learning through quality education and state of the
art infrastructure.

2. To make the students aspire towards innovation and

research to meet the technological needs of society.

3. To engage the students in activities which inculcate

professional practices with social concern.

Programme Educational Objectives :

1. Graduate will be empowered with strong fundamental

concepts, analytical capability, programming and problem
solving skills.

2. Graduates will be employed, may pursue higher education

or undertake research.

3. Graduates will embrace Professional Career Growth with

Values & Ethics and urge for lifelong learning.
 POs & PSOs
Program Outcomes
Engineering Knowledge: Apply the knowledge of mathematics, science,
PO 1 engineering fundamentals, and an engineering specialization to the
solution of complex engineering problems.
Problem analysis: Identify, formulate, review research literature, and
analyze complex engineering problems reaching substantiated
PO 2
conclusions using first principles of mathematics, natural sciences, and
engineering sciences.
Design/development of solutions: Design solutions for complex
engineering problems and design system components or processes that
PO 3 meet the specified needs with appropriate consideration for the public
health and safety, and the cultural, societal, and environmental
considerations.
Conduct investigations of complex problems: Use research-based
knowledge and research methods including design of experiments,
PO 4
analysis and interpretation of data, and synthesis of the information to
provide valid conclusions.
Modern tool usage: Create, select, and apply appropriate techniques,
resources, and modern engineering and IT tools including prediction and
PO 5
modeling to complex engineering activities with an understanding of the
limitations.
The engineer and society: Apply reasoning informed by the contextual
knowledge to assess societal, health, safety, legal and cultural issues and
PO 6
the consequent responsibilities relevant to the professional engineering
practice.
Environment and sustainability: Understand the impact of the
professional engineering solutions in societal and environmental contexts,
PO 7
and demonstrate the knowledge of, and need for sustainable
development.
Ethics: Apply ethical principles and commit to professional ethics and
PO 8
responsibilities and norms of the engineering practice.
Individual and team work: Function effectively as an individual, and as
PO 9
a member or leader in diverse teams, and in multidisciplinary settings.
Communication: Communicate effectively on complex engineering
activities with the engineering community and with society at large, such
PO 10 as, being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear
instructions
Project management and finance: Demonstrate knowledge and
understanding of the engineering and management principles and apply
PO 11
these to one’s own work, as a member and leader in a team, to manage
projects and in multidisciplinary environments.
Life-long learning: Recognize the need for, and have the preparation
PO 12 and ability to engage in independent and life-long learning in the broadest
context of technological change.
Program specific outcomes
PSO1 Design, Analyze and develop modules and systems for applications in advanced
electronics and communication systems.
Utilize modern tools for modeling and computational techniques in IC fabrication
PSO2
and RF technologies.
 SYLLABUS

EC612PE: DIGITAL IMAGE PROCESSING

B.Tech. III Year II Sem.
UNIT-1

Number System and Boolean Algebra And Switching Functions: Review of

Number Systems, Complements of Numbers, Codes- Binary Codes, Binary
Coded Decimal Code and its Properties, Unit Distance Codes, Alpha Numeric
Codes, Error Detecting and Correcting Codes.
Boolean Algebra: Basic Theorems and Properties, Switching Functions,
Canonical and Standard Form, Algebraic Simplification of Digital Logic Gates,
Properties of XOR Gates, Universal Gates, Multilevel NAND/NOR realizations.
UNIT-2

Minimization and Design of Combinational Circuits: Introduction, The

Minimization of switching functions using theorem, The Karnaugh Map Method
up to Five Variable Maps, Don’t Care Map Entries, Tabular Method, Design of
Combinational logic: Adder, Subtractors, Comparators, Multiplexers,
Demultiplexers, Decoders, Encoders and Code Converters, Hazards and Hazard
Free Relations.
UNIT-3

Sequential Machines Fundamentals and Applications: Basic Architectural

Distinctions between Combinational and Sequential circuits, The Binary Cell,
Fundamentals of Sequential Machine Operation, Latches , Flip-Flops: SR,JK,
race around condition in JK , JK Master Slave , D and T Flip-Flops, Excitation
of all Flip-Flops , Design of a Clocked Flip-Flop, Timing and Triggering
Consideration , Clock skew Conversion from one type of Flip-Flop to another.
Registers and Counters: Shift Registers, Data Transmission in Shift Registers,
Operation of Shift Registers, Shift Register Configuration, Bidirectional Shift
Registers, Applications of Shift Registers, Design and Operation of Ring and
Twisted Ring Counter, Operation Of Asynchronous And Synchronous Counters.
UNIT-4

Sequential Circuits - I: Introduction, State Diagram, Analysis of Synchronous

Sequential Circuits, Approaches to the Design of Synchronous Sequential Finite
State Machines , Synthesis of Synchronous Sequential Circuits, Serial Binary
Adder, Sequence Detector, Parity-bit Generator, Design of Asynchronous
Counters, Design of Synchronous Modulo N – Counters.
UNIT-5

Sequential Circuits: Finite state machine-capabilities and limitations, Mealy

and Moore models-minimization of completely specified and incompletely
specified sequential machines, Partition techniques and Merger chart methods-
concept of minimal cover table.
 TEXT/REF/WEB/JOURNALS/BEYOND
S.No. Text Books Publication
1 Switching and Finite Automata Theory- Zvi Kohavi & Niraj K. Cambridge
Jha, 3rd Edition, Cambridge
2 Digital Design- Morris Mano, PHI, 3rd Edition. PHI

S.No. Ref Books Publication

1 Modern Digital Electronics – R P Jain. CRC

2 Switching Theory and Logic Design-A. Anand Kumar,3 rd PHI

Edition,PHI,2013.

S.No. Web Link

1 http://nptel.ac.in/courses/117106086/8

2 http://www.nptel.ac.in/courses/106108099//Digital%20Systems.pdf

S.No. Journal
1 IEEE Transactions on VLSI Circuits.

S.No. Gaps in Curriculum

1 Mathematics sets and relations

S.No. Topics Beyond Syllabus

1 NPTEL-Switching Theory And Logic Design
2 Design of Programmable array logic and Programmable logic array.
 ACADEMIC CALENDAR

C201 Course Objectives

A To learn basic techniques for the design of digital circuits and fundamental
concepts used in the design of digital systems
B To understand common forms of number representation in digital electronic
circuits and to be able to convert between different representations
C To implement simple logical operations using combinational logic circuits
D To design combinational logical circuits, sequential logic circuits.
E To impart to student the concepts of sequential circuits, enabling them to
analyze sequential systems in terms of state machines.
F To implement synchronous state machines using flip-flops.

Course Outcomes
C201

At the end of the course Student will be able to:

1 Understand the number systems and algebraic simplification of digital logic
gates using Boolean Algebra.
2 Analyze of combinational circuits and to use standard combinational
functions /building blocks to build larger more complex circuits.
3 Design of sequential circuits and to use standard combinational functions
/buiding blocks to build larger more complex circuits .
4 Analyze the sequential circuits and to use standard building blocks to build
the application like registers and counters.
5 Evaluate the synchronous sequential circuits using state machines.

6 Analyze the sequential circuits using state minimization techniques.

 ACADEMIC CALENDAR

COURSE OBJECTIVES COs PROGRAM OUTCOMES (POs) PSOs

A B C D E F 1 2 3 4 5 6 7 8 9 10 11 12 I II
3 CO1 3 3 1 3 - - - - - - - - 3 -

3 CO2 3 3 1 3 - - - - - - - - 3 2

3 CO3 3 3 1 3 - - - - - - - - 3 2

3 CO4 3 3 1 3 - - - - - - - - 3 2

3 CO5 3 3 1 3 - - - - - - - - 3 2

3 CO6 3 3 1 3 - - - - - - - - 3 -

Signatur
e Signatur
Faculty e HOD
ACADEMIC CALENDAR
 COURSE SCHEDULE -TIME TABLE
COURSE SCHEDULE
Unit Total No.
S.No Description From To
No Periods
Number System and Boolean
1 I Algebra And Switching Functions
Boolean Algebra
Minimization and Design of
2 II
Combinational Circuits
Sequential Machines
3 III Fundamentals and Applications
Registers and Counters
4 IV Sequential Circuits - I

5 V Sequential Circuits - II

TIME TABLE

SEC-A 1 2 3 4 Break 5 6 7
MON
TUE
WED
THU
FRI
SAT

SEC-B 1 2 3 4 Break 5 6 7
MON
TUE
WED
THU
FRI
SAT

Signatur
e Signatur
Faculty e HOD
 GUEST LECTURES / SEMINARS / FIELD VISITS
B CO PO TEXT
Uni Cumulativ Planne Actual
Week Topic(s) to be covered T BOOK Remarks
t e Period d Date Date
L S
FIRST SPELL OF INSTRUCTION
1 Unit- I Number System and 1 1,2 1,2 T1,T2
Boolean Algebra And
Switching Functions -Binary
Number Systems, Base
Conversion
2 Octal Number Systems, Base 2 2 1,2 T1,T2
Week-1 Conversion
I Number System and Boolean Algebra And Switching Functions

3 Hexa-decimal Number 2 2 1,2 T1,T2

Systems, Base Conversion
4 Codes-Weighted codes, Non- 3 3 1,2 T1,T2
Weighted codes
5 Radix Complements of 3 3 1,2 T1,T2
Numbers
6 Diminished Radix 3 3 2 T1,T2
Complements of Numbers
7 Binary Coded Decimal Code 2 2 2 T1,T2
and its Properties
Week-2 8 Unit Distance Codes,Excess-3 3 2 1,2 T1,T2
code
9 Self-complementing codes, 3 3 2 T1,T2
parity bits
10 Hamming code, problems 4 4 1,2 T1,T2
11 Alpha Numeric Codes-ASCII 2 2 2 T1,T2
Week-3 Code
12 EBCDIC Code, problems 2 2 2 T1,T2
13 Basic Theorems and 2 2 2 T1,T2
Properties, Boolean function
14 Finding Duals, Complements, 3 2 1,2 T1,T2
Week-4 Simplification
15 Switching Functions, SOP 3 4 1,2 T1,T2
forms
16 POS forms 3 4 1,2 T1,T2
17 Algebraic Simplification of 3 4 2 T1,T2
Digital Logic Gates
Properties of XOR Gates, 3 3 2 T1,T2
Universal Gates
18 Multilevel NAND and NOR 4 4 2 T1,T2
realizations
Week-5 19 Tutorial 2 T1,T2
20 Unit-II Minimization and 2 2,3 2 T1,T2
Design of Combinational
Circuits -Introduction, The
Minimization with theorem
21 The Karnaugh` Map 3 4 2 T1,T2
Method,2-variable map
22 3-variable,4-variable maps 3 4 2 T1,T2
23 Five Variable K Maps 3 4 2 T1,T2
24 Five Variable K Maps 3 4 2 T1,T2
Week-6 25 Don’t Care Map Entries, 3 4 2 T1,T2
Using the Maps for
Simplifying
26 Tabular Method 3 4 2 T1,T2
Week-7 27 Tabular Method 3 4 2 T1,T2
28 Design of Combinational 5 5 2 T1,T2
Circuits
29 Arithmetic Circuits 5 5 2 T1,T2
30 Comparator, Multiplexers 5 5 2 T1,T2
31 Encoders, decoders 5 5 2 T1,T2
32 Code Converters 5 5 2 T1,T2
 GUEST LECTURES / SEMINARS / FIELD VISITS
33 Practical Aspects related to 4 3 2 T1,T2
Combinational Logic Design,
Hazards and Hazard Free
Relations
34 Unit-III Sequential Machine 2 1,2 2 T1,T2
Fundamentals and
Unit-III Sequential Machine Fundamentals and

Applications -Basic
Architectural Distinctions
Week-8 between Combinational
circuits
35 Sequential circuits, The 2 4 2 T1,T2
Binary Cell
Applications

36 Fundamentals of Sequential 2 4 2 T1,T2

Machine Operation
37 Latches and Flip-Flops 2 4 2 T1,T2
38 S-R Flip-Flop and its 3 4 2 T1,T2
excitation
39 J-K Flip-Flop , JK Mater 3 4 2 T1,T2
Slave and its excitation
40 D and T Flip-Flop and its 3 4 2 T1,T2 `
excitation
Week-9
41 Timing and Triggering 2 4 2 T1,T2
Consideration, Clock Skew
42 Conversion from one type of 3 4 2 T1,T2
Flip-Flop to other

43 TUTORIAL 2 T1,T2
44 Unit-III Registers and 2 2,3 2 T1,T2
Unit-III Registers and

Counters -Shift registers

and Data transmission in
Counters

Week- shift registers.

10 45 Shift Register configuration 3 4 2 T1,T2
46 Bidirectional Shift registers 3 4 2 T1,T2
47 Application of Shift registers 4 6 2 T1,T2
48 Design and operation of Ring 5 5 2 T1,T2
and Twisted Ring Counter
49 Operation of Asynchronous 3 4 2 T1,T2
Counters
50 Design of Synchronous 5 5 2 T1,T2
Modulo N – Counter
Week-
51 Tutorial 2 T1,T2
11 52 Tutorial 2 T1,T2
Tutorial 2 T1,T2
Unit-IV: Sequential Circuits- 2 2,3 2 T1,T2
I : Introduction , State
Diagram
53 Analysis of Synchronous 5 5 2 T1,T2
Sequential Circuits
Week- 54 Approaches to the design of 5 5 2 T1,T2
12 Synchronous Finite State
Machines
55 Synthesis of Synchronous 5 5 2 T1,T2
sequential circuits
56 Serial Binary Counter , 5 5 2 T1,T2
Sequence Detector
57 Parity –bit Generation 5 5 2 T1,T2
Design of Asynchronous 5 5 2 T1,T2
58
Counters
Week-
Design of Synchronous 5 5 2 T1,T2
13 59
Modulo –N Counters
60 Tutorial 2 T1,T2
61 Tutorial 2 T1,T2
62 Tutorial 2 T1,T2
 GUEST LECTURES / SEMINARS / FIELD VISITS
63 Unit-V Sequential Circuits : 2 2,3 2 T1,T2
Finite state machine-
capabilities and limitations
64 Mealy and Moore models- 2 4 2 T1,T2
65 Minimization of completely 5 5 2 T1,T2
Unit-V Sequential Circuits

Week- specified and incompletely

14 specified sequential machines
66 Minimization of completely 5 5 2 T1,T2
specified and incompletely
specified sequential machines
67 Minimization of completely 5 5 2 T1,T2
specified sequential machines
68 Minimization of completely 5 5 2 T1,T2
Week- specified sequential machines
15 69 Partition techniques 5 5 2 T1,T2
70 Partition techniques 5 5 2 T1,T2
71 Merger chart methods 5 5 2 T1,T2
72 Merger chart methods 5 5 2 T1,T2
73 concept of minimal cover 5 5 2 T1,T2
Week- table
16 74 concept of minimal cover 5 5 2 T1,T2
Unit-V Sequential Circuits

table
75 University Questions Papers
Solvong
77 University Questions Papers
Solvong
78 University Questions Papers
Week- Solvong
17 79 University Questions Papers
Solvong
80 University Questions Papers
Solvong

Signatur
e Signatur
Faculty e HOD

B CO PO Text
Cumulative Planned Actual
Unit Week Topic(s) to be covered T Remarks
Period Books Date Date
L

FIRST SPELL OF INSTRUCTION

 GUEST LECTURES / SEMINARS / FIELD VISITS
1 Unit- I Number System and 1 1,2 1,2 T1,T2
Boolean Algebra And
Switching Functons -Binary
Week-1 Number Systems, Base
Conversion

2 Octal Number Systems, Base 2 2 2 T1,T2

Conversion

3 Hexa-decimal Number 2 2 2 T1,T2

Systems, Base Conversion

4 Codes-Weighted codes, Non- 3 3 2 T1,T2

Weighted codes

Week-2

5 Radix Complements of 3 3 2 T1,T2

I Number System and Boolean Algebra And Switching Functons

Numbers

6 Diminished Radix Complements of 3 3 2 T1,T2

Numbers

7 Binary Coded Decimal Code and its 2 2 2 T1,T2

Week-3 Properties

8 Unit Distance Codes,Excess-3 code 3 2 1,2 T1,T2

Week-4 9 3 3 2 T1,T2
Self-complementing codes, parity bits

10 Hamming code, problems 4 4 2 T1,T2

11 Alpha Numeric Codes-ASCII Code 2 2 2 T1,T2

Week-5
12 Basic Theorems and Properties, 2 2 2 T1,T2
Boolean function

13 Finding Duals, Complements, 2 2 2 T1,T2

Simplification

14 Switching Functions, SOP forms 3 2 2 T1,T2

15 POS forms 3 4 2 T1,T2

Week-6
16 Algebraic Simplification of Digital 3 4 1,2 T1,T2
Logic Gates

17 Properties of XOR Gates, Universal 3 4 2 T1,T2

Gates

Week-7 Multilevel NAND and NOR 3 3 2 T1,T2

realizations

18 Unit-II Minimizaton and Design of 4 4 2 T1,T2

Combinatonal Circuits -Introduction,
The Minimization with theorem

19 The Karnaugh` Map Method,2- 2 T1,T2

variable map

20 3-variable,4-variable maps 2 2,3 2 T1,T2

21 Five Variable K Maps 3 4 2 T1,T2

 GUEST LECTURES / SEMINARS / FIELD VISITS
22 Don’t Care Map Entries, Using the 3 4 2 T1,T2
Maps for Simplifying

23 Tabular Method 3 4 2 T1,T2

Week-8 24 Tabular Method 3 4 2 T1,T2

25 Design of Combinational Circuits 3 4 2 T1,T2

Unit-II Minimizaton and Design of Combinatonal Circuits

26 Arithmetic Circuits 3 4 2 T1,T2

27 Comparator, Multiplexers 3 4 2 T1,T2

28 Encoders, decoders, Code Converters 5 5 2 T1,T2

29 Practical Aspects related to 5 5 1,2 T1,T2

Combinational Logic Design, Hazards
and Hazard Free Relations

Week-9 30 Unit-III Sequental Machine 5 5 2 T1,T2

Fundamentals and Applicatons
-Basic Architectural Distinctions
between Combinational circuits

31 Sequential circuits, The Binary Cell 5 5 2 T1,T2

32 Fundamentals of Sequential Machine 5 5 2 T1,T2

Operation

33 Latches and Flip-Flops 4 3 2 T1,T2

34 S-R Flip-Flop and its excitation 2 1,2 2 T1,T2

35 J-K Flip-Flop , JK Mater Slave and its 2 4 2 T1,T2

excitation

Week- 36 D and T Flip-Flop and its excitation 2 4 2 T1,T2

10
37 Timing and Triggering Consideration, 2 4 2 T1,T2
Unit-III Sequental Machine Fundamentals and Applicatons

Clock Skew

38 Conversion from one type of Flip- 3 4 2 T1,T2

Flop to another

39 Unit-III Registers and Counters 3 4 1,2 T1,T2

-Shift registers and Data transmission
in shift registers

40 Shift Register configuration 3 4 2 T1,T2 `

41 Bidirectional Shift registers 2 4 2 T1,T2

42 3 4 2 T1,T2

Week-
11

Application of Shift registers

 GUEST LECTURES / SEMINARS / FIELD VISITS
43 Design and operation of Ring and 2 T1,T2
Twisted Ring Counter

44 Operation of Asynchronous Counters 2 2,3 2 T1,T2

Unit-III Registers and Counters

45 Design of Synchronous Modulo N – 3 4 2 T1,T2

Week-
Counter
12
46 Tutorial 3 4 2 T1,T2

47 Tutorial 4 6 2 T1,T2

48 Tutorial 5 5 2 T1,T2

49 Unit-IV: Sequental Circuits-I : 3 4 2 T1,T2

Introduction , State Diagram

50 Analysis of Synchronous Sequential 5 5 2 T1,T2

Circuits

51 Approaches to the design of 5 5 2 T1,T2

Synchronous Finite State Machines

Week- 52 Synthesis of Synchronous sequential 5 5 2 T1,T2

circuits
13
Serial Binary Counter , Sequence 5 5 2 T1,T2
Detector

Parity –bit Generation 2 2,3 2 T1,T2

53 Design of Asynchronous Counters 5 5 2 T1,T2

54 Design of Synchronous Modulo –N 5 5 2 T1,T2

Week- Counters
Unit-IV Sequental Circuits-I

14
55 Unit-V Sequental Circuits : Finite 5 5 2 T1,T2
state machine-capabilities and
limitations

56 Mealy and Moore models- 5 5 2 T1,T2

Minimization of completely specified 5 5 2 T1,T2

57 and incompletely specified
sequential machines

Minimization of completely specified 5 5 2 T1,T2

58 and incompletely specified
sequential machines
Week-
15 Minimization of completely specified 5 5 2 T1,T2
59 sequential machines

Minimization of completely specified 5 5 2 T1,T2

60 sequential machines

61 Partition techniques 5 5 2 T1,T2

62 Partition techniques 5 5 2 T1,T2

63 Merger chart methods 2 2,3 2 T1,T2

Week-
Sequental

16
Circuits

T1,T2
Unit-V

64 Merger chart methods 2 4 2

65 concept of minimal cover table 5 5 2 T1,T2

66 concept of minimal cover table 5 5 2 T1,T2

 GUEST LECTURES / SEMINARS / FIELD VISITS

Signature Signatur
Faculty e HOD

Lectures
No. of
Resource
Date Organization Topic Students
person
Attended

Seminars
No. of
Resource
Date Organization Topic Students
person
Attended
 GUEST LECTURES / SEMINARS / FIELD VISITS
Vice-chair, Genetic
21-02- Computer Society Algorithm &
Dr. M A Jabbar 20
2019 Chapter of IEEE Its
Hyderabad Section Applications

Industry /Field Visits

No. of
Organization
Date Place of visit Coordinator Students
/ field
Attended
 REMEDIAL/SPECIAL CLASSES

Date Period No. of Students Attended Theory/ Test

09-04- After 04 19 Theory
19 PM
10-04- After 04 12 Test
19 PM
14-04- After 04 12 Theory
19 PM
16-04- After 04 09 Theory
19 PM
 COURSE REVIEW /COMPLETION CERTIFICATE

Date of
Remarks Signature
Review
Review 1
(Before
Commencement)
Review 2
(Before MID-I)
Review 3
(Before MID-II)

COURSE COMPLETION CERTIFICATE

This is to certify that Dr. SK. Fairooz had completed the syllabus and course work
for the allocated subject Switching Theory & Logic Design (EC401ES) of 2 nd
year 2nd semester for the academic year 2018-2019.

Remarks:

HOD

PRINCIPAL IQAC
 COURSE MATERIAL

1 COURSE MATERIAL
2 QUESTION BANK
3 DESCRIPTIVE QUESTIONS
4 OBJECTIVE QUESTIONS
 TUTORIAL – SOLUTIONS – SAMPLES

1 TUTORIAL PROBLEMS
2 SOLUTIONS
3 SAMPLE SCRIPTS
 PREVIOUS QUESTION PAPERS

1 PREVIOUS QUESTION PAPERS

2 MODEL PAPERS
 MID QUESTION PAPER – SOLUTIONS – SAMPLES

1 MID QUESTION PAPERS

2 SOLUTIONS
3 SAMPLE SCRIPTS
 ASSIGNMENT – SOLUTIONS – SAMPLE

1 ASSIGNMENTS
2 SOLUTIONS
3 SAMPLE SCRIPTS
 RESULT ANALYSIS

1 CO-PO ATTAINMENT SHEET

2 PASS PERCENTAGE
3 PERFORMANCE EVALUATION
 COURSE ASSESSMENT

Attainme
C201 Course Outcomes Target Remarks
nt

CO 1

CO 2

CO 3

CO 4

CO 5

CO 6

Average Course Attainment

Head of the Committee

(Dept Assessment & Audit Committee)

HOD PRINCIPAL IQAC