a THE 9* INTERNATIONAL SYMPOSIUM ON ADVANCED TOPICS IN ELECTRICAL ENGINEERING May 7-9, 2015 Bucharest, Romania Optimization of a de to de Boost Converter using Interleaved Command Technique Liviu Dince!, Jenice-Ileana Coreaw', Eduard Ureche? {Deputment of Electrical, Energetic and Aerospace Engineering, University of Craiova, Romania “University Politelnica of Buchasest Idinea@elth uev 30, jeoreau@elth uev zo, eduard weehe@gmail com Abstract. In thie paper is optimized by numerical simulations 2 de to de boost converter with two parallel stages using de interlewed command technique A comparative study bepveen UUuee converter tepologies ~ one siage, vo parallel stages el twee interlewed stger it presented, Fis the interleaved ‘commen converter i medeled in MULTISIM and ir terted ‘under meny ouput loads. For compariven, simulations with ‘constant and contrlled duty cycle of the PWM are performed. ‘The main clewacterintcs of the three topologies are discussed: input current, input current ripple, ouput voltage rippl and ‘te MOSFET peakewrrent Keywords: optimization ofa de te de boost conwerter, interleaved ‘command technique, PWM puleer 1 yrropuctiow One of the problem for the static power converters on sizerft in the output voltage pple increase with respect the ‘output loed and thus the power quality on board get worst. ‘Another important aspect conceming th static converters on board is the efficiency improvement once the PWM duty cycle increases. The PWM duty cyele depends on the ‘outpwinput voltage ratio but also on the output load. At sual duty cyele the efficiency decreases. So, because the dlty cyele decreases once the output lod decreases, at small futput loads the efficiency decays. In conclusion, it is [rofitble to keep the duty cyele as close as possible to the ‘pfinum vale for that converter [1-14 ‘One solution to this roblem is to replace a single high ‘power converter witha multistage puellel converter [2]. This comvertercomsts infact in several lower power conveitzs working in puallel The adventage in this case iz the possibilty of the intelesved command of the lower power stages, Each MOSFET is conuuanced witha nn phase shi, where n is the nuuber of the puallel working stages. One obtains by this way an inportet lessening ofthe nipple both fx the input cuzent an for the outpat voltage. Mote, taking ‘nfo account the volume aid weight of the elechone components substantially increase withthe driven power, it is posible to obtein « smaller overall volume and weight comparative ta single stage converter. mn [15] is resented a study concerning the possibility of reducing the volume and weight of the power comvezsion stem tring several lower power couvertes. It mentions also novel efficiency impovement by this way. By successive couplng of supplementary pale] stages once the power request on the bus increases itis posible to manfan each 978-1-4799-75143/1 51831 00 ©2015 IEEE. stage near to the optimum duty cycle. So, the ensemble efficiency is improved and in less dependent on the power load on the bus ‘An important point of his topology is the improvement of the reliilty forthe conversion system. Inthe topology with ze high power converter if this converter fils, fails the entixe couversion system. In the topology with several low power converters, if one converter fails, the other converters may be Jept in function. The less power pulsed on the bus may be ducted by the power management system to the main consumers, the secondary consumers can be tumed off inthis case. The contol system of the multistage parallel converter ‘can be designed fo detect a stage failue and to start another slage iit is available A difficulty which can appear when supplementary stages are successive started is the necessity to adjust the phase sluft ‘The transistors command presented in [16)-[17} axe implemented in analogical version using mono-stable cixcuits Which ensue the phase shift. This version does not pert to adjust the phase shift with respect the nunber of the working stages. A solution is to we a microcontoller to dive the (MOSFETs. By software one can manage together the mumnber of working stages, the duty cyele and the phase shifts T. —- MODELING AND ANALYSIS oF ADe TDC CONVERTER WITHINTERLEAVED STAGES Inorder to work together fuel cell and a boost converterit is necessary to diop as move as possible the input cwrent nipple. To ths end in [17] intenleaved phases converters exe ‘wed. Versions with up to five inteleaved phases are tested and itis obtained a diop to 10 % of the mpples with respect the version with one single phase_ In tis paper, because the command scheme in MULTISIM get too cumbersome and the simulation time enormous increeses, one tested a vession with only two interleaved stages. Another problem which apptars is the simulation process instability for complex schemes in MULTISIM. As more complicated scheme as ‘more insteble is the simulation process. The simulation scheme is presented in figure 1. I presents common elements withthe schemes in 1-2) For the interleaved phases one used the impulse generar followed by two mono-stabe cxcits UIA and ULB, CD4538 type. One obtained by this way a pulse train shifted wath 180" wth respect the initial palses train. On each pues tain is Asposed e linear vanable volage (LVV) generetey followed by a comparator in order to obtein the PWM 190° shifted pulses Ithas tobe mentioned that « precise 180° phage shft easis obtained only for a 50% duty cyele. Ele, a slight deviation of the phase shift appeaus, but the converter functioning is not considerable affected. ‘Design process of the interleaved stages converter is the same with the single stage boost couverter ‘Output voltage can be contolled by the PWM duty eyele, a) I-d where: dis the duty eyele of the command pulses, 7, isthe input voltage and Yi the output voltage "The inductor value canbe estimated by the relation [4] ¥, L,=— 4 SFP AM ce” where: n is the numberof parallel stages, 4, au. is the put ‘cunent ripple and is the switching ftequency, fu (ee ‘Rig. 1. Boost Conmeter ath Humlewed stages schema wah PD consol nplen TL NuweicaL SmeuLarions RESULTS ‘The simulation results for 202 load are presented in figure Simulations for about 10 loads were performed and the characteristics in figure 3 were obtained The graphs in figwe 3 are made in MATLAB. In figure 3 is comparison between the simulation results for thee converter topologies ~ single stage converter in blue, two parallel stages in magenta and 05 Due to the contol signals are interleaved and the phase shaft is 2yh, the frequency of the input cument ripple isn times bigger the switching fiequency. The capacitor value in the filter of then interleaved stages converters 1, Cm = Pom Vo ae ® Tien i8 the mnximam nat cUen, AV aja is the ‘maximum ripple ofthe output voltage ‘The output voltage contoller was kept the same as in (1]- (QJ. It provide the same voltage for the both comparatoxs of the PWM generators. By this way one obtain tains of PWM. pulses with variable duty cyele shifted with approximately 180° for the MOSFETs command. For a comparison, the converter Land Cvalues ave kept the same in (1]-[2] ated MULTE two inteeaved stages in red. Concerning the mean input ‘cunent, itis a concordance between the three versions, the input cient is about 2 times bigger the output cunent. ‘The interleaved stages version reduce indeed the input cunent nipple at about 50% fiom the two parallel stages ripple, but the output characteristic of the interleaved stages cowverters has a considerable eater drop than the twoypuallel stages converter. Following the contol signals ‘oblained in figure 2 one find the output voltage controller provide a very small output voltage and thus the duty eye is too large. Against expectations a higher duty cycle produces a higher output voltage, inthis case, inthe period between two successive pulses, when the inductor has to load the capacitor, it is not enough time to push the entie gained ‘energy. So itis obtained an earlier diop of the output voltage, although, the two purlle inductors converter gives a higher ‘output cwrent, For the two parallel inductors case, although the period between two pulses is small, the ivductors push in the same time the energy on the capacitor. Inthe intezleaved stages case each inductors push its energy separately, for a shot period and further more, i is possible to lock each other when the output voltages of the two stages intersect ‘The choose solution in order to improve the couverter behavior were to lower limit the controller output voltage at about 3V with a Zenner diode (see figure 4). So, the duty ceyele is upper limited at about 70%. For this configuration zany simulations were performed. On these simulations, the output characteristics of the inteleaved phases converter, with contolled and constant duty cycle were drawn. ‘These fare yesented in figue 5. One can observe fiom these characteristics an increase of the output cwnent form 25 A to 4) A and a input cunent ripple diop fiom 17 A to about 6 A. In conclusion, this method to improve the converters behavior by upper limiting the duty eyele is good and against the theory’ a higher duty cycle produce a higher output ‘voltage. This is conect only if the inductor has enough time to push its energy on the capacitor inthe period between two pulses Mo ‘Big 2 Stmubtionrenhs of dc toe comer wih treed pines fr? ala 20