Received: 23 July 2018 Revised: 10 February 2019 Accepted: 22 March 2019

DOI: 10.1002/jnm.2604

RESEARCH ARTICLE

FPGA implementation of chaos‐based high‐speed true

random number generator

Ramji Gupta | Alpana Pandey | Rajendra Kumar Baghel

Department of Electronics and

Communication Engineering, MANIT,
Bhopal, India
Correspondence
Ramji Gupta, Department of Electronics
and Communication Engineering,
MANIT, Bhopal 462003, India.
Email: ramjigupta38@yahoo.com
Abstract
A true random number generator (TRNG) is a basic building block of many
modern cryptographic systems. As field programmable gate array (FPGA) has
a flexible architecture and low‐cost test cycle, hence, it becomes an ideal plat-
form for hardware implementation of digital systems. This paper presents an
FPGA implementation of a high‐speed TRNG that is based on a chaotic oscil-
lator at 100 MHz frequency with speed of 1600 Mbps. The experimental results
show that the proposed generator is faster and more compact than the existing
chaotic ring‐oscillator‐based TRNGs, and further, it is verified that the gener-
ated bit sequences pass all TRNG tests in National Institute of Standards and
Technology (NIST SP 800‐22). The proposed TRNG is implemented in two
FPGA families: Nexys 4 DDR XC7A100TCSG‐1 (Artix 7) and Basys 3
XC7A35T1CPG236C (Artix 7) Xilinx Vivado v.2017.3 design suite.

KEYWORDS
chaotic oscillator, field programmable gate array (FPGA), true random number generator (TRNG)

1 | INTRODUCTION

True random number generators (TRNGs) are an inseparable part of any security system that uses encryption and
decryption as its main protective measure. With high entropy and good speed, they find applications in software security
via password generation, protocols to validate aforesaid parties, and vector initialization. TRNG overcomes the limitation
of pseudorandom numbers generators using microscopic or macroscopic phenomenon such as electrical noise and cir-
cularly polarized photons, as these sources produce predictable outcomes.1,2 TRNG based on analogue circuits requires
larger area, high power consumption, and having low speed.3 On the other hand, digital logic and field programmable
gate array (FPGA)‐based TRNG have good flexibility, high speed, reduced size, and less complexity. Digital TRNGs have
mainly three components: entropy source such as ring oscillator (RO) or chaotic oscillator (CO), entropy harvester such
as sampler, and postprocessor such as LFSR.4-6 Our aim is to design TRNG containing digital components to make
design simple and suited for FPGA implementation. Digital implementation of TRNG has limited sources of randomness
like frequency of free running oscillator, random phase shift and clock signals, and meta‐stability of circuit elements.
The speed of the TRNGs depends upon the used entropy sources such as accumulated jitter1,4,7 and transition effect.6
CO can be used as an entropy source and the achieved output bit rate are in the range of 125 Mbit/s.8 Self‐time ring‐
based TRNG (STRNG) gives a high bit rate with larger area.9 TRNG based on critical sampling requires a fast oscillator
with manual placement.10 TNRG based on two metastable flip‐flops (FFs) uses an adaptive feedback loop to control the
randomness.2 We propose an FPGA implementation of TRNG using CO as a source of randomness in addition to meta‐
stability state of the FF stage, which provide a high bit rate with small area in terms of LUT's and registers compared
with previous designs.
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https://doi.org/10.1002/jnm.2604
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2 | CHAOS‐ B A S E D TR N G

The proposed chaos‐based TRNG with multiple sampling uses CO as a source of randomness and output of the RO to
provide clock signal. The CO frequency is kept minimum three times the RO frequency to pass the National Institute of
Standards and Technology (NIST) test. The schematic diagram of CO consists of 16 inverter in series is presented in
Figure 1. RO also consists of 16 inverters in series is presented in Figure 2. The schematic diagram of chaos‐based pro-
posed TRNG is presented in Figure 3. The output bit rate can be easily increased either by increasing the global clock
frequency or by adding identical TRNGs in parallel. The proposed design of TRNG consists of chaos‐based 16 identical
TRNGs in parallel to increase the bit rate. The output signal of CO is sampled into the positive edge triggered D FF,
which works as a sampler. The clock pulse is provided by the RO. For randomness of CO, the maximum achieved clock
frequency of RO founds 100 MHz. So under the design framework the proposed TRNG generates 16 bits in 10 nanosec-
onds at the output. CO and RO start oscillation at enable high. The output of CO is sampled to the D FF at the intervals
of Tclk, and it generates 16 bit random string in 10 nanoseconds. CO and RO did not oscillate at enable low, and FFs
retain the previous value.
Further to increase randomness, postprocessing unit (PPU) is added to the circuit as presented in Figure 4. The PPU
consists of 4 bit linear feedback shift resister (LFSR) connected to the TRNG, which remove the raw numbers from gen-
erated bit strings and improve the randomness. Other PPU structures like longer bit LFSR or encryption algorithms can
be used for better performance. The schematic diagram of PPU unit implemented in FPGA is shown in Figure 5.

3 | IMPLEMENTATION A ND TEST RESULTS

The proposed TRNG is implemented with Nexys 4 DDR XC7A100TCSG‐1 (Artix 7) and Basys 3 XC7A35T1CPG236C
(Artix 7) FPGA families. Nexys 4 and Basys 3 give high performance with Vivado Design Suite of Xilinx's, which
includes several new tools and design flows that expedite and improve the latest design methods. It runs faster and
make better use of FPGA resources.
For the NIST test, 106 bit streams were generated from TRNG, and the bit streams at the output of PPU were trans-
mitted from the FPGA board to the PC using the USB port of the Nexys 4 DDR and Basys 3 evaluation board with the
help of interface unit. The interface unit is implemented by a FIFO‐UART (Universal Asynchronous Receive Transmit)
combination. For NIST test results, the level of significance is set to P = .01.11 In the result, all P value are greater than
.01, which confirms that generated bit string is random as shown in Table 1.
The area (LUT and register) and throughput of the proposed TRNG are given in Table 2. Experimental results show
that the proposed design gives the same bit rate with and without PPU, hence, eliminate the need of this unit in the
design. The experimental result also shows that the proposed design unit is work as TRNG for 2n stages of parallel
TRNGs connected only when value of n is even.
The statistics of the TRNGs implemented previously is given in Table 3. It can be observed from Tables 2 and 3 that
the presented TRNG is optimized in terms of bit rate and area. At a very high bit rate of 1600 Mbps, the proposed TRNG
occupy a relatively low area. The parameter bit rate to area ratio (BPA) of proposed TRNG is better than the TRNGs
compared in Table 3.

FIGURE 1 Schematic of chaotic oscillator

FIGURE 2 Schematic of ring oscillator

GUPTA ET AL. 3 of 5

FIGURE 3 Structure of proposed true

random number generator (TRNG)

FIGURE 4 True random number

generator (TRNG) with postprocessing
unit

FIGURE 5 Schematic of postprocessing unit (PPU)

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TABLE 1 NIST test results of proposed TRNG

Artix7 Nexus‐4 Artix7 Basys‐3

Test P Value Result P Value Result

Frequency (monobit) 0.579 Successful 0.783 Successful

Block frequency 0.288 Successful 0.433 Successful
Cumulative sums (forward) 0.097 Successful 0.387 Successful
Cumulative sums (inverse) 0.453 Successful 0.613 Successful
Runs 0.288 Successful 0.783 Successful
Longest run 0.539 Successful 0.563 Successful
Rank 0.349 Successful 0.231 Successful
FFT 0.999 Successful 0.342 Successful
Nonoverlapping 0.734 Successful 0.672 Successful
Overlapping 0.342 Successful 0.876 Successful
Universal 0.394 Successful 0.453 Successful
Approximate entropy 0.743 Successful 0.821 Successful
Random excursions (x = +1) 0.384 Successful 0.781 Successful
Random excur. Variant(x = −1) 0.832 Successful 0.912 Successful
Serial (m = 16) 0.403 Successful 0.994 Successful
Linear complexity 0.754 Successful 0.834 Successful

Abbreviation: FFT, Fast Fourier Transform; TRNG, true random number generator.

TABLE 2 Implementation results of proposed TRNG in two FPGA families

Area (LUT + Reg.)

Mbit=s
BPA ( )
FPGA Family TRNG TRNG with PPU Bit Rate, Mbit/s LUT þ Reg:
Nexus 4 DDR Artix7 581 + 16 593 + 32 1600 2.6800
Basys 3 Artix7 581 + 16 593 + 32 1600 2.6800

Abbreviations: FPGA, field programmable gate array; PPU, postprocessing unit; TRNG, true random number generator.

TABLE 3 Implementation statistics results of previous TRNGs

Koyuncu and
Sunar et al4 Cherkaoui et al9 Turan Ozcerit12 Wu and Li13 Cherkaoui et al14 Choi et al15

Area (LUT + Reg) 525 + 130 352 + 256 12430 + 32 298 511 21 + 15
Bit rate (Mbps) 2.2 245 58.76 150 133 12.5
BPA 0.0033 0.42 0.0047 0.5033 0.260 0.33
FPGA family Cyclone V Cyclone V Vertex‐6 Altera Cyclone III Cyclone V
Cyclone IV

Abbreviations: FPGA, field programmable gate array; TRNG, true random number generator.

4 | CONCLUSION

We presented a chaos‐based TRNG using CO at 100 MHz using multiple sampling implemented in two FPGA family:
Nexys 4 DDR XC7A100TCSG‐1 (Artix 7) and Basys 3 (Artix 7) Xilinx vivado v.2017.3 design suite passed all the NIST
GUPTA ET AL. 5 of 5

test. The clock timing of 10 nanoseconds and 16 bit TRNGs that were added in parallel increased the bit rate. The exper-
imental results showed that the proposed TRNG is faster and more compact than previously implemented TRNGs.

ORCID
Ramji Gupta https://orcid.org/0000-0002-4126-4323

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How to cite this article: Gupta R, Pandey A, Baghel RK. FPGA implementation of chaos‐based high‐speed true
random number generator. Int J Numer Model. 2019;e2604. https://doi.org/10.1002/jnm.2604