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    Daniel Monjaras
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    sistemas

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    2 views4 pages

    Codigo

    Uploaded by

    Daniel Monjaras
    sistemas

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 4

    ------------------------------------

    CONTADOR MODULO 4 ASCENDENTE Y DESCENDENTE SIN MODIFICAR


    -----------------------------------
    library ieee;
    use ieee.std_logic_1164.all;
    entity contador_desyasc is
    port (
    RST: in std_logic;
    CLK: in std_logic;
    D: in std_logic;
    Y: out std_logic_vector(1 downto 0)
    );
    end contador_desyasc;
    architecture simple of contador_desyasc is
    signal Qn,Qp:std_logic_vector (1 downto 0);
    begin
    combinacional: process (Qp,D)
    begin
    case Qp is
    when "00"=> if(D='1') then Qn<="01";
    else Qn<="11";
    end if;
    when "01"=> if(D='1') then Qn<="10";
    else Qn<="00";
    end if;
    when "10"=> if(D='1') then Qn<="11";
    else Qn<="01";
    end if;
    when others=> if(D='1') then Qn<="00";
    else Qn<="10";
    end if;
    end case;
    Y<=Qp;
    end process combinacional;
    secuencial: process (RST,CLK)
    begin
    if(RST='0') then
    Qp<=Qn;
    end if;
    end process secuencial;
    end simple;

    ------------------------------------
    CONTADOR MODULO 4 ASCENDENTE Y DESCENDENTE CON MODIFICACION
    -----------------------------------
    library ieee;
    use ieee.std_logic_1164.all;
    entity contador_desyascdos is
    port (
    RST: in std_logic;
    CLK: in std_logic;
    D: in std_logic;
    Y: out std_logic_vector(1 downto 0)
    );
    end contador_desyascdos;
    architecture simple of contador_desyascdos is
    signal Qn,Qp:std_logic_vector (1 downto 0);
    begin
    combinacional: process (Qp,D)
    begin
    case Qp is
    when "00"=> if(D='1') then Qn<="01";
    else Qn<="11";
    end if;
    when "01"=> if(D='1') then Qn<="10";
    else Qn<="00";
    end if;
    when "10"=> if(D='1') then Qn<="11";
    else Qn<="01";
    end if;
    when others=> if(D='1') then Qn<="00";
    else Qn<="10";
    end if;
    end case;
    Y<=Qp;
    end process combinacional;
    secuencial: process (RST,CLK)
    begin
    if(RST='0') then
    Qp<="00";
    elsif (CLK' event and CLK='1') then
    Qp<=Qn;
    end if;
    end process secuencial;
    end simple;

    ------------------------------------
    CONTADOR MODULO 4 ASCENDENTE Y DESCENDENTE CON HABILITACION SIN MODIFICAR
    -----------------------------------
    library ieee;
    use ieee.std_logic_1164.all;
    entity contador_desyasch is
    port (
    RST: in std_logic;
    CLK: in std_logic;
    D: in std_logic;
    H: in std_logic;
    Y: out std_logic_vector(1 downto 0)
    );
    end contador_desyasch;
    architecture simple of contador_desyasch is
    signal Qn,Qp:std_logic_vector (1 downto 0);
    begin
    combinacional: process (Qp,D)
    begin
    case Qp is
    when "00"=> if(H='1') then if(D='1') then Qn<="01";
    else Qn<="11";
    end if;
    else Qn<=Qp;
    end if;
    when "01"=> if(H='1') then if(D='1') then Qn<="10";
    else Qn<="00";
    end if;
    else Qn<=Qp;
    end if;
    when "10"=> if(H='1') then if(D='1') then Qn<="11";
    else Qn<="01";
    end if;
    else Qn<=Qp;
    end if;
    when others=> if(H='1') then if(D='1') then Qn<="00";
    else Qn<="10";
    end if;
    else Qn<=Qp;
    end if;
    end case;
    Y<=Qp;
    end process combinacional;
    secuencial: process (RST,CLK)
    begin
    if(RST='0') then
    Qp<=Qn;
    end if;
    end process secuencial;
    end simple;

    ------------------------------------
    CONTADOR MODULO 4 ASCENDENTE Y DESCENDENTE CON HABILITACION CON MODIFICACION
    -----------------------------------
    library ieee;
    use ieee.std_logic_1164.all;
    entity contador_desyaschdos is
    port (
    RST: in std_logic;
    CLK: in std_logic;
    D: in std_logic;
    H: in std_logic;
    Y: out std_logic_vector(1 downto 0)
    );
    end contador_desyaschdos;
    architecture simple of contador_desyaschdos is
    signal Qn,Qp:std_logic_vector (1 downto 0);
    begin
    combinacional: process (Qp,D)
    begin
    case Qp is
    when "00"=> if(H='1') then if(D='1') then Qn<="01";
    else Qn<="11";
    end if;
    else Qn<=Qp;
    end if;
    when "01"=> if(H='1') then if(D='1') then Qn<="10";
    else Qn<="00";
    end if;
    else Qn<=Qp;
    end if;
    when "10"=> if(H='1') then if(D='1') then Qn<="11";
    else Qn<="01";
    end if;
    else Qn<=Qp;
    end if;
    when others=> if(H='1') then if(D='1') then Qn<="00";
    else Qn<="10";
    end if;
    else Qn<=Qp;
    end if;
    end case;
    Y<=Qp;
    end process combinacional;
    secuencial: process (RST,CLK)
    begin
    if(RST='0') then
    Qp<="00";
    elsif (CLK' event and CLK='1') then
    Qp<=Qn;
    end if;
    end process secuencial;
    end simple;

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