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UNITED INTERNATIONAL UNIVERSITY (UIU)

COURSE NO. EEE 402 (CONTROL SYSTEM LABORATORY)

EXPT. NO. 7

DESIGN A LEAD-LAG COMPENSATOR USING ROOT LOCUS METHOD AND SISO

DESIGN TOOL

Design Requirement:
K
Given the transfer function, G ( s )  and H(s) = 1, design a lag-lead
s  17 s  76s  60
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compensator so that the system is operated with i) 20% OS, ii) a twofold reduction in settling
time and iii) tenfold improvement in steady-state error for a step input.

Procedure:
Uncompensated system:
1. Using SISO Design tool, create the design for the given G(s) and H(s) and plot the
root locus.
2. From Edit| SISO Tool Preferences window, select Options tab, select Zero/pole/gain
radio button under Compensator Format and click Ok.
3. Right click on the SISO Design Tool window and then click on Grid.
4. Right click on the SISO Design Tool window and then click on Design Constraints|
New from the appeared window. Select Constraint Type as Percent Overshoot, set
Percent Overshoot as 20 and click Ok.
5. Select the closed-loop pole at the intersection of shadowed region and the root locus.
Write down the value obtained in the C(s) text box. Also, write down the closed-loop
poles and damping ratio obtained from View| Closed Loop Poles.
6. Select Analysis| Response to Step Command. Write down the values of percent
overshoot, peak time, settling time and steady state error from the appeared window
of LTI Viewer for SISO Design Tool. The performance is tabulated in Table 1.
Lead-compensated system:
7. Calculate the imaginary part, d and real part, d of the compensated dominant pole
to realize the twofold reduction in settling time as:  d   n  2   d ,uncompensated and
 d   n tan  , where   cos 1 ( ) .
8. Select the location of lead-compensator zero as 6, coincident with the open-loop
pole at 6. This choice will eliminate a zero and leave the lead-compensated system
with three poles, the same number that the uncompensated system has.
9. Find the sum of angles,  from the uncompensated system’s poles and zeros and the
compensator zero to the desired dominant poles calculated in Step 7. Then, calculate
the location of compensator pole, pc using the formula  d /(pc   d ) = tan (1800 ).

This sheet for Control System Laboratory has been prepared by:
Md. Iqbal Bahar Chowdhury, Assistant Professor, EEE, UIU.
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10. Set the value of the calculated compensated real pole and the zero at -6 to the root
locus using the window appeared after selecting Compensators| Edit| C, the value of
which is obtained in Step 8.
11. Repeat Steps 5, 6. This is the end of lead-compensation.
Lag-Lead-compensated system:
12. Choose the lag-compensator pole at 0.01 and for this pole, calculate the lag-
compensator zero. Set these values using the window appeared after selecting
Compensators| Edit| C.
13. Repeat steps 5, 6. This is the end of lag-lead-compensator.

PostLab:
1. Fill up the following table, comment on the findings (Why Ts is increased after
adding lag, which (lead-lag/ lead) is faster considering amplitude development, is
our final design acceptable?)
2. Design a passive circuit for the above lead-lag controller.

Uncompensated Lead-compensated Lead-Lag-compensated

Plant and
Compensator
Dominant
Poles

n

% OS

Ts

Tp

Kp

e()

Other poles

Zeroes

This sheet for Control System Laboratory has been prepared by:
Md. Iqbal Bahar Chowdhury, Assistant Professor, EEE, UIU.