Week 8: Assignment Solutions

1. Suppose that in a MIPS32 based computer, memory locations 500, 501,

502 and 503 (in decimal) contains the data 55, 36, 212 and 5 (in decimal
respectively.
For the following MIPS32 code segment, the final value of R8 will be …….
ADDI R5,R0,35
SUI R7,R0,23
LW R6,501(R0)
ADD R5,R5,R7
SUB R8,R5,R6
Correct solution is: –24
The values calculated by the instructions in sequence will be:
R5 = 0 + 35 = 35
R7 = 0 – 23 = –23
R6 = Mem[501 + 0] = 36
R5 = 35 + (-23) = 12
R8 = 12 – 36 = –24

2. Suppose that in a MIPS32 based computer, memory locations 500, 501,

502 and 503 (in decimal) contains the data 55, 36, 212 and 5 (in decimal
respectively.
After execution of the following MIPS32 code segment, memory location
503 will contain ……………..
ADDI R1,R0,500
LW R2,0(R1)
LW R3,2(R1)
ADD R3,R2,R3
SW R3,3(R1)
Correct solution is: 267
The values calculated by the instructions in sequence will be:
R1 = 0 + 500 = 500
R2 = Mem[500 + 0] = 55
R3 = Mem[500 + 2] = 212
R3 = 55 + 212 = 267
Mem[500 + 3] = 267

3. For the register values R2=35 and R6=52, after execution of the
instruction “SLT R12,R2,R6”, the contents of R12 will be ………
Correct answer is: 1
The SLT instruction will set the value of register R12 to 1 if R2 < R6, and
will set it to 0 otherwise. In this example, since R2 < R6, R12 will become
1.
4. For the instruction encoding as discussed in the lectures, what will be the
hexadecimal machine code for the instruction “SUBI R21,R17,365”?
a. 32’h2e41003d
b. 32’h2e35016d
c. 32’h2e35017a
d. None of the above
Correct answer is (b).
For the I-type instruction, the various fields of the instruction will be:
001011 10001 10101 0000 0001 0110 1101
(recall that 365 is 016d in hex)

5. For the following code segment, what will be the hexadecimal machine
code for the BEQZ instruction, assuming the instruction encoding as
discussed in the lectures?
Loop: ADD R2,R5,R10
SUI R11,R2,25
MUL R3,R2,R1
ADDI R7,R0,12
BEQZ R11,Loop
a. 32’h39600005
b. 32’f3960fff9
c. 32’h3960fffb
d. None of the above
Correct answer is (c).
It may be noted that when the BEQZ instruction is executed, PC points to
the next instruction. So the target of the branch will be -5. In 16-bit 2’s
complement, -5 is 1111 1111 1111 1011 (i.e. fffd in hex).
Here, the various fields of the instruction will be:
001110 01011 00000 1111 1111 1111 1011

6. The decimal number -7 is represented in 4-bit binary 2’s complement

notation. It is sign extended to 16 bits. The sign extended value in
hexadecimal will be
a. FFF9
b. FFF7
c. 8007
d. None of the above
Correct answer is (a).
In 4 bits, -7 is 1001 in 2’s complement notation. So when sign extended to
16 bits, it will become:
1111 1111 1111 1001 = FFF9 (in hex)
7. Why is the HALTED signal required in the Verilog implementation of the
processor as discussed in the lecture?
a. It is used for an external device to halt the processor.
b. It is used to tell the instructions after the HLT instruction that the
processor has halted and they should not make any changes.
c. It is used to indicate that the processor has started its execution.
d. None of the above.
Correct answer is (b).
When the HLT instruction is executed, and it reaches the WB stage, that
should mark the end of execution. All the following instructions that have
already entered the pipeline must not be allowed to make any changes
anywhere.