library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity convelution_encoder is

port (i_clk : in std_logic;

i_rstb : in std_logic;

i_sync_reset : in std_logic;

i_data_enable : in std_logic;

i_data : in std_logic;

o_data_valid : out std_logic;

o_data_out_x : out std_logic;

o_data_out_y : out std_logic);

end convelution_encoder;

architecture Behavioral of convelution_encoder is

constant C_XPOLY : std_logic_vector(5 downto 0) := ("111001"); -- 1 71 oct, first '1' is not computed
since is the input

constant C_YPOLY : std_logic_vector(5 downto 0) := ("011011"); -- 1 33 oct, first '1' is not computed
since is the input

signal r_delay : std_logic_vector(5 downto 0);

begin
p_encoder : process(i_clk,i_rstb)

variable v_x : std_logic;

variable v_y : std_logic;

begin

if(i_rstb='0') then

o_data_valid <= '0';

o_data_out_y <= '0';

r_delay <= (others=>'0');

elsif(rising_edge(i_clk)) then

o_data_valid <= i_data_enable;

if(i_sync_reset='1') then

r_delay <= (others=>'0');

elsif(i_data_enable='1') then

r_delay <= i_data&r_delay(r_delay'length-1 downto 1);

end if;

v_x := i_data;

v_y := i_data;

for i in r_delay'length-1 downto 0 loop

if(C_XPOLY(i)='1') then

v_x := v_x xor r_delay(i);

end if;

if(C_YPOLY(i)='1') then

v_y := v_y xor r_delay(i);

end if;

end loop;

o_data_out_x <= v_x;

o_data_out_y <= v_y;

end if;

end process p_encoder;

end Behavioral;