ECC66100 Series

SD-FEC Encoder/Decoder Cores

Viasat’s ECC66100 is a family of soft decision Forward Error Correction SOFT DECISION FEC
(FEC) IP cores based on Turbo Product Code (TPC) designed for use in 100 AT-A-GLANCE
Gbps communications applications.
Encoder and Decoder
TPCs are the optimum FEC for high data rate applications as they Features:
provide high Net Electrical Coding Gain (NECG) with low implementation
»»100 G OTU4 application
complexity. TPCs also have large minimum distances leading to a very low
error floor, several orders of magnitude below the target 1e-15 Bit Error Rate »»15% or 20% overhead rate
(BER), based on asymptotic analysis. »»NECG of 11 or 11.3 dB
ECC6100’s underlying TPC architecture has been used extensively for a »»High burst error correction
variety of applications that has proven successful in both simulations and »»Extensively proven TPC core
hardware. architecture
The ECC6100 series consists of the following overhead rates: »»Low implementation complexity
»»15% with 11 dB NECG »»Easily configurable to achieve
»»20% with 11.3 dB NECG desired performance and
complexity
»»Low latency
SOFT DECISION FEC PERFORMANCE
1.00E-+00

1.00E-01

1.00E-02
Uncoded BER
1.00E-02
15% OH BER
1.00E-03 20% OH BER

1.00E-04
Bit Error Rate

1.00E-05

1.00E-06

1.00E-07

1.00E-08

1.00E-09

1.00E-10

1.00E-11

1.00E-12

1.00E-13

1.00E-14

1.00E-15
3 4 5 6 7 8 9 10 11 12 13 14 15

Eb/No (dB)

OUTPUT BER VS. INPUT BER

1.00E-+00
15% OH BER
1.00E-01
20% OH BER
1.00E-02

1.00E-03

1.00E-04

1.00E-05
OUTPUT BER

1.00E-06

1.00E-07

1.00E-08

1.00E-09

1.00E-10

1.00E-11

1.00E-12

1.00E-13

1.00E-14

1.00E-15

1.0E-02 1.0E-01

INPUT BER
ECC66100 Series SD-FEC Encoder/Decoder Cores

SPECIFICATIONS
FEATURE/PARAMETER FEATURE/PARAMETER (CONTINUED)
Coded Line Rate  Power Consumption 40 nm process <8 W Typical
»» 15% OH 120 Gbps
Size (Includes Flipflops, Logic Gates and RAM)
»» 20% OH 126 Gbps »» Encoder + interleaver
NECG ÌÌ 15% and 20% OH 1.64 M equivalent gates
»» 15% OH 11 dB »» Decoder + deinterleaver
»» 20% OH 11.3 dB ÌÌ 15% OH 25.8 M equivalent gates
Clocking 500 MHz ÌÌ 20% OH 22.0 M equivalent gates
Burst Error Correction
»» 15% OH 1536
DELIVERABLES
»» Encrypted RTL: synopsys and/or cadence compatible
»» 20% OH 1152
»» System verilog, VMM based testbench and testcases
Soft Decision Resolution
»» “C” SW model (gcc object file)
»» 4 bits
»» User documentation
»» LLR input 8 bits I & Q
Latency RELATED VIASAT PRODUCTS
»» Encoder »» DSP IP cores for coherent receiver and transmitter
ÌÌ 15% OH 2 µs »» FPGA demonstration platform for algorithm verification
ÌÌ 20% OH 1 µs
Visit www.viasat.com for further information
»» Decoder
ÌÌ 15% OH less than 8 μs
ÌÌ 20% OH 5 µs

FIGURE 1. TPC DECODER FIGURE 2. TPC ENCODER

APB_* Senc_In_Data(256)
Pre Processor Pre Processor
Dec_In_DataHI(256) Senc_In_Valid

Dec_In_DataHQ(256) (vsat_sdec_ Iteration Senc_In_Sof

prep_encrypt)
Dec_In_DataVI(256)
Dec_In_DataVQ(256) (vsat_sdec_
iter_encrypt)

APB_*
Iteration Clk_Core Encoder
Rst_Core_n
(vsat_sdec_ Rst_Cfg_n
Clk_Core iter_encrypt)
Rst_Core_n
IRQ_Senc
Rst_Cfg_n
Dft_Pm*
Dft_Pm* Iteration

Interleaver
(vsat_sdec_
iter_encrypt)

Post Processor
APB_* Iteration
(vsat_sdec_ Senc_Out_DataHI(64)
Dec_Out_Data(256) post_encrypt)
Senc_Out_DataHQ(64)
Dec_Out_Valid (vsat_sdec_
Senc_Out_DataVI(64)
iter_encrypt) Differential
Dec_Out_Sof
Senc_Out_DataVQ(64) Encoder
Senc_Out_Valid
Senc_Out Sof

(vsat_senc_encrypt)

CONTACT
SALES
TEL +1 216 706 7800 FAX +1 216 706 7801 EMAIL ipcores@viasat.com WEB www.viasat.com/advanced-technology

Copyright © 2017 Viasat, Inc. All rights reserved. Viasat and the Viasat logo are registered trademarks of Viasat, Inc. All other product or company names mentioned are used for identification purposes only and may be
trademarks of their respective owners. Specifications and product availability are subject to change without notice. 468044-171013-008