-- Module Name: motor_paso - Behavioral

-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;

entity motor_paso is
Port ( clk,reset,der,izq : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0));
end motor_paso;

architecture Behavioral of motor_paso is

type state_type is (P1,P2,P3,P4);
signal state : state_type;
begin
process(clk,reset)
begin
if reset = '0' then
state <= P1;
elsif rising_edge(clk) then
case (state) is
when P1 => S <= "1010";
if (der = '0' and izq = '1') then
state <= p2;
elsif (der = '1' and izq = '0') then
state <= p4;
else
state <= p1;
end if;
when P2 => S <= "1001";
if (der = '0' and izq = '1') then
state <= p3;
elsif (der = '1' and izq = '0') then
state <= p1;
else
state <= p2;
end if;
when P3 => S <= "0101";
if (der = '0' and izq = '1') then
state <= p4;
elsif (der = '1' and izq = '0') then
state <= p2;
else
state <= p3;
end if;
when P4 => S <= "0110";
if (der = '0' and izq = '1') then
 state <= p1;
elsif (der = '1' and izq = '0') then
state <= p3;
else
state <= p4;
end if;
end case;
end if;
end process;
end Behavioral;