Mano 4 PDF

4-1
Inputs Outputs
Combinational Next
circuit state Storage Present
elements state
Fig. 4-1 Block Diagram of a Sequential Circuit
© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
4-2
0 0
•
tpd • • •
1t 1t
(b) 2 pd 2 pd
tpd
(a) (d)
1 1
•
tpd
(c)
Fig. 4-2 Logic Structures for Storing Information

4-3
Inputs Outputs
Combinational
circuit
Flip-flops
Clock pulses
(a) Block diagram
(b) Timing diagram of clock pulses

Fig. 4-3 Synchronous Clocked Sequential Circuit

4-4
R (Reset) S R Q Q
• • Q
1 0 1 0
Set state
0 0 1 0
0 1 0 1
0 0 0 1 Reset state
S (Set)
• • Q 1 1 0 0 Undefined
(a) Logic diagram (b) Function table
Fig. 4-4 SR Latch with NOR Gates

4-5
0.0 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns
i S Cs
i R Cs
o Q Cs
o Q_B
Fig. 4-5 Logic Simulation of SR Latch Behavior

4-6
S (Set) S R Q Q
• • Q
0 1 1 0
Set state
1 1 1 0
1 0 0 1
1 1 0 1 Reset state
R (Reset)
• • Q 0 0 1 1 Undefined
Fig. 4-6 S R Latch with NAND Gates

4-7
C S R Next state of Q
S
• • • Q 0 X X No change
1 0 0 No change
C • 1 0 1 Q = 0; Reset state
1 1 0 Q = 1; Set state
• • • Q 1 1 1 Undefined
R
Fig. 4-7 SR Latch with Control Input

4-8
D • S
• • • Q
C •
• • • Q
• R
(a) Logic diagram
C D Next state of Q
0 X No change
1 0 Q = 0; Reset state
1 1 Q = 1; Set state
(b) Function table

Fig. 4-8 D Latch

4-9
C • •
D TG • • • Q
• •
•
TG • Q
• •
Fig. 4-9 D Latch with Transmission Gates

4-10
Y
S S S Q
C • C C
Y
R R
• R
• Q
•
Fig. 4-10 SR Master-Slave Flip-Flop

4-11
0.0 50ns 100ns 150ns 200ns
iC Cs
iS Cs
iR Cs
oY
oQ
Fig. 4-11 Logic Simulation of a Master-Slave Flip-Flop

4-12
S S • Q
J
C • C C
K
R • R • • Q
•
(a)
Next State
J K of Q
0 0 Q
0 1 0
1 0 1
1 1 Q
(b)
Fig. 4-12 Master-Slave JK Flip-Flop

4-13
D D S Q
C
• • C
• R
• Q
•
Fig. 4-13 D-Type Positive Edge-Triggered Flip-Flop

4-14
J D S • Q
C • C
K • • C • R
• • Q
•
Fig. 4-14 Positive Edge-Triggered JK Flip-Flop

4-15
S • S D D
R • • R
• C
• • C
•
SR SR D with 1 Control D with 1 Control
(a) Latches
S S J J
C
• C C
• C
R • R • K • K •
Triggered SR Triggered SR Triggered JK Triggered JK
(b) Master-Slave Flip-Flops
D D J J
C • C
C • • C • K • K •
Triggered D Triggered D Triggered JK Triggered JK
(c) Edge-Triggered Flip-Flops
Fig. 4-15 Standard Graphic Symbols for Latch and Flip-Flops

4-16
TABLE 4-1
Flip-Flop Characteristic Tables
(a) JK Flip-Flop (b) SR Flip-Flop
J K Q (t ⫹ 1) Operation S R Q (t ⫹ 1) Operation
0 0 Q(t ) No change 0 0 Q(t ) No change

0 1 0 Reset 0 1 0 Reset
1 0 1 Set 1 0 1 Set
1 1 Q(t ) Complement 1 1 ? Undefined
(c) D Flip-Flop (d) T Flip-Flop
D Q (t ⫹ 1) Operation T Q (t ⫹ 1) Operation
0 0 Reset 0 Q(t) No change

1 1 Set 1 Q ( t) Complement
Table 4-1 Flip-Flop Characteristic Tables

4-17
S R C J K Q Q
• S
1J Q
0
1
1
0
X
X
X
X
X
X
1 0
0 1
0 0 X X X Undefined
C1
→→→→
1 1 0 0 No change
1K
• Q 1
1
1
1
0
1
1
0
0 1
1 0
• R 1 1 1 1 Complement
(a) Graphic symbols (b) Function table
Fig. 4-16 JK Flip-Flop with Direct Set and Reset

4-18
X
B •
J A
Y • •
C
C •
• K • A
Clock
Fig. 4-17 Implementing Input Equations

4-19
•
X •
D • A
• C
• A
D • B
•
• C
B
Clock
•
Fig. 4-18 Example of a Sequential Circuit
4-20
TABLE 4-2
State Table for Circuit of Figure 4-18
Present State Input Next State Output
A B X A B Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
Table 4-2 State Table for Circuit of Figure 4-18

4-21
TABLE 4-3
Two-Dimensional State Table for the Circuit in Figure 4-
18
Next state Output

Present
state X⫽0 X⫽1 X ⫽0 X⫽1
A B A B A B Y Y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0
Table 4-3 Two-Dimensional State Table for the Circuit in Figure 4-18

4-22
A
X D • Z
Y C
•
Clock
(a)
Present Next
state Inputs state Output
A X Y A Z
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 0
1 0 0 1 1
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
(b) State table
Fig. 4-19 Logic Diagram and State Table for D A = A ⊕ X ⊕Y

4-23
TABLE 4-4
State Table for Circuit with JK Flip-Flops
Present state Input Next state Flip-flop inputs
A B X A B JA KA J B KB
0 0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0 1
0 1 0 1 1 1 1 1 0
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1
1 1 1 1 1 1 0 0 0
Table 4-4 State Table for Circuit with JK Flip-Flops

4-24
0/0 1/0
00 01
0/1
0/1 0/1 1/0 01,10
00,11 0/0 1/1 00,11

1/0 01,10
1/0 10 11
(a) (b)
Fig. 4-20 State Diagrams

4-25
1/0 1/0 1/0

A B A B C
(a) (b)
1/0 1/0 0/0 1/1

A B C D
(c)
0/0 1/0
1/0 1/0 0/0

A B C D
1/1
0/0
0/0
(d)
Fig. 4-21 Construction of a State Diagram

4-26
TABLE 4-5
State Table for State Diagram in Figure 4-21
Next State Output Z

Present
State X⫽0 X⫽1 X ⫽0 X⫽1
A A B 0 0
B A C 0 0
C D C 0 0
D A B 0 1
Table 4-5 State Table for State Diagram in Figure 4-21

4-27
TABLE 4-6
Sequence Tables for Code Converter Example
Sequences in Order of Digits Represented Sequences in Order of Common Prefixes
BCD Input Excess-3 Output BCD Input Excess-3 Output
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0
1 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1
0 1 0 0 1 0 1 0 0 0 1 0 1 1 1 0
1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 0
0 0 1 0 1 1 1 0 0 1 1 0 1 0 0 1
1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0
0 1 1 0 1 0 0 1 1 0 0 1 0 0 1 1
1 1 1 0 0 1 0 1 1 0 1 0 0 0 0 1
0 0 0 1 1 1 0 1 1 1 0 0 0 1 1 0
1 0 0 1 0 0 1 1 1 1 1 0 0 1 0 1
Table 4-6 Sequence Tables for Code Converter Example

4-28
Init Init
0/1 1/0 0/1 1/0
B1=0 B1=1 B1=0 B1=1
0/1 1/0 0/0 or 1/1

(a)
B2=0 B2=1 B2=X
(b)
Init Init
0/1 1/0 0/1 1/0

0/1 or 1/1 0/1 or 1/1
B1=0 B1=1 B1=0 B1=1

0/0 or 1/1 0/0 or 1/1
0/1 1/0 0/0 or 1/1 0/1 1/0 0/0 or 1/1
B2=0 B2=1 B2=X B2=0 B2=1 B2=X
0/0 or 1/1
0/1 1/0
1/0
0/1
B3=0 B3=1 B3=0 B3=1
(c) (d)
Fig. 4-22 Construction of a State Diagram

4-29
TABLE 4-7
Table 4-5 with Names Replaced by Binary Codes
Next State Output Z
Present State X⫽0 X⫽1 X ⫽0 X⫽1
00 00 01 0 0
01 00 11 0 0
11 10 11 0 0
10 00 01 0 1
Table 4-7 Table 4-5 with Names Replaced by Binary Codes

4-30
TABLE 4-8
State Table for Design Example
Present State Input Next State Output
A B X A B Y
0 0 0 0 0 0
0 0 1 0 1 1
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 0 0
1 0 1 1 1 1
1 1 0 1 1 0
1 1 1 0 0 0
Table 4-8 State Table for Design Example

4-31
0/0
00
1/1 1/0
0/0
1/0 01 11
0/0 1/1
10
0/0
Fig. 4-23 State Diagram for Design Example

4-32
BX B BX B BX B
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
0 1 0 1 1 0 1
A 1 1 1 1 A 1 1 1 A 1 1
X X X
DA = AB + BX DB = AX + BX + ABX Y = BX
Fig. 4-24 Maps for Input Equations and Output Y

4-33
•
D • A
C
X • • • • • A
•
•
• D • B
• C
• • B
Clock
Y
Fig. 4-25 Logic Diagram for Sequential Circuit with D Flip-Flops

4-34
TABLE 4-9
State Table for Second Design Example
Present State Input Next State
A B C X A B C
0 0 1 0 0 0 1
0 0 1 1 0 1 0
0 1 0 0 0 1 1
0 1 0 1 1 0 0
0 1 1 0 0 0 1
0 1 1 1 1 0 0
1 0 0 0 1 0 1
1 0 0 1 1 0 0
1 0 1 0 0 0 1
1 0 1 1 1 0 0
Table 4-9 State Table for Second Design Example

4-35
CX C
AB 00 01 11 10
00 X X X X 1 X X 1
01 1 1 1 1 1
B
11 X
X X X X X X X X X X X
A
10
1 1 1 1 1
DA = AX + BX + BC DB = AC X + ABX DC = X
Fig. 4-26 Maps for Simplifying Input Equations

4-36
TABLE 4-10
Flip-Flop Excitation Tables
(a) JK Flip-Flop (b) SR Flip-Flop
Q (t ) Q (t ⫹ 1) J K Q (t ) Q (t ⫹ 1) S R
0 0 0 X 0 0 0 X
0 1 1 X 0 1 1 0
1 0 X 1 1 0 0 1
1 1 X 0 1 1 X 0
(c) D Flip-Flop (d) T Flip-Flop
Q (t) Q (t ⫹ 1) D Q (t) Q (t ⫹ 1) T
0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0
Table 4-10 Flip-Flop Excitation Tables

4-37
TABLE 4-11
State Table with JK Flip-Flop Inputs
Present State Input Next State Flip-Flop Inputs
A B X A B JA KA JB KB
0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 X 1 X
0 1 0 1 0 1 X X 1
0 1 1 0 1 0 X X 0
1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X
1 1 0 1 1 X 0 X 0
1 1 1 0 0 X 1 X 1
Table 4-11 State Table with JK Flip-Flop Inputs

4-38
BX B BX B
A 00 01 11 10 A 00 01 11 10
0 1 0 X X X X
A 1 X X X X A 1 1
X X
JA = BX KA = BX
BX B BX B
A 00 01 11 10 A 00 01 11 10
0 1 X X 0 X X 1
A 1 1 X X A 1 X X 1
X X
JB = X KB = AX + AX
=A X
Fig. 4-27 Maps for J and K Input Equations

4-39
AND2
FJKC
X
INV
A
AND2
AND2
INV
FJKC
XNOR2
CLK
Fig. 4-28 Logic Diagram for Sequential Circuit with JK Flip-Flops

4-40
R: 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0
X: 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 0
A: X X 0* 0 0 0 1 1 1 1 0 0 1 1 0* 0
B: X X 0* 0 1 1 0 0 1 1 0 1 0 1 0* 0
Y: 0 0 0* 1 0 0 0 1 0 0 1 0 1 0 0* 0
* These responses are asynchronous with the clock and thus do not w ait for the next positive
clock edge.
(a) Circuit test and expected results
0.0 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns 200ns 220ns 240ns 260ns 280ns
i CLK Cs
iR Cs
iX Cs
oA
oB
oY
(b) Simulation results
Fig. 4-29 Logic Simulation Verification for the Circuit in Figure 4-28

4-41
-- Positive Edge-Triggered D Flip-Flop with Reset:

-- VHDL Process Description
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(CLK, RESET, D : in std_logic;
Q : out std_logic);
end dff;
architecture pet_pr of dff is

-- Implements positive edge-triggered bit state storage
-- with asynchronous reset.
begin
process (CLK, RESET)
begin
if (RESET = '1') then
Q <= '0';
elsif (CLK'event and CLK = '1') then
Q <= D;
end if;
end if;
end process;
end;
Fig. 4-30 VHDL Process Description of Positive Edge-Triggered Flip-Flop with Reset

4-42
-- Sequence Recognize r: VHDL Process Description
-- (See Figure 4-21 f or state diagram)
library ieee;
use ieee.std_logic_11 64.all;
entity seq_rec is
port(CLK, RESET, X: in std_logic;
Z: out std_logic);
end seq_rec;
architecture process_3 of seq_rec is

type state_type is (A, B, C, D);
signal state, next_state : state_t ype;
begin
-- Process 1 - state_ register: implements positive edge-triggered

-- state storage with asynchronous reset.
state_register: process (CLK, RESET)
begin
if (RESET = '1') then
state <= A;
elsif (CLK’event and CLK = '1') then
state <= n ext_state;
end if;
end if;
end process;
-- Process 2 - next_s tate_function: implements next state as

-- a function of inpu t X and state.
next_state_func: process (X, state)
begin
case state is
when A =>
if X = '1' then
next_state <= B ;
else
next_state <= A ;
end if;
when B =>
if X = '1' then
next_state <= C ;
else
next_state <= A ;
end if;
Fig. 4-31 VHDL Process Description of a Sequence Recognizer

4-43
-- Sequence Recognizer: VHDL Process Description (continued)
when C =>
if X = '1' then
next_state <= C;
else
next_state <= D;
end if;
when D =>
if X = '1' then
next_state <= B;
else
next_state <= A;
end if;
end case;
end process;
-- Process 3 - output_function: implements output as function

-- of input X and state.
output_func: process (X, state)
begin
case state is
when A =>
Z <= '0';
when B =>
Z <= '0';
when C =>
Z <= '0';
when D =>
if X = '1' then
Z <= '1';
else
Z <= '0';
end if;
end case;
end process;
end;
Fig. 4-32 VHDL Process Description of a Sequence Recognizer (continued)

4-44
TABLE 4-12
Illustration of generation of storage in VHDL
Inputs Action
RESET = 1 CLK = 1 CLK’event
FALSE FALSE FALSE Unspecified
FALSE FALSE TRUE Unspecified
FALSE TRUE FALSE Unspecified
FALSE TRUE TRUE Q <= D
TRUE — — Q <= '0'
Table 4-12 Illustration of generation of storage in VHDL

4-45
// Positive Edge-Triggered D Flip-Flop with Reset:

// Verilog Process Description
module dff_v(CLK, RESET, D, Q);

input CLK, RESET, D;
output Q;
reg Q;
always @(posedge CLK or posedge RESET)

begin
if (RESET)
Q <= 0;
else
Q <= D;
end
endmodule
Fig. 4-33 Verilog Process Description of Positive Edge-Triggered Flip-Flop with Reset

4-46
// Sequence Recognize r: Verilog Process Description
// (See Figure 4-21 f or state diagram)
module seq_rec_v(CLK, RESET, X, Z);
input CLK, RESET, X;
output Z;
reg [1:0] state, next _state;
parameter A = 2'b00, B = 2'b01, C = 2 'b10, D = 2'b11;
reg Z;
// state register: im plements positive edge-triggered
// state storage with asynchronous reset.
always @(posedge CLK or posedge RESET)
begin
if (RESET == 1)
state <= A;
else
state <= next_state;
end
// next state functio n: implements next state as funct ion
// of X and state
always @(X or state)
begin
case (state)
A: if (X == 1)
next_state <= B;
else
next_state <= A;
B: if(X) next_state <= C ;else next_state <= A;
C: if(X) next_state <= C ;else next_state <= D;
D: if(X) next_state <= B ;else next_state <= A;
endcase
end
// output function: i mplements output as function
// of X and state
always @(X or state)
begin
case (state)
A: Z <= 0;
B: Z <= 0;
C: Z <= 0;
D: Z <= X ? 1 : 0;
endcase
end
endmodule
Fig. 4-34 Verilog Process of a Sequence Recognizer

4-47
TABLE 4-13
Illustration of generation of storage in Verilog
Inputs Action
posegdge RESET
and RESET = 1 posedge CLK
FALSE FALSE Unspecified
FALSE TRUE Q <= D
TRUE FALSE Q <= 0
TRUE TRUE Q <= 0
Table 4-13 Illustration of generation of storage in Verilog


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4-1

Fig. 4-1 Block Diagram of a Sequential Circuit

© 2001 Prentice Hall, Inc.

Fig. 4-2 Logic Structures for Storing Information

© 2001 Prentice Hall, Inc.

(a) Block diagram

(b) Timing diagram of clock pulses

© 2001 Prentice Hall, Inc.

(a) Logic diagram (b) Function table

Fig. 4-4 SR Latch with NOR Gates

© 2001 Prentice Hall, Inc.

0.0 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns

Fig. 4-5 Logic Simulation of SR Latch Behavior

© 2001 Prentice Hall, Inc.

(a) Logic diagram (b) Function table

Fig. 4-6 S R Latch with NAND Gates

© 2001 Prentice Hall, Inc.

(a) Logic diagram (b) Function table

Fig. 4-7 SR Latch with Control Input

© 2001 Prentice Hall, Inc.

(a) Logic diagram

(b) Function table

© 2001 Prentice Hall, Inc.

Fig. 4-9 D Latch with Transmission Gates

© 2001 Prentice Hall, Inc.

© 2001 Prentice Hall, Inc.

0.0 50ns 100ns 150ns 200ns

© 2001 Prentice Hall, Inc.

Fig. 4-12 Master-Slave JK Flip-Flop

© 2001 Prentice Hall, Inc.

© 2001 Prentice Hall, Inc.

(b) Master-Slave Flip-Flops

(c) Edge-Triggered Flip-Flops

Fig. 4-15 Standard Graphic Symbols for Latch and Flip-Flops

© 2001 Prentice Hall, Inc.

(a) JK Flip-Flop (b) SR Flip-Flop

0 0 Q(t ) No change 0 0 Q(t ) No change

(c) D Flip-Flop (d) T Flip-Flop

0 0 Reset 0 Q(t) No change

Table 4-1 Flip-Flop Characteristic Tables

© 2001 Prentice Hall, Inc.

(a) Graphic symbols (b) Function table

Fig. 4-16 JK Flip-Flop with Direct Set and Reset

© 2001 Prentice Hall, Inc.

© 2001 Prentice Hall, Inc.

Present State Input Next State Output

Table 4-2 State Table for Circuit of Figure 4-18

© 2001 Prentice Hall, Inc.

Next state Output

© 2001 Prentice Hall, Inc.

Fig. 4-19 Logic Diagram and State Table for D A = A ⊕ X ⊕Y

Present state Input Next state Flip-flop inputs

Table 4-4 State Table for Circuit with JK Flip-Flops

© 2001 Prentice Hall, Inc.

0/1 0/1 1/0 01,10

00,11 0/0 1/1 00,11

© 2001 Prentice Hall, Inc.

1/0 1/0 1/0

1/0 1/0 0/0 1/1

1/0 1/0 0/0

Fig. 4-21 Construction of a State Diagram

Next State Output Z

Table 4-5 State Table for State Diagram in Figure 4-21