AXI Protocol Specification Important Points

Features:

1. supports high frequency,low latency and high performance system designs

2. Separate Address and Data Phases
3. Burst based transactions
4. Unaligned transfers
5. Out of Order Completion of Transactions
6. Overlapping of Transactions
7. Outstanding Transactions
8. Supports implementation of semaphore type operations using Exclusive Access.
9. Backward compatible with AHB,APB

Write Address Channel:

1. Signals starts with "AW" prefix.

2. Address and Control information about particular Transaction is sent over this
channel from Master to Slave.
3. Control Information includes
1. Burst length
2. Burst size
3. Burst type
4. Atomic Access
5. Cache
6. Protection Type
4. Handshaking Signals:
1. VALID : given by Master
2. READY : given by Slave
5. Signals in Depth:
1. AWID :
1. Write Address ID
2. This signal is the identification tag for the write Address group of
signals.
2. AWADDR :
1. Write Address
2. The write Address Bus gives the address of the first transfer in the
write Burst Transaction.
3. AWLEN :
1. Burst Length
2. It indicates exact number of transfers in a burst.
4. AWSIZE :
1. Burst Size
2. It indicates size of each transfer or beat in a burst.
3. Size of transfer is number of bytes to be transferred in each beat.
4. If size is specified as N then it transfers 2^N bytes
5. AWBURST :
1. Burst Type
 2. It details how the address for the each transfer within a burst is
calculated.
3. Burst Types :
1. Fixed Burst
1. Used for FIFO type access
2. Address remains same for every transfer in a burst.
2. Increment Burst
1. Used for Normal Sequential Memory
2. Address for the each transfer in the burst is an
increment of the previous transfer address. Increment
value depends on size of the transfer.
3. Wrap Burst :
1. Incrementing Address Burst that wraps to a lower
address at the wrap boundary
2. This is similar to an Incrementing Burst in which
address for each transfer is an increment of the previous
transfer address.
3. However, the address wraps around to a lower address
when wrap boundary is reached.
4. Wrap Boundary is decided by size of the each transfer
multiply by number of transfers in the burst.
5. Ex. Size of each transfer is 1 byte and number of
transfers are 4 and so, wrapping boundary becomes 4
bytes. Suppose wrapping boundary is specified from
100 to 103. Starting address is 101 then for this
transaction, transfer happens to location 101,102,103
and as wrapping boundary is reached, it wraps around
and Transfer happens to 100th location.
6. AWLOCK :
1. Atomic Access types
1. Normal Access
2. Exclusive Access
1. Exclusive Access Process
3. Locked Access
1. Locked Access

Write Data Channel:

1. Write Data is transmitted through this channel.

2. Signals : Prefix : "W"ID
1. WID
1. Transaction ID.
2. It must Match with AWID for that particular transaction.
2. WData : Data width can be 8,16,32,...
3. WStrobe :
1. It tells which Byte lane has Valid Data.
 2. For example, Data width is 32 bit and we want to transfer 16 bit data
so, strobe signal will tell which 2 byte lanes have this 16 bit data out of
4 byte lanes.
4. Wlast:
1. This signal when asserted indicates last transfer in a Write burst.
2. Suppose, length is 4 then for the 4th wdata on data bus,last signal is
asserted.
3. This signal indicates Slave that Master has completed transfers in that
particular write Burst.
5. VALID and Ready for Handshaking!

Write Response Channel:

1. Slave response back to Master through this Channel for Write Transaction.
2. Signals : Prefix "B"
1. BID :
1. Must match with AWID and WID.
2. Master identifies through BID that for which transaction id, this
particular Response is for.
2. BRESP : Slave can give 4 types of Response to Master.
1. OKAY :
1. For Normal Access Completion of Transaction.
2. For Exclusive Access, refer Exclusive Access note.
2. EXOKAY :
1. For Successful completion of Exclusive Access Transaction.
3. Slave Error :
1. If Slave is not able to complete transaction due to some reason
like
1. FIFO is Full and Write Transaction comes.
2. FIFO is Empty and Read transaction comes.
4. Decode Error :
1. Suppose Master issues a transaction which is not addressable to
any Slave.
2. Then, out of many slaves one slave is assigned as Default slave.
And this default slave gives Decode Error response to Master.
3. VALID and Ready signals for handshaking.
1. Here Valid is issued by Slave as he is the initiator.
4.

Read Address Channel:

1. Prefix : "AR" ex. ARID

2. Control Information signals are same as Write Address Channel.
3. Handshaking Signals :
1. ARVALID : Given by Master as he is the initiator
2. ARREADY : Given by Slave to indicate he is ready to accept information.
READ DATA Channel

1. Prefix : "R" ex. RID

2. Must Match with ARID Value of read transaction to which it is Responding.
3. R DATA : Read Data
4. RLAST : Indicates last transfer in read Burst
5. RRESP : response given by slave to Master
6. Handshaking Signals :
1. RVALID : Given by Slave as He is the Initiator
2. RREADY : given by Master to indicate that it can read data and Response
info.

Exclusive Access Process:

1. A Master performs an Exclusive Read from an Address Location.

2. At some later time, the Master attempts to complete the exclusive operation by
performing exclusive write to same address Location.
3. Exclusive Write Operation is signaled as :
1. Successful if no other master has written to that location between the Read and
Write Access.
2. Failed if another master has written to that location between the read and
Write access. In this case address location is not updated.
4. Exclusive Access from Perspective of Master :
1. Receives EXOKAY response from the slave for the Exclusive Read
Operation, indicating that the Slave has recorded the address to be
monitored.
2. Receives OKAY Response from the slave for the Exclusive Read Operation,
indicating that Slave does not support Exclusive operation.
3. Receives EXOKAY Response from the slave for the Exclusive Write
Operation to the Same location, indicating that location has Not changed since
exclusive Read and exclusive write operation is successful and Memory
location is updated.
4. Receives OKAY response from the slave for the Exclusive Write Operation to
the same location, indicating that address location is changed since Exclusive
Read and Exclusive Write Operation is Failed and Memory location is not
updated.
5. Exclusive Access from the Perspective of Slave :
1. If Exclusive Access is Not supported by Slave then it gives OKAY response
for both Normal and exclusive access.
2. Must have Monitor Hardware to support Exclusive Access
6. Exclusive Access Restrictions :
1. Master Must Not Commence Exclusive Write Operation until Exclusive Read
is Completed.
2. IDs for Exclusive Read Exclusive Write i.e. ARID and AWID must be Same.
3. All the Control information like Size, length must be Same for both Exclusive
Read and Exclusive Write Operations.
4. The address for the exclusive Access must be aligned to the Total number of
bytes in the transaction.
 5. Transactions MUST NOT BE Cacheable.

Protection Unit Support

1. AWPROT and ARPROT : 3 bit signals

2. Need :
1. To support Complex System Designs, it is often necessary for both the
Interconnect and the other devices in the system to provide protection against
illegal transactions.
3. AWPROT and ARPROT Signals address this need by providing three levels of access
protection :
1. 0th bit : specifies Normal or Privileged Access
2. 1st bit : Secure or Non secure Access
3. 2nd bit : Instruction or Data Access.
4.

Cache Support

1. AWCACHE AND ARCACHE : 4 bit

2. Using these Cache information signals, Support for System Level Caches and other
Performance enhancing Components is provided.
3. Additional support may be like :
1. Bufferable Transaction
2. Cacheable Transaction
3. Read Allocate
4. Write Allocate
1. For a transaction to be Read or Write Allocate transaction, it should be
Cacheable first.
4. Bufferable Transaction Support :
1. If a given transaction is signallled as Bufferable then Interconnect or (any
other component involved in) may delay the transaction reaching its final
destination (or Slave) for an arbitrary number of cycles.
2. If a Write Transaction is signallled as Bufferable then Interconnect or any
other involved component provides write response.
1. If it is not Bufferable then Slave or Final Destination should provide
the write Response.
2.

Locked Access

1. Requirement :
1. There Should Not be any outstanding transactions to complete from the
Master initiating Locked Transaction.
2. Achieved by Interconnect. Not by Master or Slave.
3. Interconnect must ensure that only that master is allowed access to Slave until an
unlocked transfer from same master completes.
4. Restrictions :
1. Locked Transaction must be followed by Unlocked transfer to remove locking
of locked slave. If Not, slave remains locked to that Master.
2. The Master must ensure that all transactions within a locked sequence have the
same ARID or AWID value.