DESCRIPTION ‘The R65C21 Peripheral Interface Adapter (PIA) is designed to ‘s0ive abroad range of peripheral control problems inthe imple- ‘mentation of microcomputer systems. This device allows a very effective trade-off between software and hareware by providing significant capablity and flexibility in a low cost chip. When ‘coupled with the power and speed of tho FI6500, RBSOOI" or R6SCOO family of microprocessors, the ABEC21 allows impie- ‘mentation of very complex systoms ata minimum overall cos. Control of peripheral devices is handled primarily through two B-bit bidirectional ports. Each ofthese lines can be programmed toactas either an put or an output. In addition, four peripheral controVnteruptinputlines are provided. These lines canbe used tointerrupt the processor orto "handshake” data between the processor and a peripheral device. r Ya fap om me? whew 338 B man qs wb Ree ds 4 Bae bas apo ea 2 po om bo om abo pe abo os x bor roe abe cad pes cor pose Yee 5 nw Peripheral Interface Adapter (PIA) R65C21 R65C21 FEATURES Low power CMOS Nell silicon gate technology Direct replacement for NMOS 6520 or MC6E2" PIA ‘Twos-bitbidirectional /O ports with individual data direction contol ‘Automatic “Handshake" control of data transfers ‘Two interrupts (one fr each port) with program control 1, 2,3, and 4 MHz versions. ‘Commercial and industria temperature range versions ‘Wide variety of packages = 40-pin plastic and ceramic DIP = 44-pin plastic leaded ehip cartier (PLOC) Single +5 Vac power requirement ‘Compatible with the R500, RG500/" and RSCOO family of microprocessors EgPaRSREEEE SeePeRee gag Figure 1. R65C21 Pin Assignments Document No. 29651N53 19 Product Description ‘Order No. 2150 Rev. 5, June 1987Peripheral Interface Adapter (PIA) R6SC21 ORDERING INFORMATION ba Part Number: Resear Le 0 Range (7, Ty) Blank = OC to +70°C E = -40%C to +85°C = T= Mie 22 aMae 52 ame a2 aMe | — Package © = 40-Pin Ceramic OP P = 40pm Plaste DIP 5S 4a-Pin Plastic Leaded Chip Carrie (PLCC) INTERFACE SIGNALS “The PIA interfaces tothe 8500, ASSO!" or the RBSCOO micro- processor famdy wih a reset line, a82clock ine, areadiwrte tine, {wo interrupt request ines, two register select lines, three chip select ines, and an 8 bidirectional data bus, ‘The PIA interfees to the peripheral devices with four interrupt control ines and two 8-bidirectional data ports. Figure 1 (on the front page) shows the RESC21 PIA pin assign ‘ments and Figure 2 groups the signals by functional interface. CHIP SELECT (CSO, CS1, CS2) “The PIA is selected when CSO and CS1 are high and TSE is low. These three chip select lines are normally connected to the processor address lines either directly or through external ooor ° RSSO0, a be nso oR cso nescoo oe wicedenocesson ) 8! van a decoder circuits, When the PIs sloctod, data willbe transferred between the data ines and PIA registers, andlor peripheral nter- face lines as determined by the RAW, ASO, and RS1 lines and the contents of Control Registers A and 8. RESET SIGNAL (RES) ‘The Reset (RES) input initalzes the RBSC2t PIA. A low signal ‘on the RES input causes all imtornal registers tobe cleared. CLOCK SIGNAL (02) ‘The Phase 2 Clock Signal (82) s the system clock that triggers alldata ansters behweon tho CPU and ihe PIA. 62s generated bythe CPU andis herafore the synchronizing signelbetween the CPU ana the PIA. READ/WRITE SIGNAL (R/W) ‘sade (AW) controls the drecion of data transfers between the PIA and the data lines associated with the CPU and the peripheral devices. RIW high permits the peripheral devices to transfer data to the CPU from the PIA. IW low allows data to be transfered from the CPU to the peripheral devices from the PIA, REGISTER SELECT (RSO, RS1) “The two Register Select ines (ASO, RS1),in conjunction wth the Control Registers’ (CRA, CRB) Data Direction Register access bits select the various R65C21 registers 1 be accessed by the CPU. RSD and RS! are normally connected to the microprocessor (CPU) accross output lines. Through contol ofthese lines, the (CPU canwrite dzecty into the Control Registers (CRA, CRB), he Data Direction Registers (DRA, ODAB) and the Peripheral Out- put Register (ORA, ORB). adton, the processor may directly ead te contents of the Control Registers and the Data Direction Registers. Accessing the Peripheral Output Register forthe pur- ‘pose of reading data back into the processor operates ciferenty fon the ORA and the ORB registers and, therefore, are shown separately in Table 1 PERIPHERAL, Ke Paorar Dever —— car 7 [$———» caz scat PA jo car PERIPHERAL i DEVICE e Figure 2. R65C21 ACIA Interface Signals 120Peripheral Interface Adapter (PIA) R65C21 ‘Table 1. ORA and ORB Register Addressing Regier [Data Dect regina |Selet Lines] Control | Regatar Operation caress cra [cra] = ex) [ast | nso | an 2)|cen2) niweH o Pe] et | a | — |pea rea |wito ona 0 | ct | t | 0 | = |pead poRalwreo OORA a fetal lRead CRA [wae CRA 2 |u| cy] — | 1 |peaaPe |wae ons 2 || c | = | o {mead DoRe|wee ooRE a | | & | — | — |peascra [wie crs INTERRUPT REQUEST LINES (IRGA, IRB) “The active low Interrupt Request lines (QA and TRGB) act 0 Interrupt the microprocessor either directly or through external imerruptpronty circuitry. Theeelines are opancrain and arecapa- ble of sinking 1.6 mA from an external source. This permits all, interrupt request lines tobe tied together in a wired-OR contigu- ration, The A and Bin the titles of these lines correspond to the Peripheral port Aand the peripheral port B sothat each interrupt request line services one peripheral data port Each Interrupt Request ine has two interupt fag bits which can ‘cause the Interrupt Requestline to golow. These flags are bts & ‘and 7 inthe two Gontrol Registers (CRA, CRB), These flags act 28 the link between the peripheral interrupt signals and the ‘microprocessor interrupt inputs. Each fag has a corresponding Intoruptaisable bit which allows the processor to enable or dis- ‘able the interrupt from each o the fourinteruptinputs (CAT, CA2, (©B1, CB2). The four interrupt lags are set by active transitions ‘ofthe signal on the interupt input (CAT, CA2, CB1, CB2) (CRA DIt7(IROAT) is always set by an active transition ofthe CAT imerrupt input signal. However, [RGA can be disabled by setting bit 0 in CRA to a 0. Likewise, CRA bit 6 (IROAZ) is set by an active transition of the CA2 Interrupt input signal and IRQA can be disabled by seting bit 3 in CRA toa 0. Both bit6and bit7 in RA are resetbya "Read Peripheral Output Register A" operation. This s defined as an operation in which ‘the readiwnte, proper data ection registr and register select ‘signalsare provided to allow tne processor toreadthe Peripheral A-WO port. A summary of IRGA control is shown in Table 2 Contro! of IRB is performed in exactly the same manner 2s ‘that described above for RGA (Table 2). Bit 7 in CRB (ROB!) is set by an active transition on CB! and IRQB trom this flag 's controled by CRB bit 0. Likewise, bt 6 RGB2) in CRB is set by an active transition on C82, and IGE from this tag is controled by CRB bit3. Also, both bit6 and bt 7 of CRB arereset by "Read Peripheral B Output Register” operation. Table 2._ TRA and iF'GB Controt Summary ‘Aeon IGA goes low Active) IGA goes low Active) ROB goes low (Active) 1B goes low (Active) Control Register Bi ‘GAA =1 and CRAO=1 ‘GAAG= tend CRAI=1 (CAB7= tend CRBO=1 ‘CAB-6=1 and CRBS=1 F a) 421 INTERRUPT INPUT/PERIPHERAL CONTROL LINES (CA1, CA2, CBI, CB2) ‘The four interrupt inpuperipheral contol ines provide a num- ber of special peripheral control functions. These Ines greatly {enhance the power of the two general purpose interface ports (PA0-PAT), PBO-PB?). Figure 4 summarizes the operation of these contol nes. CCA isan interrupt input only. An active transition ofthe signal ‘on this input wl set bit 7 of the Control Register A toa logic 1. “The active transition can be programmed by setting ain bit ofthe CRA tthe intoruptfiag bit 7 of CRA) is tobe setonanega- tivetransitionofthe CA1 signalora itis tobe setonapositive transition, ‘CA2 can actas a totally independent interrupt or asa peripheral Controloutput. Asan input (CAA, bit = 0)itactsio set the inter- ruptfag,bit6of CRA, toalogic 1 on the active transition selected by bi 4of CRA, “These contro egistr bits and interrupt inputs serve the same ‘basi function as that described above for CA1. The input signal ‘sets the interupt flag which serves as the ink between the peripheral device andthe processor interupt structure. Theinter- ‘uptcisable bit allows the processor o exorcise contol over the system interupt {nthe output mode CRA, bits = 1), CA2 can operate indopend- ently to generate a simple pulse each time the microprocessor reads the data on the Peripheral AVO port This madeis selected by seting CRA, bit 4 to @ and CRA, bit 3to@ 1. This pulse out- putcan be used to contolthe counters, shiftregisters, ec. which ‘make sequential data available on the Peripheral input lines. ‘Asecond output mode allows CA2 tobe used in conjunction with CAI to "handshake" betwoen the processor and the peripheral ce Figure 3. 122 R65C21 PIA Block DiagramR65C21 Peripheral Interface Adapter (PIA) Table 3. Control Registers Bt Designations 7 [8 5 3 2 _ DORWORA ro (oat conta 7 T+ 3 2 T° ens [mas | nace Donaions 31 ol DATA DIRECTION REGISTERS (DDRA, DDRB) “The Data Direction Registers (ODRA, DAB) alow the processor ta program each line in the @-bit Peripheral VO porto be ether ‘aninputor an output. Each bitin DDRA controls the correspond ing ing in the Peripheral A port and each bitin DDRB controsthe corresponding linen the Prigheral 8 por. Writing aOin abitpost tion in the Data Direction Register causes the corresponding Peripheral WO line to act as an input; a 1 causes itto act as an output 'it2in each Control Register (CRA and CRB) controls accoss to the Data Direction Register or the Peripheral interface. Mbit 2s 21, @ Peripheral Output register (ORA, ORB) is selected, andi! bit2 is 0, aData Direction Register (DRA, DORB) s selected The Data Direction Register Access Control bit, together wth the Register Select lines (ASO, ASt) selects the various internal ragistors as shown in Table 1 PERIPHERAL OUTPUT REGISTER (ORA, ORB) ‘The Peripheral Output Registers (ORA, ORB) store the output data from the Data Bus Butters (O88) which appears on the Peripheral] port. ta tine on the Peripheral A Portis pro- ‘grammed as an output by the DDRA, wring a 0 into the cor- ‘esponding bitin the ORA causes that line to go low (=0.4 Vac), iting a1 causes the ine to go high. The lines ofthe Peripheral 8 por are controled by ORB inthe same manner. INTERRUPT STATUS CONTROL (ISCA, ISCB) ‘The four interruptiperipheral control ines (C1, CA2, CB1, C82) ‘are controlled by te nterupt Status Controtioic (AB). Tislogic Interprots the contents ofthe corresponding Control Register and ‘detects active transkions on the interupt inputs, PERIPHERAL 1/0 PORTS (PAO-PA7, PBO-PB7) “The Peripheral A and Peripheral 8 VO ports allow the micro- ‘processorio interface tothe inputlines onthe peripheral device bby writing datainto the Peripheral Output Register. They also allow the processor interface withthe peripheral device outputtines by reading the data onthe Peripheral Port input lines directly onto the data bus and into the intemal registers ofthe processor. Each of the Peripheral YO lines canbe programmedio actas an inputor an output. This is accomplished by sttinga 1 in tho cor. responding itn te Data Direction Register for those ines which are to act as outputs, A On abit ofthe Data Direction Register ‘causes the corresponding Peripheral /O nes toact as an input ‘The butfers which drive the Peripheral A VO lines contain "pas- ‘sive pull-up devices. These pull-up devices areresstive in nature and therefore allow the output voltage to gote Voc for a logic 1. ‘The switches can sink fll3.2 mA, making these butts capa ble of driving two standard TTL. loads. Inthe input mode, the pulFup devices are stil connected othe {UO pin and stil supply current this pin, For ths reason, these lines also represent two standard TTL loads inthe input mode. ‘The Peripheral BVO por duplicates many ofthe functions ofthe Peripheral A port. The process of programming thesetines toact {a an input or an output similar tothe Peripheral A port, as is the efec of reacing or wring this port. However. there are saver ‘characteristics of the butters diving theselines which affect he use in periphoral interfacing “The Peripheral 8 VO port butters are push-pull devices, ie. the pull-up devices are switched OFF in the 0 state and ON for a logic 1. Since these pulkups are active devices, the logic 1 votage will not go higher than +2.4 Vac. ‘Another difference between the PAO-PAT lines and the PEO ‘through PB7 lines i that they have three-state capablity which allows them to enter a high impedance state when programmed tebe used as input ines. In addition, data on thess lines wil be ‘ad properly, when programmed as oulputlines, even the data signals fall below 2.0 Vdc fora high” state or are above 0.8 Vdc fora “iow” state. When programmed as output, each line can drive at least a two TTL load and may also be used as a source of upto3 2mAal 1.5 Vdc to directly drive the base ot transistor ‘iteh, such as a Darlington pate Because these outputs are designed to drive transistors directly, ‘the output datas read direct rom the Persheral Output Register {or thase lines programmed to act as inputs ‘The final charactorsticis the high-impedance input stato which {is a function ofthe Peripheral B push-pull butlers. When the Peripheral 8 1O Ines are programmed 0 act as inputs, the out: put buffer enters the high impedance state. DATA BUS BUFFERS (OBB) ‘The Data Bus Butfors are &-bit bidirectional buffers used for data ‘exchange, onthe D0-D7 Data Bus, between the microprocessor land the PIA. These butlers are tri-state and are capable of div- ing a two TTL load (when operating in an output mode) and representa one TTL load tothe microprocessor (when operating in an input mode).R65C21 Peripheral Interface Adapter (PIA) CONTROL REGISTER A (CRA) (CA2 INPUT MODE (BIT 5 = 0) 7 6 3 a 3 2 1 o Toar | iRGA2 | _CABINPUT Thon ROR ‘ODRAORA TROAT aa ruc | Flac | mooesetect | TransiTion | ENABLE SELECT. | TRANSITION | ENABLE or seuect | _FORIROAZ ‘SELECT FOR IROAY TROATROA? TROAMROAT ‘CONTROL CONTROL (CA2 OUTPUT MODE (BITS = 1) 7 3 3 a) a 2 1 a Tan ° ‘cAz OUTPUT xe cae DORAIORA RON TRON FAG Mone sevect | ouTPUT restore | setecr | TRANSITION | ENABLE Co contac, | CONTROL SeecT | _FORIROAI az TRGAIROAT CONTROL CONTROL ee? CA2 INPUT OR OUTPUT MODE (BIT 5 = 0OR 1) 1ROAT FLAG. ‘Avvansion hs occured on CAt hat eteies the bit 1 RGA transton polar ctoria, This itis cleared by a read of Oupu Register A cory RES. Ne tanston has cecurred on CAt that stifle thet 1IROAT transition polarity crite. DATA DIRECTION REGISTER A/OUTPUT REGISTER A SELECT Select Output Registar A. Select Data Dretion Register A IROA1 TRANSITION SELECT Sel ROA1 Fag (Bt 7) on a posive (ow ehigh) ransiion of CA Sel ROAt Flag it 7) on anepalve (aghio%ow)transtion of CAN, RGA ENABLE FORIROA Enable assertion of RGA when IRQA’ Flag ot 7's Set Disable assertion of HOA when IRCAT Flag (7s sot Bus 1 CCAR INPUT MODE (BIT 5 = 0) CA2 OUTPUT MODE (BIT 5 = 0) 1ROAZ FLAG Bie NOTUSED ‘tration has occured on OA2 tha satisfies thoi ¢ 0 Aways zoo TROA2 ranston olay esteria. The fag eared by ‘8 e9ad of Output Register A or by RES. fear] Coxe woe seer "Notranston has oocurred on CA that satisfies the Mitt consrcxeoncertiece Dt IROA2 vansiion polantycrtoria ita cA2 OUTPUT CONTROL ‘GAZ MODE SELECT 1 GAB goes low when a ze is wrt nto CRA D3. Select CA2 Input Mode, (GA2 goes high when a one is wit into CRA bit. | © GA goes low one ret nogaive rgh-osow) 2 clock §ROA2 TRANSITION SELECT | transtion folowing @ fad of Output Rogistor A ‘SetIRQA2 Fiag(t6)on aposiiveow-toign) transition | GAZ rturs high a epecti by Bt 3 orcae. ‘SetIROA2Flag(it8)on angie (igho4ow) ransion ‘BR3 _CA2 READ STROBE RESTORE CONTROL (4 = 0} ofcaz. 1 GAB turns high onthe next 82 clock nepatve a {ranstion following a read of Output Rogstor A IRGA ENABLE FOR IRQAZ 0 CAzretums high on the next ate CA wansiton Enable assertion of RGA when IRQA2 Fag (ht 6 is st folowing a read of Output Regstor Aas spectiod by Disable assertion of HOA when IROAZ Flag (6) et. bat Figure 4. Control Line Operations Summary (1 of 2) 128R65C21 Peripheral Interface Adapter (PIA) CONTROL REGISTER 8 (CRB) (CBR INPUT MODE (BITS = 0) 7 6 5 4 3 2 i ° iro | wmose | cezinpuT ROB Roe DORBIORE ROB cd Flas | Flas | MODEScLECT | TRANSITION | ENABLE ‘setect | TRANSINON | ENABLE (=9) seuct | _FoRimase sevect | FORIROB! wRasnnaee TRGBAROSt ‘CONTROL { CONTROL (©82 OUTPUT MODE (BITS = 1) 7 ‘ s “ 3 2 7 a R08 ° ‘o32 ouTPUT ca cae DORBIORE ROB Ras FLAG MDE sect | OUTPUT restore | SELECT | TRANSITION | _ ENABLE =) conTRoL | CONTROL SELECT FOR IROBt 52. TRGBNROBT CONTROL CONTROL (€B2 INPUT OR OUTPUT MODE (BIT 5 = 0 OR 1) n7 ] inoBI FLAG 1” | transition nas occurred on Ct that aise the bt 1 ROB: trans polar cto, This biti cleared by aad of Output Rogistr B or by RES, 0 | Novwanstion nas occured on C81 that satiss the bit 1 IAOB! tanstion pean eters, tan 2 | DATA DIRECTION REGISTER BIOUTPUT REGISTER SELECT 1 | Select Output Register 8. 0 | Sect Data Ovoction Rosser 8 ts | snot TRANSITION SELECT 1 | SotROB% Fag (bt 7) ona postive fowt-high ransion of CBI 0 | Setima8: Fag (bt 7) 09a negative (igh low) ranstion of Bs tro | IRB ENABLE FoR IRBs 1 | Enable ascorion o TRB when IROB! Fag (bt 78s. | Dlzable arcorton of ROB when IFO} Flag (ot 7) et (CB INPUT MODE (BITS = 0) (€B2 OUTPUT MODE (BIT 5 = 0) ‘ene nae FLAG ‘Bie NOTUSED 1 Attansiton has occured on CB2 tha satsfos the Bt 6 © Aways zero 1RQB2 vansiton polarty eteia. Ths fags cared by ‘road of Output RegistrB or by FES, wns ceamovasausct © Novanstion has occured on C82 that satisfies the fie coosicos oucnisas ‘iA TROBE wanton platy eter, oun ‘ IT CONTROL, fs ceamoe seuecr oN See gestion when sols itn ino CRB 2. © Select C82 ipur Made ‘C82 goes high when a one's written ito CRE bi 3 (© CBZ goes low onthe fst negative righ-o tow) #2 cock ‘8h 4 O82 TRANSITION SELECT ‘ans folowing ard of Output Register 8 1 SetlRGB2Flag Bit ona postive (low-high ransiton ‘CBE returns righ as spociiog by bit orca, © SatIRGB2 Fiag it )ona negative tightotow)ransiion ‘Ba CB2 READ STROBE RESTORE CONTROL (4 | ote. 1 CB2rotuns high onthe nest 2 clock nogstve | ‘rans follwing a read of Output Regist 8 ‘53 iROS ENABLE FOR ROB © GB2 returns igh onthe neat aetve CBI Wansiion “1 Enable asgotion of ROB whon tROB2 Fig (bt 6's se. folowing a read of Output Register B a spectod by 0 Disable aecorion of ROB when IROA2 Flag ft 6):6 sat. bet Figure 4. Control Line Operations Summary (2 of ) 125R65C21 Peripheral Interface Adapter (PIA) READING THE PERIPHERAL A /0 PORT Performing Read operation with RS1 = 0,S0 = andthe Data Direction Register Access Controlbit(CRA2) = 1, directly trans- {ers the data on he Peripheral A /0 ines tothe databus. nthis situation, the data bus willcontain both the input and output data, ‘The processor must be programmed to recognize and interpret only those bits which are important to the particular peripheral ‘operation being pertormed ‘Since the processor aways reads the Peripheral AUO port pins Instead of the actual Periphoral Output Register (ORA), I is possible for the data read by the processor to difer from the Contents ofthe Peripheral Output Register for an output ti This is true when the VO pin is not allowed to go to a full +24 Vde when the Peripheral Output register contains a logic 1. {this case, the processor wil read a0 fromthe Peripheral A pin, ‘even though the corresponding bitin the Peripheral Output rogistor isa 1 READING THE PERIPHERAL 8/0 PORT Roading the Peripheral B UO port yields a combination of input fand output data in a manner similar to the Peripheral & port However, data is ad directly trom the Peripheral B Output Register (ORB) fr those lines programmed to act as outputs. t is therelore possible to load down the Peripheral Output ines wiiout causing incorrect data to be transferred back to the processor on a Read operation. coz (HAND SHAKE) Figure 5, Reed Timing Wavetorms 428R65C21 Peripheral Interface Adapter (PIA) a2 (HAND SHAKE) Figure 6. Write Timing WaveformR65C21 Peripheral Interface Adapter (PIA) ‘SWITCHING WAVEFORMS Wor = 5.0 Vde £546, Vgg = 0,7, = T, 10 Ty unless otherwise noted) BUS TIMING Tie awe Sate amie Parameter ssymot [win | wax | min, [Moc | min | Max | ine [Mx | Unit ‘oxce ic ac ren ers | ee os =v $2 Pulse With te | «0 [ — [a0 10 [= | 0 | — | oe #2 ise od Fal Tine ean a re ee ee |e [r= foe re Read Dasiss Seni Tine ta [oe [wf [s[-~sel-T= eres Hold Tine ‘oa | of - | of-] of-|o]— |r Peripheral Data Sap Tw ‘ren | 200 [= | wo [ — | no | — | ms | — [rs ‘Data Bus Delay Tine ‘con |= [sus [= [es [sos [as To ‘Data Bus Hod Time a write asros Setup Tine to [wf [wt-Ts}-Tsel-To ‘dross Hold Tine Tou [et =}6)- | of- | of -1 = IW Setup Time ‘wey | 80] — | oo] — | [- | 6] — | PAW Hos Tine r of=- ,e{-| of— | e|— | ‘Data Gus Get Up Tine F sacra cr aoe reo alee ‘Data Bus Hold Time a ripheral Data Delay Tine ew | = [10 | = [es | — [os [ —Tos [ Peripheral Data Day Tine ‘ws | - | 20] —- |e | — for | — [os | « *2CMOS Love PERIPHERAL INTERFACE TIMING Perper Oats Setup a €2 Low 19 CA2 Lon Doay i Sarna rte as e|oe—n sl| e €2 Low 9 CAS High Doay te = | wo [= [os | = [es | — | os 1s ‘CAI Aatve 10 CA2 High Daa “ = [20 [= Po [= [io | — P10 fs €2 High 9682 Low Day te | = [10 | = [os | — [os | — [os |» Furphwral Daa vatste CSPLowDeey | toc | 0 | 15 | o | or | 0 | os | 0 | oa7 | €2 High 1 C82 Hag Ostay te | = [10 | — [es [= [os | — [os [os (C8 Acie o 82 High Daly tee [= 0 [= fo | = [oer | — [0s Te ‘AI, CAZ, CBI and C82 wr | = pro | — fro | — peo | — [oo | {rout ise ana Fal Tne NOTE: Timing measurements ar roleronced to and from a low voage of 0.8 Vac anda high voltage of 2.0 Ve. 128R65C21 Peripheral Interface Adapter (PIA) “ABSOLUTE MAXIMUM RATINGS* Pareneter Smmbot| Vane [Unt] “NOTE: Strses above thse listed may cause permanent = Te} casw 270 Toe ‘Gamage tothe even, Thsis stress rating ony and uncial opt Cotsae % ve operation of the device at these or any other conditions above eae Mo = 0.8 10 Vor +0:3 | Vee. those indicated in other sections of this document is not implied. apa von Warr] =0310Vee +03 [Woe Exposure tabsolue maximum ratingcondtons or extended poratng Tonperatr Range) Ts 7c pods may afect device reli ‘Sonera ow +70 ina woe +85 Serge Torpwatwe | Tare [S510 #1501 OPERATING CONDITIONS Parameter ‘Symbol_[ Value ‘Supply Voliage Noo | 5V 35% Teperaure Range | Tx ToT Conard oterwiore fraosat | etc emsec ELECTRICAL CHARACTERISTICS (Vee = 5.0 Vde #58, Veg = 0,T4 = T,10Ty, Unies otherwise noted) prameter ‘Symbot Min. Typ? Max. Unit? | Test Conditions ino ah Vota vw [80 = Yes v input Low okage _ ve | =08 =~ [oa input Leakage Cure 5 A Waves Fu REE SO Rt, C80, C83, CMY, COI, 82 s 25 veo sav or S soo int Lago OuretTee Sate OF Te = Fr 0] pk ys avy 20-07, ren Por, coe Mines ing rh Curent we 8 = wes 20v pao Sar. cnt Tiga Low Curent ie = 2] ae ee pao. Par Oe Outpt igh Vorage Yor 7 Wes av 2a = : Woo toua 80:57, C82 (Carngon Dv) i = = _|t2 2 =m Saipan votage Ya = = soa 7 Wee = 4757 on0-Pny, cad, pao-Fe7, C82 Wes mn 5oco7, ROA GD oo =item Outot gh Curent Couch) ioe 4 zo | 1500 | - th Nou = 24v eb: P67, C82 (Ouington Drv) os * = me Welty | Sain Low Cure ira) St t No. = ov AO-PAT Bon PS? CBE, CA2 a2 = - ma boco7, ROA OE % = {= m ual eatage Curent OF Sas) ae 7 wo | oA Wes Ba hoa Roe Pee Power Osan 7 = 7 one input Capeciance Sn Nec = 807 | ISSa.DI pan Pn, P0.P67, a2, cB = 5 we feo iW RES so Fst 050,651 OSE = = ° pe (tau = = co ee = es 7 70 ra Notes 1 ks are det cure (except cepactnce 2 Nogunre sy icates outwar ae‘ aw, poste ats nward ow 3 Tyna vloe ae shown fo Veg = SOV andy = 26 129R65C21 PACKAGE DIMENSION! Peripheral Interface Adapter (PIA) ‘40-PIN CERAMIC OIP 44-PIN PLASTIC LEADED CHIP CARRIER (PLCC) Tor view pms EJECTOR om MARS ets pen Sues Eousry “aaron orn ‘rvprcat) porroM view J SEATING PLANE [crane [is] [ave | cap [eves forms TON AA ‘T¥P FOR BOTH AXIS (EXCEPT FOR BEVELED EDGE)