Link Material

1
 Lesson-2
Operating principle and characteristics of a p-n junction
diode (L2.1)

A p-n junction diode is formed by placing p and n type semiconductor materials in

intimate contact on an atomic scale. This may be achieved by diffusing acceptor
impurities in to an n type silicon crystal or by the opposite sequence.

A junction is characterized by the doping level (impurity atom density). In a step junction
accepter atom density has a high constant value in the p region and a very low value in
the n region. The opposite holds true for the donor atom density. In a graded junction
impurity density changes more gradually across the junction. Fig.1 shows a typical plot
of impurity densities for both types of junction.

Back
Back to “reverse saturation current Is”

2
Fig. 1: Schematic diagram and impurity atom densities in a p-n junction (a)
Schematic diagram, (b) Impurity density in a step junction, (c) Impurity density in a
graded junction.
For the rest of the discussion a step p-n junction will be assumed. In an open circuit p-n
junction majority carriers from either side with defuse across the junction to the opposite
side where they are in minority. These diffusing carriers will leave behind a region of
ionized atoms at the immediate vicinity of the metallurgical junction. This region of
immobile ionized atoms is called the “space charge region”. Accumulated space charges
give rise to an electric field and potential barrier at the junction which opposes the
diffusion of carriers. Once the electric field and the potential barrier develop to sufficient
level, migration of carriers across the junction stops. At this point the p-n junction is said
to have attained “thermal equilibrium”. A some what idealized plot of the variation of the
space charge density, the electric field and the electric potential along the device is shown
in Fig 2.

Fig. 2: Space charge density, electric field and electric potential inside a p-n junction
in thermal equilibrium; (a) schematic diagram; (b) space charge density; (c) electric
field; (d) electric potential.

The space charge densities in this idealized representation are assumed to be step
functions of magnitudes –Na and Nd on the p are n sides respectively over the space
charge regions (-Wpo in the p side and Wno in the n side).

3
Under this assumption the electric field strength is obtained by solving the one
dimensional Poisson’s equation.

dE ( x ) -qNa (1)
= - Wpo < x �0
dx �
E ( -w ro ) = 0
-qNa ( x + Wpo ) (2)
\E ( x ) = , - Wpo < x �0
�
dE ( x ) qNd
= 0 < x �Wno (3)
dx �
E ( Wno ) = 0
qNd ( x - Wno ) (4)
\E ( x) = 0 < x �Wno
�
-qN a Wpo (5)
From (2) Emax = E(0) =
�
-qN d Wno (6)
From (4) Emax = E(0) =
�
Since E(x) is continuous at x=0, from (5) and (6) (7)
N a Wpo = N d Wno
Wno q ( N a Wpo 2 + N d Wno 2 ) (8)
Now fc = - � E ( x ) dx =
-Wpo 2�

Using (7) in (8)

qN a Wpo ( Wpo + Wno ) qN d Wno ( Wpo + Wno ) (9)
fc = =
2� 2�

Substituting Wpo + Wno = Wo = Zero bias space charge layer width

2 �fc 1 2 �fc 1 (10)

Wpo = ; Wno =
qWo N a qWo N d
2 �fc N a + N d
\ Wpo + Wno = Wo =
qWo Na Nd

2 �fc ( N a + N d ) (11)
\ Wo =
qN a N d
2fc (12)
From (7) & (10) E max =
Wo

4
In all these equations q is the charge of an electron and � is the dielectric constant of the
semiconductor material.
When an external voltage V is applied across the p and n sides, it adds or subtracts with
the contact potential fc . If the p side is made more positive with respect to the n side
(assumed positive convention of V) it subtracts from fc . Since the potential barrier
reduces, the width of the space charge layer and the maximum electric field strength at
the junction also reduce. The p-n junction is said to be forward biased under this
condition. Reversing the polarity of V (i.e reverse biasing the p-n junction) has the
opposite effect.

Application of an external voltage does not qualitatively change the shapes of the space
charge density, electric field or the electric potential distribution. Therefore, all the
relationships given so far hold good with suitable modifications. In particular

W(v) = Width of the space charge region with applied external voltage V

2 �( N a + N d ) 2 �fc ( N a + N d ) � V �
= ( fc - V ) = 1-
� �
qN a N d qN a N d � fc �

or W(v) = Wo 1 - � � (13)
�v f �
� c�

2fc �
1- V �
�
2 ( fc - V ) � fc �
�
Similarly E max ( v) = =
W ( v) Wo 1 - V
fc

2fc (14)
or E Max ( V ) = 1- V
Wo fc

Calculation of Reverse Break down Voltage (L2.1.2) Back

Equation (14) indicates that the maximum field strength at the metallurgical junction
increases with the reverse bias voltage (V negative). At some critical value of V = -V B
E Max reaches impact ionization value EB. At this electric field strength free electrons
gain sufficient kinetic energy to break other electrons free from the valance bonds. This
impact ionization field strength (EB) depends on the magnitude of the energy band gap
(between conduction and valance bands) of the semiconductor material and has a typical
value of 2 x 105 V/cm for silicon. If the reverse bias voltage exceeds V B impact ionization
will release a large number of free carriers by avalanche multiplication process and the p-
n junction will undergo “reverse break down” characterized by a large reverse current

5
(from n to p side) flowing across the junction. Such large current quickly destroys the
junction by over heating. Therefore, a p-n junction should never be operated at reverse
break down voltage. The reverse break down voltage can be calculated as follows.

From (14) putting E Max ( VB ) = E B and V = - VB

2fc VB
EB = 1+
Wo fc

Wo 2 E B 2 Wo 2 E B 2
OR VB = - fc � (Q fc << VB )
4fc 4fc

Substituting the expression of WO from (11) in to the above equation

�( N a + N d )
VB = E B 2 (15)
2qN a N d
Calculation of the Forward and Reverse Current Densities
(L2. 1. 3) Back to “equation 2.1”
Back to “forward biased p-n junction equation”
Application of external voltage not only changes the width of the space charge region
(also called “depletion region”) but also have very prominent effect on the excess
minority carrier density distribution as shown in Fig. 3.

6
Fig. 3: Excess minority carrier density distribution in a p-n junction (a) under
forward bias condition; (b) under reverse bias condition.
A forward bias voltage lowers the potential barrier and allows a large number of carriers
to change sides. It is known from the “law of the junction” that the minority carrier
density at the edge of the depletion region of a forward biased p-n junction is given by

qv
pn ( o ) = p no e KT
(16)
qv
np ( o ) = n po e KT
(17)
Where pno an npo are thermal equilibrium minority carrier densities in the p side and the n
side respectively and V is the applied voltage.

From basic semiconductor physics relationship

n2 n2 (18)
pno = i & n po = i
Nd Na
Where ni is the intrinsic carrier density in the semiconductor material.

Injected minority carriers recombine with majority carriers as they defuse further in the
electrically neutral region of the semiconductor body. In steady state minority carrier
density is exponentially distributed in distance from the junction on either side. i.e.

-x
np ( x ) = np ( o) e Ln (19)

-x

pn ( x ) = pn ( o ) e (20)
Lp

where Ln and Lp are diffusion lengths of n and p type carriers in the p and then type
regions respectively.
Hatched portions of Fig.3(a) represent stored excess minority carriers in the p and the n
type regions respectively.

n p ( o ) - n po �
Qn = q �
� �Ln (21)

p n ( o ) - p no �
Qp = q �
� �Lp (22)

Now in steady state forward bias condition excess minority carrier distributions shown in
Fig. 3 (a) remain stationary which implies that the carriers lost per unit time by
recombination must be replaced by forward current IF

dQ p dQ n
i.e. JF = + (23)
dt dt

7
From basic semiconductor physics the recombination dynamics is given by
dQ n Q dQ p Q (24)
= - n and =- p
dtτ n dt τ p

Where τn an τp are carrier lifetimes of n and p type carriers in the p and the n type
regions respectively.

Combining (23) and (24)

Qp Qn �L n Lp � �KTqv
�
JF = + = q ni2 � + �� -1�(25)
e
τp τn �Na τn Nd τp �� �

Equation (25) also holds for reverse bias condition i.e. when v is negative. For sufficient
reverse bias the reverse saturation current density is given by.
�L Lp �(26)
Js = q ni2 � n + �
�Nτ
a n N τ
d p �
(27)
\ JF = Js � e KT -1 �
qv
� �
� �
Equations (26) and (27) define the i-v characteristics of a junction diode under reverse
and forward bias conditions respectively.

8
TURN ON Behavior of a Power Diode (L 2.2) Back

Fig. 1: Forward current and voltage waveforms of a Power Diode during Turn ON.
Several physical mechanism as explained below takes place during Turn ON of a
diode.

From time 0 to to growing forward current charges the depletion layer capacitance formed
by the space charge of the drift region. The diode voltage increases gradually to the
forward bias junction voltage VF at which point the metallurgical junction p+ n- becomes
forward biased. Minority carrier densities in all the sections of the diode just reach their
respective thermal equilibrium levels at this point.
Although the diode is forward biased after t o, the forward voltage drop across the device
keeps on increasing with the forward current for same more time. During this period the
drift region offers significant resistance due to insufficient carrier injection. Stray
inductance of the wafer and bonding wires, coupled with the forward di F/dt, also
contributes to the increase in the forward voltage drop.
Finally after time to+t1 resistance of the drift region starts decreasing due to conductivity
modulation. Forward current also reaches its steady state value “I F” and diF/dt becomes

9
zero. As a result, the waveform of the forward voltage drop turns over and starts
decreasing, reaching steady state value “VF” in time t2.
The peak voltage drop across the diode is called the forward recovery voltage and is a
strong function of the forward diF/dt, The time interval t1 is a function of the forward diF/dt
with typical values in hundreds of nanoseconds. However, t 2 is more or less constant for a
given diode with typical values less than 10 us. The time period t1 + t2 is often called the
forward recover time (tfr).
The next diagram explains the diode Turn on process.

10
Reverse Recovery characteristics of a power Diode

Back to “Turn Off Behavior”

Back to “Diode”

Fig. 1: Reverse Recovery characteristics of a power Diode.

Conceptually the Turn off process of a diode can be through of as the reverse of the Turn
on process. Excess minority carriers injected into the drift region during Turn on have to
be removed before the diode can start blocking reverse voltage.
The reverse recovery current sweeps out excess carriers from the drift region. At the end
of time period t3 minority carrier density in the p+ and n+ regions are already at their
thermal equilibrium level. However, there is still a large amount of excess carriers
trapped in the drift region which is then removed by the reverse recovery current during
time period t4. During this period minority carrier densities in the p+ and n+ regions do not
change very much. At the end of t4 too few carriers exist in the n- drift region to support
the reverse recovery current demanded by the stray circuit inductance.
Recovery current starts falling sharply while the reverse voltage across the device
starts growing. Stay circuit inductance, coupled with large falling rate of the recovery
current, can give rise to a peak reverse voltage (V rr) far in excess of the steady state
blocking voltage (VR).

11
With increase in the reverse voltage across the diode, the depletion layer starts spreading
into the drift region. Minority carrier densities quickly attain their respective reverse bias
profile in the p+ and n+ regions.
Even at the end of t5 some trapped charges exist inside the drift region which
disappear by the process of recombination. Therefore, reverse recovery charge (Qrr) is
always less than the total amount of excess carriers stored in the drift region during Turn
on. Next figure explains the carrier density variation with time during the Turn off
process.

With reference ro Fig. 1

trr
I
diF diF
rr
= dt t 4
= dt s 1
(1)

trr
Q rr
 12 I t rr rr
=
diF
dt 2( s  1)
(2)
Qrr (1  s )
t rr
= diF / dt
(3)

I rr
=
2Qrr diF / dt
s 1
(4)

Now if the total charge stored in the drift region is Q F at a steady forward current I F
then

dQ Q
I F
= F = F OR QF = I F
dt 
(5)

Where  is the excess carrier life time in the drift region.

Now it has been argued earlier that Q rr
≤ Q F
always.

2 I F
Therefore for S 1 t rr  diF (6)
dt

diF
And I rr
 2I F
dt
(7)

12
Equations (6) and (7) indicate that both I rr
and t rr
increases with  . I rr
I I
diF
increases with F
and
dt
while t rr
increases with F
but decreases with
diF
.
dt

Power loss due to reverse recovery: With reference to Fig. 1. energy loss per reverse
recovery is given approximately by.
1 1
E rr
=
2 I rr t 4V F +
2 t 5V R
Irr

V F  SV R  Q rr
=
1
2 I rr t rr 

S 1
= V F  SV R  
 S  1
(8)
If the switching frequency is f sw
then reverse recovery power loss is

p = E rr f =Q V s
f S 1 F vr
rr sw rr sw

(9)

13
Shottky Diodes (L 2.4) Back

Construction and Operating Principle

A schottky diode is formed by placing a thin film of metal, usually Aluminum in direct

contact with a n type epitaxial layer grown on a n type substrate. The metal film acts

as the positive electrode (anode) while the n substrate acts as the cathode. Another

metal contact is placed on the n cathode side for current collection. Fig. 2 shows the
schematic structure of a schottky diode.

Fig.1: Schematic structure of a schottky diode.

The insulating sio 2

layer helps reduce the surface electric field and improves reverse
characteristics.
The metal semiconductor junction on the anode side has a rectifying property because the
electrons in the semiconductor have higher absolute potential energy compared to the
metal. So there will be a large flux of electrons flowing from the semiconductor to the
metal across this interface. Consequently the metal will become negatively charged while
the semiconductor positively charged and a depletion region similar to a p-n junction will
be formed at this interface. However, the negative space charge in the metal comes from
free electrons and not from movement of holes. This flow of electron will continue till the
electrostatic potential associated with the space charge stops further movement of
electrons.
When a forward bias voltage (i.e, anode positive with respect to cathode) across this
structure, it reduces the potential barrier and makes it easier

14
for electrons to cross over. Biasing the metal negative with respect to the semiconductor
has the opposite effect. Thus, the metal semiconductor interface exhibits a rectifying
properly.
The same rectifying properly is not observed at the cathode metal interface. The cathode
has a much larger doping density. Thus the depletion region that is formed is very narrow
and the electric field very large. Under these circumstances, the electrons move very
easily across the interface using a quantum mechanical effect called “Tunneling” under
the influence of small applied voltage. That is why the cathode-metal interface is an
ohmic contact and not a rectifying contact.
Characteristics of schottky diodes

Fig. 2: i- v characteristic of a schottky diode.

Forward bias i-v characteristics of a schottky diode is similar to that of a p-n junction
diode. However, these diodes are designed to have lower forward voltage drop, the
difference being 0.3-04V for the same forward current density.
In the reverse direction, a schottky diode has much larger reverse leakage current
compared to a p-n junction diode. The break down voltage is also considerably lower
(<200v). After break down it exhibits resistance like characteristics.
Schottky diodes have much shorter switching times. Being a majority carrier device, no
stored charge needs to be removed during Turn off. Consequently, there will be no
reverse current corresponding to removal of minority carriers. Reverse current associated
with the growth of the depletion layer charge in reverse bias will flow. But this is much
smaller compared to a p-n junction diode (< 5%). Reverse recovery time (a few hundreds
of nano seconds) and energy loss are also much smaller. During Turn on forward
recovery voltage V fr is negligible due to much larger doping density and smaller

15
width of the n type epitaxial layer. Voltage overshoot due to parasitic inductance may,
however, be observed at large diF/dt.

16
 Lesson-3

L 3.1

Transistor current components

Back to “equation 3.3 & 3.4”
Back to Large current gain “ ”

InE InC
(InE – InC)
E (n+) B (p) C (n) iC
iE
Ipcs
Ics
IpE incs
VCB
iB

VBE

Fig. 1 Transistor Current Components.

Fig-1 shows different transistor current components. InE is the electron component of
emitter current arising due to diffusion of electrons into the base region from emitter.
Similarly IPE is the hole component of the emitter current.

A portion of the electrons injected into the base recombines with majority hole carriers
there. Recombined holes are subsequently replenished by base current. This component
of the base current is represented by (I nE – Inc). IPE is another component of the base
current due to hole injection from base to the emitter region.
Ics is the reverse saturation current of the base collector junction and consists of hole
component (Ipcs) & electron component (Incs).

From Fig 1 one can write

17
 I E = I nE + I pE
I B = ( I nE - I nc ) - I pcs - I ncs + I pE
I C = I nc + I cs
I cs = I pcs + I ncs

Now I cs << I nc so I c �I nc
I �I �I I �I �I
\ B = �nE - 1�- cs + PE � �nE -1�+ PE
I C �I nC � I nc I nc �I nC � I nc
IB
In order to make the dc current gain as large as possible. I C should be very small.

Therefore
I nE
�1 OR I nE �I nc
I nc

Which requires that recombination of electrons in the base region be minimized. This is
achieved by making the base region very thin (fraction of a μm in case of signal
transistors) and increasing electron life time in the base region.

The other condition is

I PE I
� PE �0
I nc I nE
This is achieved by increasing the doping level of the emitter with respect to the base.

L 3.2
The collector drift region and quasi saturation in a power
transistor
Back to “drift
region”
Back to “quasi saturation region”

As in the case of a power diode a lightly doped collector drift region (link to Section
2.3.1 of Module 2) is introduced in a power transistor in order to support the large base
collector reverse voltage. This drift region has significant effect on the output i-v
characteristics of a power transistor as explained next.

18
 iB

RB vCC
RL iB
VBB
Minority carrier density.

n+ p n- n+
(E) (B) (DRIFT) (c)

Increases with time

Increases Increases
with time Increases with time
with time

In the active region the minority carrier density profile in the base extends up to the space
charge layer at the base – drift region interface. As the collector current increases the
reverse voltage across this junction reduces due to increased drop in the load resistance.
Therefore, the depletion layer width reduces and the minority carrier density profile in the
base region approaches the junction and reaches it at the beginning of the quasi saturation
region. In the quasi saturation region the base drift region junction becomes forward
biased and hole injection from the base occurs in the collector drift region. At the same
time excess electrons injected in to the base from the emitter side also enters the drift
region in order to maintain space charge neutrality.

Thus, in the drift region of a Power transistor carrier injection and conductivity modulator
occurs just as in a power diode. The resistivity of the drift region and hence the collector
emitter voltage drop depends on the amount of carrier injection into the drift region
which in turn depends on the base current. Therefore, base current retains some control
over the collector current in the quasi saturation region although the value of  reduces
considerably due to effective increase of the base width.

Hard saturation is obtained when the excess carrier density profile in the drift region
reaches heavily doped collector region interface. The drift region is now completely
shorted out by the excess carriers. Any further increase in the base current causes further

19
 increase in the excess carrier density in the drift region and hole injection in the collector
region. However, the excess carrier does not change the resistivity of the drift region
significantly and hence VCE does not change very much. The base current looses control
over the collector current which is now determined entirely by the external biasing
voltage (Vcc), load resistance (RL) and the resistance of the conductivity modulated drift
region.

L 3.3

Current Crowding and Second Break Down in a Power

Transistor

Emitter current crowding occurs in a Power BJT due to its constructional features as
explained below.

Back to “current crowding”

Back to “second break down”
Back to “the second break down”
B E B B E B
     

n+ n+

p p

n n

Current
Current Crowding
Crowding  C(a) (b)
 C

Figure 1: Emitter current crowding in a Power BJJ;

During forward bias condition,
During reverse bias condition.

20
Due to the device geometry, during forward bias condition, there will be a lateral ohmic
voltage drop in the base region. Therefore, the base emitter junction voltage near the
periphery of the emitter region will be higher compared to the central region. The base
current density near the emitter periphery will be higher as a consequence (thicker blue
arrows in Fig.1(a)). This will lead to “crowding” of emitter current near its periphery
(Thick red arrows in Fig.1(a)). Following the same logic current crowding will occur at
the central emitter region during reverse base bias condition (turn off) as shown in
Fig.1(b).

One consequence of emitter current crowding is lowering of effective DC current gain

due to high level carrier injection in some portions of the emitter. This reduction in dc
current gain occurs at a lower current level than if the current density were uniformly
spread over the entire emitter area.

However, a more serious consequence of current crowding is the increased likelyhood of

second break down failure. It has been mentioned in section 3.4 that “second break
down” failure of Power BJT occurs due to formation of “current filaments” and localized
thermal runaway. Non- uniform current density across the device will increase the
probability of such thermal run away due to negative temperature coefficient of resistivity
in a BJT. Non-uniformity of current density can be caused by emitter current crowding.
To reduce the severity of current crowding the width of the emitter regions in a power
BJT are made small while a large number of such narrow “finger like” emitters are spread
over the entire cross section of the device and connected in parallel.

Back
L 3.4

Collector Base Junction break down voltage (VCBO)

When a BJT is in the blocking state the CB junction must withstand the applied voltage.
The maximum voltage a BJT can withstand differs considerably depending on whether it
is in open base (iB = o) on open emitter condition (iB < o). These two blocking voltages
are dented by VCEO and VCBO respectively with VCEO < VCBO.

It should be noted that even with iB = 0 the base- emitter junction is forward biased due to
the reverse bias current of the C-B junction. As a result, there is carrier injection into the
base from the emitter side. This excess carrier in effect increases the reverse saturation
current of the CB junction in the open base configuration compared to the open emitter
configuration. Therefore, for a given voltage, more number of carriers cross the CB
junction depletion region in the open base configuration. Consequently, the rate of impact
ionization increases and the break down voltage reduces.

There is a semi-empirical relationship between the parameters VCEO and VCBO given by

21
 VCBO
VCEO = 1
β n

n = 4 for n p n transistors.

22
L 3.5

Switching characteristics of BTJ with L-C-R-D Snubber Back

The switching characteristics of a BJT with snubber circuit as shown in Fig 1 (a) is
shown in Fig 1 (b)

VCC

iD D IL

iLS
LS RS iRS

Q +
DS iDS
RB iB iC iCS
VCE
CS vc

VBB +
-

(a)

23
VBB 

vBB  t

-VBB

iB
 t

ics
iRS
iDS
 t

iD 
iC IL

iLS
 t

vCE

vCC vCM
vC

t

ts tfi
td tfv
(b)

24
 log iC
RBSOA
IL

Turn off FBSOA

Turn on

(c) VCEO VCBO log vCE

VCC vc max

Fig.-1: Switching characteristics of a BJT with L-R-C-D snubber

Snubber circuit, (b) Switching waveforms,
(c) Switching Trajectory

The main difference here is that iC can not rise before VCE starts falling due to the turn on
snubber inductance Ls

Here VCE starts falling first with a fall time of t fv after the usual delay time td. VCE is given
by

� t �
VCE = VCC � 1- � assuming VCE �0
� t fv �
sat

Collector current iC can be written

iC = ils - ics
Diode Ds is in off condition

t V - VCE VCC t τ 1 VCC

i ls = �CC dτ = �t dτ = t2
o Ls Ls o
fv 2 Lst fv

VCE - VC dVC VCE - VC

Also i cs = or Cs =
Rs dt Rs

dVC
or R sCs + VC = VCE = VCC �
1- t �
� , VC ( o ) = VCC
�
dt � t fv �

From which VC can be solved.

If tfv is negligible compared to Rs Cs time constant then

25
 VCC
VC ( t fv ) �VCC & i cs ( t fv ) �
Rs
1 V t fv
Also i ls ( t fv ) = 2 CC
Ls
VCC � 1 t fv �
\ i C ( t fv ) = i cs ( t fv ) + i ls ( t fv ) =
1+
Rs � � 2 ( Ls R s ) �
�
For safe operation of the BJT it will be necessary that

VCC � 1 t fv � Ls
i C ( t fv ) < I CM or 1+ < I where τ =
Rτs �
� 2 LR � �
CM
R LR
s

After tfv VCE = 0, ils increases linearly with a slope VCC/Ls and is given by

1 VCC t fv V
ils ( t ) = + CC (t- t fv )
2 Ls Ls

=
VCC �
Ls ��
t
( t - t fv ) + zfv �
�
V
= CC . t - 1 t fv
� Ls 2 ( )
V -( t-t fv ) R sCs
i cs � CC e
Rs

-( t-t fv )
VCC �t 1 t fv �
\ i c = i ls + i cs � � - + e τ RC �τ RC = R sCs
Rτs LR2 τ LR
� �

LI
Turn on process ends when i ls = I L at t = Vs L + 1 2 t fv
CC

� L I
� �
-� s L - 1 t fv �
VCC 2 �
VCC �L sI L � �
τ Rc �
At that tine i C = i CF = +e
Rs �VτCC LR �
� �
� t fv L s Cs IL �
1 �
Or i CF = I L + VCC e � 2 τ Rc R s ( VCC R s ) �
� - 2 �

Rs
For safe operation of the BJT it will be necessary that

iCF < ICM

Turn off process starts with the base drive voltage going negative. Now V CE can not rise
without charging Cs. Therefore ic starts falling with a fall live tfi and is given by
i c = I L ( 1- t t fi ) , But ils = IL

26
 \ i cs = I L - i c = I L t
t fi
1 t IL t 1 I Lt 2
\ vc =
Cs �i dτ =
o cs C s t fi �
o
τ dτ =
2 C s t fi
1 I Lt fi
at t = t fi , v c = & i c = o, i Ls = I L
2 Cs

After words vc charges with constant current ic = iLs = IL and is given by

vc =
1 t fi I L
I
2 L Cs Cs
I
+ ( t - t fi ) = L t - 1 t fi
Cs 2 ( )
VCC Cs 1
vc reaches VCC at t = IL
+ t
2 fi
� 1 t fi �
= ( VCC I L ) C s �
1+
� 2 ( VCC I L ) Cs �
�
After this time ils starts falling through resonance between Ls & Cs

diL s
\ VCC = L s + vc
dt
di
or VCC i Ls = L s i ls ls + ( v c - VCC ) i ls + VCC i ls
dt
di d
or L s i ls ls + ( v c - VCC ) c ( v c - VCC ) = 0
dt dt
\ L s i ls di ls + c ( v c - VCC ) d ( v c - VCC ) = 0
VCMax -VCC IL
\C �
o
( v c - VCC ) d ( v c - VCC ) = L s� i di ls
o ls

\1 L sI L 2 = 1 C ( VCMax - VCC )
2
2 2
Ls
or VCMax = VCC + I
Cs L
For safe operation of the transistor it is necessary that

VCMax < VCBO

Vc then discharges through Rs & D towards VCC

27
 Lesson-4

L 4.1
Thyristor Protection Back

In a converter circuit a thyristor circuit needs to be protected against (i) large di dt , (ii)

large dv dt , (iii) over voltage and (iv) over current. In addition the thyristor gate circuit
also needs to be protected against over voltage over current and spurious noise signals.

di
dt protection: As discussed in connection with turn on switching of a thyristor, the
anode current, just after turn on is restricted to a small area of the cathode which
�di �
increases with time at a finite rate. Now if the rate of rise of anode current � A dt �is
� �
larger than that rate the current density in a portion of the cathode cross section will keep
on increasing leading to the formation of local hot spots. The device may be destroyed in
the process. The manufacturers usually specify a limiting value of di A (20-500 A/μs)
dt
which should not be exceed to avoid this type of failure. In a thyristor converter circuit
the rate of rise of anode current is restricted by connecting on inductor of appropriate
value in series with the thyristor. This is called the di dt limiting inductor.

dv
dt protection: When a forward voltage is suddenly applied across reverse biased
thyristor there will be considerable redistribution of minority carriers across all three
junctions. The process is akin to charging the junction capacitances with the opposite
( )
polarity. If the rate of change of the applied dv dt is large this “capacitor charging
�c dv �
current � j dt �” across the junctions may become sufficient to satisfy the latching
� �
condition of the thyristor (i.e, 1 + 2 = 1) and the thyristor may turn on even in the
absence of a gate pulse. To protect against such spurious turn on of the thyristor a
properly designed RC snubber circuit (as discussed in connection with diode circuit)
should be used across the thyristor. The snubber components should be designed such
( )
that they along with the di dt limiting inductor and the load forms a slightly under
damped circuit.

Over voltage protection: Over voltage across a thyristor may occur due to several
reasons such as due to snappy reverse recovery, due to commutation in other thyristors in
the same circuit, network switching, lightning surges etc. Of these, the first two types can

28
 be handled by a properly designed snubber circuit across the thyristor. However, for the
last two types, over voltage protection of a thyristor must be upgraded by using a voltage
clamp device across the thyristor.

A voltage clamp device is a non linear resistance which acts as an open circuit under
normal condition (i.e. below clamping voltage) and as a short circuit when voltage across
it crosses the clamping level. The surge energy is dissipated in the non linear resister.
Metal oxide Varistors are commonly used as voltage clamp devices.

Over current protection: Over current in a thyristor circuit occurs due to a fault or short
circuit. Thyristor can with stand fault currents far in excess of its rated average or RMS
forward current for short durations (several cycles of the supply frequency). Therefore, if
the fault impedance is high or the supply ac network has a relatively low short circuit
level, the thyristor may be protected using a normal circuit breaker. However, for a short
circuit fault when the ac network supplying the thyristor circuit is stiff the fault current
may rise to dangerous level and destroy the device. To protect a thyristor against such
faults Fast Acting Current Limiting Fuse (F.A.C.L fuse) is connected in series with a
thyristor. For proper protection co-ordination of the fuse and the thyristor is important.
The i2t rating of the fuse must be less than that of the thyristor and the “peak let through
current” should be less than the sub cycle surge current rating of the thyristor. The fuse
voltage rating should also be less than the surge voltage rating of the thyristor.

Gate protection: The gate circuit should be protected against over voltage and over
current. A series resistance and a zener diode across the gate cathode terminals are
provided for this purpose. To prevent conducted or radiated EMI to affect the gate circuit
the gate supply cables are twisted and shielded. In addition, a small capacitor (a few
hunded nF) in parallel with another resistance is connected just across the gate and
cathode terminals to protect the gate against spurious noise voltages. In very large power
application Light activated Thyristors using optical fiber signal transmission is used for
maximum protection against spurious turn on. Fig 1. shows typical protection
arrangement for a high power thyristor.

Voltage clamp
device (MOV)

R.C snubber

From Circuit F.A.C.L di/dt limiting To

Supply Breaker Fuse inductor LOAD

Gate pulse

Fig. 1: Thyristor protection circuit.

29
30
L 4.2
Series and Parallel Connection of thyristors Back

In some industrial applications the voltage and current levels are in excess of a single
available thyristor. In such cases series / parallel connection of multiple thyristors are
employed. For series or parallel connected thyristors it should be ensured that each
thyristor rating is utilized fully and the system performance is satisfactory. String
efficiency is a term used to measure the degree of utilization of thyristors in series /
parallel connection and is defined as

Actual Voltage / current rating of the whole string

String efficiency =
Individual voltage / current rating of each thyristor × no. of
thyristors in the string

For obtaining the highest possible string efficiency the thyristors connected in series /
parallel must have identical i-v characteristics. Even then, unequal voltage / current
sharing does occur which makes string efficiency lees than unity. However, unequal
voltage / current sharing by the thyristors in a string can be minimized to a great extent
by using external equalizing circuits. These are discussed next.

Series connection of thyristors

iA
IA
Th1

Th1 VA1
Th2

VA2
Th2

IA

(a) VA2 VA1 VAK

(b)

Fig. 1: Characteristics of series connected thyristors.

Fig 1 (b) shows the static i-v characteristics of two series connected thyristors of Fig 1
(a). It is seen that slight difference in the forward blocking characteristics of the two

31
 thyristors results in considerable difference in the forward voltage blocked by each
thyristor. Similar difference will be found for reverse blocking voltage.

The problem of unequal voltage sharing will be more prominent during dynamic
conditions. It is likely that SCRs will not have identical dynamic characteristics. In such
cases, series connected SCRs will have unequal voltage distribution during the transient
conditions of turn ON and turn OFF.

VAK
ia

VAK1 VAK2
VS

t t
Th1
VAK VAK Th2
VAK2
VS
VS/2 VAK1
VAK2
t t

(b)
(a) VAK1

Fig. 2: Turn ON and Turn OFF characteristics of series connected thyristors.

Fig 2: Turn ON and Turn OFF characteristics of series connected Thyristors.

(a) Turn ON characteristics; (b) Turn OFF characteristics.

The Top figures of Fig 2 (a) & (b) shows the individual Turn ON and Turn Off
characteristics of series connected thyristors TH1 and TH2 of Fig 1(a). It is assumed that
TH2 has a larger turn on delay time and larger turn off time. As a result when the series
combination of TH1 and TH2 are gated together TH1 turns on faster while the voltage
across TH2 rises to the full supply voltage Vs.

During Turn off as the forward current through the series combination goes negative TH 1
recovers earlier blocking the path for reverse recovery of Th 2. Consequently the reverse
voltage is supported by TH1 alone while the voltage across TH2 remains almost zero.

32
A simple resistor as shown in Fig 1(b) will not ensure equal voltage distribution across
devices during dynamic condition. The reverse biased junctions of thyristor are likely to
have different capacitances and when connected in series, are likely to share dynamic
voltage unequally during Turn on and Turn off.

This problem can be avoided by connecting shunt capacitors across thyristors as shown in
Fig 3. These shunt capacitors being much larger than the reverse biased junction
capacitors of the thyristors tends to equalize the effective capacitance of the circuit. A
series resistance RC is also used along with the shunt capacitance in order to limit the
capacitor discharge current during “Turn on” of the thyristor. A diode D by passes RC
when forward voltage appears across the series combination. This makes the capacitor
dv
more effective for voltage equalization and for limiting across the thyristor.
dt
A

RC D
R
Dynamic C TH1
voltage
equalizer Static voltage equalizer

RC D
R
C TH2

Fig. 3: Static and dynamic voltage equalizer for series connected thyristor.

Parallel connection of Thyristors

A number of thyristors are connected in parallel to supply load currents in excess of the
individual ratings of the thyristors. For equal sharing of current the i-v characteristics of
parallel connected thyristors should be as for as possible identical. Otherwise difference
in current sharing will occurs as shown in Fig 4.

33
 ia A
TH1
Ia TH2
I1 I2 I1 TH1 TH2

VAK
I1 I2
I2
TH1 TH2

IA VAK VAK
K
(a) (b)
(c)
Fig.4: Current sharing of parallel connected thyristors.

In this case TH1 has a lower voltage drop and hence it shares larger current. Difference in
current sharing may occur due to difference in the dynamic characteristics of the
thyristors. For example, if one of the thyristors have a larger turn on delay time compared
to other thyristors with which it is paralled it will not turn on at the same instant as the
other thyristors turn ON. However, voltage across it will collapse due to turning ON of
other thyristors. For a given gate current a minimum anode cathode voltage is required
for a thristor to turn ON which may not be available in this case. Thus the thyristor with
larger turn ON delay time will never turn ON.

Unequal current sharing also causes unequal heating of thyristor junctions. The ON state
voltage drop across a conducting thyristor is a strong function of the junction temperature
and decreases with increasing junction temperature. Thus the thyristor carrying the
largest current tend to share even more current as its junction temperature rises. This may
lead to “thermal run away” and destroy all parallels connected thyristors.

In an ac circuit unequal current sharing between parallel connected thyristors can be

avoided by using a reactor as shown in Fig 4 (c). The reactor offers little impedance to
the common mode current (I1 + I2) but a large impedance to any circulating current (I 1 –
I2). Unequal current sharing is thus minimized.

34