Digital Electronics 2-2 Logic Gates Logic Gates Logic gates are the basic elements that make up a digital system. The electronic gate is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function. The types of gates available are the NOT, AND, OR, NAND, NOR, exclusive-OR, and the exclusive-NOR. _NOT gate (inverter): Switch Equivalent Truth Table Logic Diagram (Symbol) —_>— y Pin Diagram veda + © Tnput Output Switch open (Low) Lamp ON (High) Switch close (High) | Lamp OFF (Low) | Boolean Expression | Application : yok ~ | Used to complement (invert) —__|digital signal, = AND gate: The output is high only when all inputs are high. = Logic Diagram (Symbol) Switch Equivalent | Truth Table ro” o_o” o> & a Sy Sp Output | y il 7 | ———_+ 0 Tnput Output Ss Sp 0 ‘Open (Low) | Open (Low) | Lamp OFF (Low) 7 ‘Open (Low) | Close (High)| Lamp OFF (Low) ‘Close (High) Open (Low) | Lamp OFF (Low) Close (High) | Close (High) | Lamp ON (High) | Bool: E i Application : Used to polean Expression implement logical AND operation. Y=A-B TECHNICAL PUBLICATIONS”. An up thrust for knowledgeDigital Electronics 2-3 Logic Gates peer OR gate : The output is high when any of the inputs is high. Logic Diagram (Symbol) Switch Equivalent Truth Table s. a A 1 jo Y 0 Output | B Pin Diagram y | 0 1 | Tnput Output 1] | Si, Sy ] Open (Low) | Open (Low) | Lamp OFF (Low) Asia) Open (Low) | Close (High)} Lamp ON (High) | Close (High)| Open (Low) | Lamp ON (High) Close (High)| Close (High)| Lamp ON (High) - | Boolean Expression Application : Used to implement, logical OR operation. Y=A+B | ees ___ Buffer : The output is same as input. —__ pas Symbol Boolean Expression | Truth Table Y=A Pin Diagram Application : It is used | Ae 12 fo] [se to increase output driving capacity. a Ic We opt OutputDigital Electronics Logic Gates symbol It can be any} Application : used to implement digital circuit. __NAND gate :_ The output is high only when one of the inputs is low. Boolean Expression Truth Table “B Pin Diagram | fel fel Fl fol [] fe Voc To 7400 THE put i is s high when all all the inputs are Boolean Expression Truth Table +B | : It can be| any, Application used to implement digital circuit. Exclusive OR (EX-OR) Ps + Sp. | Application : It is used to implement — magnitude, comparator, gray code converter, aiken /eaibteaetoe, circuits, parity __ generator, modulo-2 adder, etc. | TECHNICAL PUBLICATIONS”. An up thrust for knowledge Hee 16-7402 “The cule is high only when ane inputs high. Boolean Expression Table Y=A@B Pin Diagram AA Al VeeExclusive NOR (EX-NOR) gate : The output is high only when even number of ones at the input or all inputs are high. Symbol Boolean Expression Y=A@B Pin Diagram rm] fel fel fe] fo] fe] fe sagt ‘ | Veo Applications : It is used) to implement even parity generator, comparator, event (iL) arity checker, etc. parity — ny Ie7 Note : EX-OR and EX-NOR gates are also known as mutually exclusive gates. See) 1. Write the logic symbol, expression and tr 1.) EX-OR (ii) NOR 2.) NAND (ii) EX-NOR 3.(i) NAND (ii) NOR (iti) EX-OR able for the following logic gates | Ei Implementations of Logic Functions ‘using Gates The Boolean algebra is used to express the output of any combinational network. Such a network can be implemented using logic gates. Let us see the implementation of SOP and POS Boolean expressions. TECHNICAL PUBLICATIONS”. An up thrust for knowiedge eeeDigital Electronics 2-6 Logic Gates Implementation of SOP Boolean Expression Consider the Boolean expression F = AB+CD+BC In this expression, we have three product terms with 2 literals in each product term. Thus, we can implement these =F product terms by using three pb Dee" 2input AND gates, as shown in 5 _ the Fig. 2.21. Expression tells Pry se c that these product terms should be ORed to get the output F. We Fig. 2.2.1 Implementation of SOP Boolean expression have three product terms so we have to use 3-input OR gate to obtain the sum of products. It is important to note that literals are complemented using NOT gates. 00 o> Implementation of POS Boolean Expression Consider the Boolean expression F = (A+B) (B+C) (C+D+E) In this expression, we have three sum terms with 2 literals ; A+B. in two terms and 3 literals in one term. We can implement Bee B me on these sum terms by using two ¢ F=(A+B)(B+C)(C+D+E) 2input OR gates and one 3-input OR gate, as shown in aa the Fig. 2.2.2. Expression tells — C+D+E that these product terms should be ANDed to get the Fi9- 2.2.2 Implementation of POS Boolean expression output F. We have three sum terms so we have to use 3-input AND gate to obtain the product of sums. It is important to note that literals are complemented using NOT gates. In the previous examples we have seen that simplified SOP Boolean expression can. be implemented using AND-OR gates. The AND-OR implementation is a two level implementation. In the first level we implement all product terms using AND gates and in the second level all product terms are logically ORed using OR gate. In case of POS expression we use OR-AND implementation. Here, we implement all sum terms using TECHNICAL PUBLICATIONS”- An up thrust for knowledgeEO S—“‘Ci:OC;CO;”Ww™;”™;™;~ Digital Electronics 2-7 Logic Gates OR gates in the first level and all sum terms are logically ANDed using AND gate, to get product of sum, in the second level. We know that, the logic gates are available in the integrated circuit (IC) packages. When we implement logic circuit using basic gates, we require ICs for AND, OR and NOT gates. Many times it may happen that all gates from A the IC packages are not required to build the circuit and thus remaining gates are unused. , po Consider a combinational circuit which requires two 2-input AND gates and one 2-input OR gate Ta as shown in Fig. 2.2.3. To implement such a circuit rig 224 we require IC 7408 (Four 2-input AND gates) and a TC 7432 (Four 2-input OR gate). When we use these two ICs we find that two 2-input AND gates are unused and three 2-input OR gates are unused, Thus, the utility factor is very poor. This uiility factor can be increased by using universal gates ‘0 implement logic functions. ee Cums torical Implement the expression. - 1) AB + BCD + EFGH : Bae B(CeD DE + Gr H+) wih lecmne Solution : 1) A s_D7 B s=[)--D~ D Ee = G H Fig. 2.2.4 2) ‘ I ° : 7 e E G é Fig. 2.2.5 TECHNICAL PUBLICATIONS”. An up thrust for knowiedge= A-BB=0 CQEEERED Dio ve ogi ingra for X = AB + BIC. al Solution: X = AB+ BC A B ‘Do Fig. 2.2.7 ¢ ’ ES Solution: X = (AB+C) D+E = (AB-C) D+E = ABCD+E Fig. 2.2.8 EW Universal Gates ‘The NAND and NOR gates are known as universal gates, since any logic functions can be implemented using NAND or NOR gates. NAND Gate The NAND gate can be used to generate the NOT function, the AND function, OR function, and the NOR function. TECHNICAL PUBLICATIONS”. An up thrust for knowledgeDigital Electronics 2-9 Logic Gates NOT Function : An inverter can be made from a NAND gate by connecting all of the inputs together and creating, in effect, a single common input, as shown in Fig. 2.3.1, for a two-input gate. Fig. 2.3.1 NOT function using NAND gate AND Function : An AND function can be generated using only NAND gates. It is generated by simply inverting output of NAND gate; ie. AB = AB. Fig. 2.3.2 shows the two input AND gate using NAND gates. d ltt Table 2.3.1 Truth table OR Function : OR function is generated using only NAND gates as follows : We know that Boolean expression for OR gate is Y= A+B = A+B (A= Al = AB DeMorgan’s Theorem 1 TECHNICAL PUBLICATIONS”. An up thrust for knowledgeDigital Electronics 2-10 Logic Gates The above equation is implemented using only NAND gates as shown in the Fig. 23.3. Fig. 2.3.3 OR function using only NAND gates Note : Bubble at the input of NAND gate indicates inverted input. als Table 2.3.2 Truth table NOR Function : NOR function is generated using only NAND gates as follows : We know that Boolean expression for NOR gate is Y = Ay ol A A. DeMorgan’s Theorem 2 ol AB [A= A] The above equation is implemented using only NAND gates, as shown in the Fig. 2.3.4. Fig. 2.3.4 NOR function using only NAND gates TECHNICAL PUBLICATIONS”. An up thrust for knowledgeDigital Electronics Logic Gates Similar to NAND gate, the NOR gate is also a universal gate, since it can be used to ate the NOT, AND, OR and NAND functions. Function : ‘An inverter can be made from a NOR gate by connecting all of the inputs together creating, in effect, a single common input, as shown in Fig. 2.3.5. Fig. 2.3.5 NOT function using NOR gate Function : ‘An OR function can be generated using only NOR gates. It can be generated by emply inverting output of NOR gate; ie. A+B = A + B. Fig. 2.3.6 shows the two input gate using NOR gates. A+B Fig. 2.3.6 OR function using NOR gates TECHNICAL PUBLICATIONS” An up thrust for knowledge =. ee LLC“Digital Electronics Table 2.3.3 Truth table AND Function : 'AND function is generated using only NOR gates as follows : We know that Bool expression for AND gate is y = AB =A [A= = A+B De-Morgan’s Theorem ‘The above equation is implemented using only NOR gates as shown in the Fig, 237. A A — =8B a= a z A B B Fig. 2.3.7 AND function using NOR gates Note : Bubble at the input of NOR gate indicates inverted input. Table 2.3.4 Truth table TECHNICAL PUBLICATIONS™- An up thrust for knowledgeal Electronics 2-13 Logic Gates NAND function is generated using only NOR gates as follows : We know that oolean expression for NAND gate is Y=AB +B DeMorgan’s Theorem 1 = A+B . [A= A] The above equation is implemented using only NOR gates, as shown in the Fig. 2.3.8. >>| mC O Tit 1. What are universal gates ? Give examples. 2. Why NAND and NOR gates are called universal gates ? 3. Why digital circuits are more frequently constructed with NAND or NOR gates than with AND and OR gates ? 4, Realize (i) AND gate (ti) NOR gate using only NAND gates. 5. Realize (i) OR gate (ii) EX-OR gate using NAND gates. 6. Realize (i) OR gate (ii) AND gate using only NOR gates. NAND-NAND Implementation The implementation of a Boolean function with NAND-NAND logic requires that the tion be simplified in the sum of product form. The relationship between AND-OR and NAND-NAND logic is explained using following example. TECHNICAL PUBLICATIONS” An up thrust for knowledgeDigital Electronics 2-14 Logic G Consider the Boolean function: Y= ABC+DE+F. This Boolean function can be implemented using AND-OR logic, as shown in Fig. 2.4.1 (a), Sis (a) AND - OR (b) NAND - bubbled OR (c) NAND-NAND Fig. 2.4.1 NAND-NAND implementation 7 mo om> | mo ow> mo om> Fig. 2.4.1 (b) shows the AND gates are replaced by NAND gates and the OR gate is replaced by a bubbled OR gate. The implementation shown in Fig. 2.4.1 (b) is equivalent to implementation shown in Fig. 2.4.1 (a), because two bubbled on the same line represent double inversion (complementation) which is equivalent to having no bubble on the line. In case of single variable, F, the complemented variable is again complemented by bubble to produce the normal value of F. In Fig, 2.4.1 (0), the output NAND gate is redrawn with the conventional symbol. The NAND gate with same inputs gives complemented result, therefore F is replaced by NAND gate with F input to its both inputs. Thus all the three implementations of Boolean function are equivalent. From the above example we can summarize the rules for obtaining the NAND-NAND logic diagram from a Boolean function as follows : 1. Simplify the given Boolean function and express it in sum of product form: (SOP form). . Draw a NAND gate for each product term of the function that has two or more literals. The inputs to each NAND gate are the literals of the term. This constitutes a group of first level gates. v » If Boolean function includes any single literal or literals draw NAND gate for each, single literal and connect corresponding literal as an input to the NAND gate. 4, Draw a single NAND gate in the second level, with inputs coming from outputs of first level gates. TECHNICAL PUBLICATIONS”- An up thrust for knowiedge| Digital Electronics 2-15 Logic Gates it isu Implement the following Boolean a with NAND-NAND logic ‘Y: -ABC+ ABC+AB: eae : Solution : Step Simplify the given Boolean function. Y = AC+ABC+ABC+AB+D = AC+BC(A+A)+AB+D =AC+BC+AB+D Step 2: Implement using AND-OR logic. Step 3 : Convert AND-OR logic to ID NAND-NAND logic. cl A c ety 8 ° Ly cL B ° a Fig. 2.4.2 (b) PEAEELED Implement the following Boolean function with NAND-NAND logic F=AB+AC+BC ‘ Solution : Step 1: Implement Boolean function Step 2: Convert AND-OR logic to with AND-OR logic. NAND-NAND logic. R 77 De ‘D- ane Fig. 2.4.3 (a) Fig. 2.4.3 (b) >I O>I D>! ol Note : It is possible to directly go to step 2 skipping step 1. Here, step 1 is included for clear understanding. TECHNICAL PUBLICATIONS”. An up thrust for knowledgeeS Digital Electronics 2-16 Logic Gates | Solution: Step 1: Simplify the given Boolean function. Fig. 2.4.4 F = AB+AC+BC Step 2 : Implement Boolean function Step 3 : Convert AND-OR logic with AND-OR logic. to NAND-NAND logic. “DD DD iD Fig. 2.4.5 (a) Fig. 2.4.5 (b) 0 Oo! OF! a>! m7 ol o>! Note : It is possible to directly go to step 3 skipping step 2. Here, step 2 is included for clear understanding. Solution : The Boolean expression for EX-OR gate is : Y = AB+AB =D- _) >” ~ =D Fig. 2.4.6 (a) We can implement AND-OR logic by using NAND-NAND logic as shown in Fig, 2.4.6 (b). | © >I TECHNICAL PUBLICATIONS”. An up thrust for knowledgeSolution : We have, A = = A a B _>— Y= 8 Lt Y EX.NOR EX-OR Inverter Fig. 2.4.7 Thus using result in previous example we have EX-NOR gate using only NAND gates as shown in the Fig. 247 (a), A Ree Fig. 2.4.8 TECHNICAL PUBLICATIONS” An up thrust for knowledgeDigital Electronics 2-18 Prime implicants : ee AB, AD, AG, BD e ee ee a ge B D> Essential prime implicants : c i: . AD, AC, BD D De B Non-essential prime implicant : AB Logic circuit : Using AND-OR-INVERT gates Logic circuit : Using NAND gate We can implement AND-OR logic Y by using NAND-NAND logic Fig. 2.4.9 Fig. 2.4.10 ae Solution : Step 1: Convert POS function into its equivalent SOP function. TIM (0, 1,2, 3, 12, 13, 14, 15) = YY m (4, 5,6,7,8,9, 10, 11) Step 2 : K-map simplification : Fig. 2.4.11 (a) f£(A,B,C,D) = AB+AB TECHNICAL PUBLICATIONS” An up thrust for knowledgeDigital Electronics 2-19 Logic Gates Step 3 : Implementation : Using basic gates Using NAND gates :>D- Dp SDT ap Fig. 2.4.11 (b) GERELEZED Drew a NAND logic diagram that implements the complement of the {following function. : : F (A,B,C, D) = ¥, 0, 1, 2,3, 4, 8, 9, 12) Solution : K-map simplification Logic diagram 2000 Fig. 2.4.12 ea Find a minimal sum-of-products representation for f (A, B, C, D, E) = m (1, 4, 6, 10, 20, 22, 24, 26) + d(0, 11, 16, 27) using Karnaugh map method. Draw the "circuit of the minimal expression using only NAND gates. Solution : The given function has 5 variables. Thus solving it by five variable K-map we get, TECHNICAL PUBLICATIONS” An up thrust for knowledgeDigital Electronics 2-20 ll Fig. 2.4.13 (a) f(A, B,C, D, E) = ABCD+BCE+BC D+ABCE gum of product equation can be implemented using NAND-NAND logic as shown in Fig. 24.13 (b). ’ mow! O1O1DI> nial @> COlw ~ Solution: Y = AB+AC+BD ie The SOP expression can be é D (D directly __implemented by NAND-NAND logic as shown in a the Fig. 24.14 Fig. 2.4.14 TEGHNICAL PUBLICATIONS”= An up thrust for knowledgeDigital Electronics 2-24 Logic Gates eee mae Clas 44. Implement the following function with NAND gates. F(x, ¥»2) y 0) Ans.: | | | DH DD | Fig. 24.15 | Example 2.4.12 Design a logic circuit to simulate the function f(A,B,C)=A(B+O) by using only NAND gates. | Ans.: | Fig. 2.4.16 | NOR-NOR Implementation Cee The NOR function is a dual of the NAND function, For this reason, the implementation procedures and rules for NOR-NOR logic ate the duals of the corresponding procedures and rules developed for NAND-NAND logic. The implementation of a Boolean function with NOR-NOR logic requires that the fanction be simplified in the product of sum form. In product of sum form, we implement all sum terms using OR gates. This constitutes the first level. In the second level all sum terms are logically ANDed using AND gate. The relationship between OR-AND logic and NOR-NOR is explained using following example. Consider the Boolean function : Y = (A +B +) (D + FE) F This Boolean function can be implemented using OR-AND logic, as shown in the Fig. 2.5.1 (a). Fig. 2.5.1 (b) shows the OR gates are replaced by NOR gates and the AND gate is replaced by a bubbled AND gate. The implementation shown in Fig. 2.5.1 (b) is equivalent to implementation shown in Fig. 2.5.1 (a), because wo bubbled on the same TECHNICAL PUBLICATIONS™- An up thrust for knowledgeSolution : F(A, B, C, D, E) = (A+B+C+D+E) (A+B+C+D+E) (A+B+C+D+E) (A+B+C+D+E) (A+B+C+D) (A+B+C+E) (A+B+C+D+E) OR-AND implementation can be replaced by NOR-NOR implementation. Logic diagram using NOR gates A B C Dd E igh ih ; 1h + a * U -* T TT Note : Inverter can be represented by NOR gate +D--= {> Fig. 2.5.7 A yyyyyyy Y TECHNICAL PUBLICATIONS”. An up thrust for knowledgeDigital Electronics 2-25 Logic Gates =e Implement the following function using a quad 2-input NOR gates ‘= (AB + ©) D. : a Solution: f = (AB+C)D roe &e+QD = (AB+Q+D +C)+D (A+B)+C+D oO > o Fig. 2.5.8 Implement F = (AB' + A’B) (C + D') with only NOR gates. Solution: F = (AB + AB) (C+ D) = ABC+ABD+ABC+ABD ABC + ABD+ABC+ABD = ABC-ABD-ABC-ABD = (B4B+O) (A +BHd) (A+B +C)-(A+B4D) This product of sum (POS) expression can be implemented by NOR-NOR logic as shown in the Fig. 2.5.9. A B Cc V => re => in pbb” ww - Fig. 2.5.9 Implementation using only NOR gates pt at TECHNICAL PUBLICATIONS” An up thrust forkniowledgeA Digital Electronics 2-26 ea ecseensaiae CEE vloment EX-NOR gate solution : The Boolean expression for EXNOR = & gate is : B “D7 A oa using only NOR gates. We can implement OR-AND logic by using Fig. 2.5.10 (a) Fig. 2.5.10 (b). NOR-NOR logic, as shown in oo Fig. 2.5.10 (b) ne following SOP function using NOR gates- - (EEE Sit and implement # f(A, B,C, D) = PrOL4s 5, 10, 11, 14, 15) Solution : o its equivalent POS function. Step 1: Convert SOP function ints IM (2,3, 6,7, & 9, 12, 13) ” Yme@ 1, 4,5, 10, 11, 14, 15) = Step 2: K-map simplification + AC Fig. 2.5.11 (a) £ (A,B,C, D) = (A+ 0) (A+ ©) TEGHNIGAL PUBLICATIONS™- An up tras for knowledge ——Digital Electronics 2-27 Logic Gates Step 3 : Implementation : Using basic gates Using NOR gates A c =(A+C)(A+C) =(A+T) (A+) Fig. 2.5.11 (b) Note : We can convert OR-AND logic into NOR-NOR logic. Step 1: Implement Boolean function with OR-AND logic. 7 x so Dp -D-* <— 4D Fig. 2.5.12 (a) Fig. 2.5.12 (b) Step 2 : Convert OR-AND logic to NOR-NOR logic. Note : It is possible to directly go to step 2 skipping step 1. Here, step 1 is included wo >I I> for clear understanding. a Solution : Boolean expression of EX-OR gate F = AB + _ F >> = (A+B)(A +B) De Fig. 2.5.13 (a) Note : We can implement OR-AND logic NOR-NOR logic. TECHNICAL PUBLICATIONS” An up thrust for knowledgeDigital Electronics 2-28 Logie ee Solution : K-map simplification Logic diagram De tT BC B+C B+T B+T B+c oo 01 11 10 ar>t | > Output Ciel Fig. 2.5.14 Multilevel Gate Implementations We know that logic gates can be cascaded to get the desired output. The maximum number of gates cascaded in series between a network input and the output is referred to as number of levels of- gates. Thus, the Boolean functions written in sum-of-products form or in product-of-sums form are the two level gate networks. Usually, it is assumed that all variables and their complements are available as network inputs. Thus, we will not normally count inverters connected directly to input variables as a separate levels in the network. Fig. 2.6.1 shows the networks with levels of gates. TECHNICAL PUBLICATIONS”. An up thrust for knowledgeDigital Electronics 2-29 Logic Gates Level 1 Level 2 Level 3 Level 4 mo Oa> 9 -p>——_ Fig. 2.6.1 (a) Four level network Let us consider a Boolean function. Level 1 Level 2 Level 3 F = ACD+ABD+ABD+ ACD j t, Dlo> cla> om>! COIs! This Boolean function can Levels :2 be implemented using two F Gates: 5 1 k hi ‘ ote inputs : 16 level network as shown in Fig. 2.62. The two level implementation requires 5 gates and 16 inputs. Fig. 2.6.2 Now we factorize the Boolean function and implement with gates. We observe that factorization increases the gate levels but decreases the gate inputs. F = ACD+ABD+ABD+ ACD = AD(G+B)+ AD(B+C) c B Dap j Levels : 3 B Gates : 5 Dz Gate inputs : 12 Cc & Fig. 2.6.3 TECHNICAL PUBLICATIONS”. An up thrust for knowiedgeDigital Electronics 2-30 Logic Gates Ome eel) 1. Write a short note on multilevel gate implementations. ‘| Multilevel NAND and NOR Implementations In the previous section we have seen that how AND-OR network can be converted to NAND-NAND network and how OR-AND network can be converted to NOR-NOR network. This logic can be applied to any even level AND-OR network or OR-AND network. This is illustrated in Fig, 2.7.1 (a) and Fig. 2.7.1 (b). sl a jt >-y Fig. 2.7.1 (a) AND-OR network >t —pIPDrip, ste Fig. 2.7.4 (b) Equivalent NAND-NAND network “ A 8 ” D Y E =L > Fig, 2.7.1 (c) OR-AND network A sp—L~ © D Y 7 Fig. 2.7.1 (d) Equivalent NOR-NOR network TECHNICAL PUBLICATIONS”. An up thrust for knowledgeDigital Electronics 2-31 Logic Gates Draw the multiple level NAND circuit for the following expression. W(X-+YZ) +XY. Solution : F = W(X+YZ)+ XY —$__— ¥ F = W(X+YZ)+XY Fig. 2.7.2152 Ch. 6 Combinational Example 6-17: Find the POS and SOP forms of Y¥ = Xim(0, 1, 3, 6, 7, 8, 9, 13, 15) Which is less expensive? SoLUTION: The map is shown in Fig. 6-18. Reading the I's, Y = BC + ABD + ABC + ABD (15 inputs) Reading the 0°s, Y= (B+ 6+ D\A+ B+ DXA+ B+ CA + B+ C) (16inputs) The SOP form is less expensive. Y= 8 + ABD + Aec + aD =(B+C+DNA+B+D)(A+B+C\A+B+C) FIG. 8-18 Example 6-17 Example 6-18: Find the minimum expression for the equation ¥ =D m2, 3,4, 5, 6, 7, 12, 13, 14, 15, 18, 19, 20, 21, 22, 23, 28, 29, 30, 31) . SOLUTION Plotting on a five-variable map (Fig. 6-19) and reading the I's for the SOP form, Y=C+8D Reading the 0's for the POS form, y=(8+CXC + D) The SOP form requires four inputs (note that there is no need for an AND gate for the C term); the POS form requires six. Therefore, the minimum expres- sion is Y=C+8DSec. 6-6 Product-of-Sums Reduction 163 Y=c+BD FIG, 6-19 Exomple 6-18 =(B+CNC +0) Maxterms Let's be logical about logic. If there is an animal called a minterm, there surely must be one called a maxterm. There is. A maxterm is a sum of all the variables within the logic system. If 4, 8, C, D, and E are all the variables within a system, then the following would represent maxterms: A.A+B+EC+D+E B.A+8+C+D+E CA+B+CH+DHE D.A+B+C+Dt+E BE, A+ B+ C+ D+E Just as any Boolean expression can be transformed into a sum of minterms, any Boolean expression can be written as a product of maxterms. Maxterms are plotted as 0’s on a map for the purpose of reduction. However, the numbering of maxterms is slightly different from the numbering of minterms. Referring to Fig, 6-20, read the square labeled “14” off the map as a sum: 4+ B + M,=A+B+C+D My =A+B4+C+3 40 at fs O-++m,-A+8+E+0 s| Fig.154 Ch. 6 Combinational Logic € + D. Ascan be seen, maxterm isis A+ B+ C+ Dwith the NOT literals called 1’s and the uncomplemented literals 0’s in forming the binary maxterm designators. Maxterm 4 (abbreviated My with a capital M) is A + B+ C+D,M,isA+ B+ C45, andM,,isA+B+C+D. Just as a problem can be stated as a sum of minterms, it can also be stated as a product of maxterms, with the Greek letter [J, upper case pi, representing a product: Y= 11 M@1,3.4) RAF BE CAT B+ CA +B 4 CHAT B+O -These 0's can then be plotted on a map, the rest ofthe squares set to I,and then reduced to SOP or POS forms. Example 6-19: Find the minimum expression of Y=][ MO, 1, 3, 5, 6, 7, 10, 14, 15) SOLUTION: Plotting these maxterms as 0’s on the map and the Fermaining squares as 1's results in Fig. 6-21. Reading the POS form, Y=(A+ B+ OKA + E+ DXA + DVB +O) resulting in 14 inputs. Reading the SOP form, y = d4BcB + BCD + ABD + AC resulting in 16 inputs. Therefore, the POS form is less expensive. co ABN 00 O11 oo} 0°|"0,1,0 st 3 oi 1,| 0 °° of ‘© |=9/6 a 1 Pe woh af 1] Y= A+B + CHA + C+ DIIA + DVB + C) Y= ABCD + BCD + ABD+ AC FIG. 6-21 Example 6-19 Example 6-20: Find the minimum expression for ¥ =I M@, 1,9, 10, 11, 13, 14, 15, 16, 17, 22, 23, 26, 27) SoLuTION: When dealing with complex maps, it helps to draw separate maps for reading the SOP and POS forms (Fig. 6-22).Sec. 6-7 Hybrid Functions 166 BC oo or _ 1110 oo Of 11_— 10 ol o| oj} 1} oo 1 Sete | T ot Tt itajolo ma 3 aie 0 Pelee eelan 1 1*Pololo ‘T'1 | 0] 0 Y=BGD + ABC + ABC + BOE + ACD + ABD (a) SOP Map DE A BC oo 01 1110 oo or 10 of [6] 1 [1 oS) 1]1 } of ata ja] 1} 1/83 1H} 4. | Oba? afafata 1o| 1 | o*f*or To 1|1[olo Y= (840+ DNB +C+ONA+B +E +0) A+B + ENA +B +O) (b) POS Map ® FIG. 6-22 Example 6-20 Reading the SOP map, Y= BCD + ABC + ABC + BDE + ACD + ABD requiring 24 inputs. Reading the POS map, Y=(B+C + D(B+ C+ DXA +B+C+D) x (A+ B+ EA + B+ D) requiring 21 inputs. Therefore, the POS form is the minimum expression. 6-7 HYBRID FUNCTIONS Sum-of-products and product-of-sums reduction produces an input gate feeding and an output gate. Therefore, it is called two-level logic, since cach input signal has to pass through two gates before reaching the output. This has the advantage of pro- viding uniform time delay between input signals and the output; if each gate has a 10-ns delay, all input signals are delayed 20 ns between input and output.156 Ch. 6 Combinational However, two-level logic does not necessarily produce the simplest ci How’s that for an eye opener! Here we spend all this time on minimization only find out minimum is not minimum. Many times it is possible to reduce a Bool SOP or POS circuit by factoring, producing a hybrid circuit—one that has than two levels. For example, the equation Y = ABC + ABD + ACD + BCDis minimum sum-of-products form and requires 16 inputs. The equation can be red by factoring, however; Y = ABC + ABD + ACD + BCD = AB(C + D) + CD(A + B) Implementing this result (Fig. 6-23) shows we have reduced the number of inputs from 16 to 12. Note, however, that the C input to the OR gate must go thro three levels of logic before reaching the output, whereas the C input to the AND gate must only go through two levels. This can provide a critical timing problem a logic race. Assume, for example, that each gate has a 10-ns delay and that A = @ B=0,C=1, and D = I. Gate A, will not AND since A and B are 0; gate Ay not AND since A + B= 0. ‘Next, assume A and B go high at precisely the same time C and D go low. A, will provide a | to A; for 10 ns after C and D go to 0 due to its propagation delay, and for that 10 ns all three inputs will be high, causing a 10-ns pulse to be outpt by 4,. At the end of this skinny pulse, 4, output will go low, blocking 4, ; since and D are already 0, A, output will go low. Had two-level logic been used, this logs race and its resulting pulse would not have occurred. ‘ => oO: A 8. Mg ci : B: => Y = ABIC + D) + CDIA + B) FIG. 6-23 Hybrid Logic Decoders A decoder is a circuit that will energize a particular line or lines, depending the binary code at the input. One such device decodes binary data and energizes particular line at the output specified by the binary code, Figure 6-24(a) illustrates circuit that has 16 output lines. A binary 12 on the input would energize line 12,® Soaasen oo o hed t= < 1 ad af a a D as A & 10 Le B 3 aX aA a E 3 z " o o i a» c 10 8 a se 4 & 12 1 P; 12 RK A Da 5 85 13 3 o: D iy X 8 AB 2C S, 8 14 5 a A © : {2) Block Diagram Fi 5 *o 7 °F 15, o ° (b) Using Four Input Gates {c) Two-Level Decoder Block Diagram 24 One of 16 DecoderCD Decoder (d) Two Level Decoder Logic Diagram FIG. 6-24 (continued) 158‘Sec. 6-7 Hybrid Functions 159 a binary 7, line 7. One possible manner in which this might be accomplished is to use 16 four-input gates, each decoding one binary input [Fig. 6-24(b)]. This would require 16 x 4 or 64 inputs, However, by converting this to a two-level function, we can save some money, To do this, we shall build two decoders: an AB decoder (a | of 4 decoder) and a CD decoder (a second 1 of 4 circuit). These two circuits can then feed second-level output gates (Fig. 6-24(c)]. The completed logic diagram is shown in Fig. 6-24(d), Note that the total input count is AB decoder 4x2=8 CD decoder 4x2= 8 Output gates 16 x 2= 32 Total 48 This compares with 64 if we had used the four input gates. This concept can be extended to any number of inputs. The general approach is as follows: A. List all the input variables. B. Break the list roughly in half, and continue breaking the resultant groups until groups of two or three variables are obtained. C. Design decoders for each group. Example 6-21: Design a 1 of 512 decoder using multilevel logic. SoLuTiON: The output variables would be ABCDEFGHI. Grouping these, (ABCDE)(FGHI) and again, (ABC) DEMEGKHD) ‘The block and logic diagrams for the circuit are shown in Fig. 6-25. Each decoder is a combinational logic circuit consisting of two or three input gates. Because the logic diagram is quite extensive, only the FGHI decoder is shown. If a single-level decoder had been used, the gate count would have been 9 x 512 = 4608 For this two-level circuit, the count is ABC decoder Bx3— 24 DE decoder 4x2 8 FG decoder 8 . HI decoder 8 ABCDE decoder 32x2 64 FGHI decoder 16 x 32 Output gates 512 x 2 = 1024 Total 1168160 Ch. 6 Combinational Logie ABC Decoder D. E 4 Lines 512 Lines f HI 1 Decoder DE Decoder ie FG s Decoder (a) Block Diagram FIG, 6-25 Example 6-21, One of 512 Decoder (a) Block Diagram Parity Detectors Another very useful multilevel function is the parity detector-generator. Figure 6-26 illustrates the circuit, which consists of cascaded exclusive OR gates. Remember that an exclusive OR gate will provide an output of | if either input (but not both) is a 1. Therefore, we could state that if the number of I's on its input i= even, it will output a 0; if odd, it will output a 1. When the gates are connected as shown, they can detect or generate parity, for when the number of I's at the input is even, the output is a 0. When the number of I’s at the input is odd, the output isal. The circuit shown can be used either to generate parity at the transmitter or to detect parity at the receiver. If used at the transmitter, bits A, B, C, and D are data bits and bit £ the parity bit. If odd parity is desired, bit E can be’ inverted. ‘When used at the receiver, the circuit detects parity over four bits,‘Sec. 6-7 Hybrid Functions 161 FG FG FG FG {b) Logic Diagram FIG. 6-25 (continued) (b) Logic Diagram D, and provides an error signal, E, if the parity is not even. If odd parity is used, Eis merely inverted, and the error signal occurs when parity is even. ‘Although a four-bit parity detector-generator is shown, any word length can be handled by connecting additional XOR gates in cascade. It should be noted, though, delay and logic race problems. that this increases propagation162 Ch, 6 Combinational AB+AB (a) Exclusive OR (XOR) Function -D- (b) Exclusive OR Symbol 3 E = 0 Even Parity E = 1 Odd Parity > c E D (c) Four Bit Parity Checker/Generator FIG. 6-26 Parity Generator/Checker 6-8 INCOMPLETELY SPECIFIED FUNCTIONS In all the previous maps, each minterm has been specified as a 1 or a 0. Hor many designs require that only certain of the minterms (or maxterms) be defined, any others could be either I's or 0's. An example of this is a binary-coded deci system where the binary states 1010, 1011, 1100, 1101, 1110, and 1111 never Let us assume we require a logic circuit to detect whenever a BCD nt higher than 5 (0101) occurs. The circuit will have four input lines, as shown in 6-27. Define the truth table by putting 0's in those states where a 0 output is desi 1's on those states where a | output is desired, and X"s on those states ‘that will occur, Reading the truth table, the function can be expressed as Y¥ = L m6, 7, 8, 9) + d10, 11, 12, 13, 14, 15) where the d terms represent the unspecified states: those that will never occur. terms are also called the don’t cares. ‘Next, transfer this information to the map. Then read the SOP form off the using the X’s as 1’s whenever needed to make a larger 2"-square as shown. This in Y=A+BCMsBOA——> B Combinational c Logic i, sD D>} {2} Block Diagram ‘A 00:00 ODO 11111117 B 0000 1111 0000 1111 © 0011 0011 0011 0011 D 0101 0101 O101 O11 Y 0000 0011 11XX XXXX {b) Truth Table co aB\_00 011110, + = ] oo] ope fee see 2H or] 0. O | 4 1 34 rw wt X x x x 12] “sas | aa op ee |x | af of nf] “vo (c) SOP Map (a) POS Map 8. c Y re (e) AND-OR Circuit 8. c Y A (f) NAND Circuit FIG. 6-27 Don't Cares 163—— _ ar 164 Ch. 6 Combinational Logic By using the don’t cares as shown, the result was a less expensive circuit, for if these had been 0's, the result would have been Y = ABC + ABC However, the POS form must also be evaluated. Maybe there is an even less expensive circuit. Therefore, combine the X’s with the 0's on the POS map, whenever helpful, and read the result, In this particular problem, there are three equally expen~ sive POS forms: Using four-squares 1 and 2 Y= (A + BYXA+C) Using four-squares 2and4. ¥Y=(B+CYXA+C) Using four-squares | and3 Y= (A + BB+ C) All three are more expensive than the SOP form, which is shown implemented in AND/OR and NAND logic. ‘What would happen if a 1011 were to appear at the inputs (even though we said it never would)? Examining the SOP map, note that all the don’t cares were assumed to be 1’s. This includes minterm 11 (binary 1011). Therefore, 1011 will result in a 1 appearing at the output. Keep in mind that the only “don’t care” about a don’t care is that we don’t care whether it is a 1 or a 0 in the final design. During the process of design using an SOP map, each don’t care will be combined with a 1 to form a 2 square (in which case we are declaring it a 1) or it will be left alone (in which case we are declaring it a 0). Correspondingly, don’t cares combined with 0’s on a POS map are 0's, and those left alone are 1's. Therefore, all don’t cares will ultimately be resolved to I's or 0's. After all, these are binary systems, and only two states are allowed. Example 6-22: Design the minimum NAND logic circuit to detect a decimal 3, 4, 5, or 6 in 5211 code. SOLUTION: Referring to Table 3-1, fill out the truth table (Fig. 6-28), Each 5211 code represents a minterm. For example, a decimal 4 is 0111, which is minterm 7. Then transfer the truth table to SOP and POS maps. Reading the two maps, SOP Y= 4B+ AB POS Y=(4+ BA + B) Since the SOP requires six inputs and POS six inputs, the SOP circuit was arbitrarily implemented (Fig. 6-28). Example 6-23: A circuit is to be designed that has one control line and three data lines. When the control line is high, the circuit is to detect when one of the data lines has a 1 on it. No more than one data line will ever have a | on it. ‘When the control line is low, the circuit will output a 0, regardless of what is om the data lines.msB A 0000 0000 1111 1111 B 0000 1111 0000 1117 c 0011 0011 0011 0011 isB D 0101 0101 0101 0101 Y 00XO X1X1 1X1X 0X00 “(a) Truth Table cD Ad\00__O1_11_10 AB\_0 011110 0/0); 0 Os]. % wo} O21 910 x orl x Tak o1 x [1 1|x " Cant nlo}|x]o}o Myo}; x}o]o L— ern 10 x |x wl 1} x|x}4 xx] i >I Y=(A+B)(A+B) (c) POS Map (d) AND-OR Circuit (e) NAND Circuit Example 6-22166 Ch. 6 Combinational Logic Sotution: A block diagram for the cireuit is shown in Fig. 6-29(a), with C being the control line and D,, D;, and D, the data lines. Next, the truth table is shown, with. X's (don’t cares) entered anytime more than one data line is high, 1 anytime C is high and one of the three data lines is high, and 0's for all other rminterms. I have to confess that when I first drew the truth table, I incorrectls ( 0, Logic dD, Circuit = Da (a) Block Diagram © 0000 0000 1111 1411 D, 0000 1111 o000 1111 D, 0011 0011 0011 0011 Dy 0101 0101 0101 0101 je ait ee Z 00x Oxxx 011x 1Xxxx (b) Truth Table 0,0, coN 011110 wf oto TxTo offot xt xt x Wit? xTx]x 10! 0 x 2Z=CD, + CD, +CDa Z=(D, +0, +D,IC (c) SOP Map (d) POS Map. ogg (e) NAND implementation FIG. 6-29 Example 6-23Sec. 6-9 Multiple-Output Minimization 167 put 0's on Z anytime C was 0. However, the more don't cares that are used, the simpler the final circuit. Therefore, I corrected the table to that shown. ‘Next, POS and SOP maps are constructed from the truth table. The two results are Z=CD,+CD,+CD; = C(D, + D + Ds) Since the POS is simpler, it is implemented in NAND logic. The inputs to the OR gate have been negated, and by the time they pass through the inverter on the input to the gate, they will appear noninverted, as the equation specifies. 6-9 MULTIPLE-OUTPUT MINIMIZATION Up to this time, we have only considered logic systems that have multiple inputs and one output. However, there are many design problems requiring several outputs, as shown in Fig, 6-30. One example is of a dual output function where input lines 'A, B, and C are to provide two output lines as defined by W and X in the truth table (Fig, 6-31). The maps for W and X are shown in Fig. 6-31(c) and (4). The results from Loic CIRCUIT Combinational = Logic (a) Block Diagram A 0000 1111 B 0011 0011 € 0101 101 w 1110 0010 x 1101 1011 (b) Truth Table FIG. 6-31 Multiple Output Minimization168 Ch. 6 Combinational BC Noo 1 10 Xo or 1 10 o} ay" 0 * Prt oles rfatafo fof ofo|*1 afolt]a (c) W Map (d) X Map. 8 é We A a 6 : x c A Cc (e) Logic Diagram BC A\_©_o1_11_10 of 171] 0] 0 ifofof ol (f) WX Map FIG. 6-31 (continued) the W map are aa W = AB + BC However, there are two possible ways to read the X map: X= BC+ AC + AB X= AB + BC+ AC But note that the W output has an 4B term in, the expression. If we were to-chooseSec. 6-9 Multiple-Output Minimization 169 second X expression, we could share this 4B term between the W and the X outputs, as shown in Fig. 6-31(e), and further minimize the circuit. If we did not choose this X expression, the circuit would not be minimum. This sharing of gates forms the basis for multiple-output minimization. It was fortunate that we saw that the 4B term could be shared between the W and X output expressions. There are several methods that allow us to see the sharing possibilities even more clearly without having to resort to as much intuition. One of these methods requires the construction of another map in which each output minterm is ANDed with the corresponding minterm of the second output and the results placed on this third map. Therefore, all the I’s on this third map represent minterms that are common between the two outputs. Figure 6-31(f) shows such a map for the previous illustration. By examining this map it becomes obvious that the 4B term is shared and can be used to minimize the circuit. The 4BC term is also common. How- ever, there is no way of reducing the input counts by its use. Example 6-24: Solve the following multiple-output equations using mapping: St, = Xm, 1, 2, 4, 6, 7, 10, 14, 15) fr = X mB, 4, 5,9, 10, 11, 14) SoLuTION: The maps for f, and fy are shown in Fig. 6-32(a) and (b). The terms common to f, and f, are Sicha = Lim, 10, 14) This was also mapped, resulting in the possible dual use of the ACD term. Then, the f, and f, maps were minimized, making an effort to use this ACD term. The results were f, = ABC + AB + BC +- ACD fy = ABC + ABD + BCD + ACD The logic diagram is shown in Fig. 6-32(d). cD cb cD AB\ oo or 1110, ABN oo Or_stt 10 ABN O_O eae TS ate ve1/ 0 \! 00} 0} 0}]1 0 mo} 0)/0/0);0 ol | of [21] of aftr | ol] 0 o/1]o]o] 0 Ht pe 7 ny) 0 Oo} 1 3! nl} o}o};0 i »}0);0;0 w)o] of oft ro] o | afer] ufo] oo] (a) f, Map. {b) f, Map (6) f,f Map FIG. 6-32 Example 6-24170 Ch. 6 Combinational Logie. {d) Logic Diagram FIG. 6-32 (continued) Incompletely Specified Functions Incompletely specified functions involving only two outputs can easily be solved. using maps. The only difference between these and single-output procedures is the generation of the shared-term map. If this map is used to generate a shared gate, and a particular minterm covered by that gate must be a I for one of the functions, then it must be a | for the shared-term map. Therefore, the shared-term map must obey the ules listed in Table 6-3. For example, if minterm 13 of f, is a I (do care) and m,, of JS; is a don’t care, then m,, of the shared-term map must be a 1.Sec. 6-9. Multiple-Output Minimization im AB TABLE 6-3. Generating Minterms for a Shared-Term Map fh te th xX tx 4x0+00 X4+4xOxe+0 x 44400000 Example 6-25: Design a multiple-output logic circuit using the following func- tions: fi = X mC, 3, 7, 10, 11, 14) + d(, 5, 15) F2 = Lm, 1, 4, 7, 13, 14) + als, 8, 15) Sotution: The two functions are first mapped (Fig. 6-33(a) and (b)]. Then, the shared-term map is generated according to the rules in Table 6-3; the map is shown in Fig. 6-33(c). Terms ABC, ACD, and ABD are candidates for shared terms, Since ABC must be generated for f, the same gate can be used for f,. However, m,, of f; can only be covered using the four-square shown, so, rather than generate ABD for use only in f,, four-square AD was chosen, since it is less expensive. The final functions are Si = BC + ABC + AD fr = AC + BD + ABC The logic diagram is shown in Fig. 6-33(d). co co co 00 ABN 00) Son 4110. ABN to. or 11 10 0} 0 00 vd o}o m] 0 js] 0 oi] 0 a} 1exi[ i} o of o [xT | 0 ate ufo nfol apex ya nlof}o| xy 10] 0 wx) O0;0]0 101 0] OJ oO} Oo (0) f, Map (yf Map FIG. 6-33 Example 6-25172 Ch. 6 Combinational (4) Logie Diagram FIG. 6-33 (continued) 6-10 VARIABLE MAPPING The variable mapping technique is one that allows us to reduce a large mapping problem to one that uses just a small map. It is especially useful in those problems having a few isolated variables among more frequently used variables. Consider the equation: Z = ABC + ABC + ABCR + ABC + ABC Normally, this would be a four-variable problem. However, using variable mapping we can make it into a three-variable problem. Assume this is a three-variable problem in A, B, and C. Thus. we have: A= mg + ms + mR) + m, + me In such a problem we would put I’s on the map where the minterms appear and O's where they do not. Each 1 represents a minterm. Therefore, if we put 1-R, it will represent that variable multiplied by R. Figure 6-34(a) illustrates the map. We should next recognize that each 1 entered onto the map represents R-+ R [Fig. 6-34(b))- Finally, we must cover each of the individual variables. This can be done by making a 2-square of the R in m, and the R in m, and making a 4-square of mg, m,, m, andSec. 6-10 Variable Mapping 173 Bc A 00S OPA 10) o| o 0 R o ° 1 a 2 Le TA 1 1 1 ‘ 5 7 ‘ 2=ABE + ABC + ABCR + ABC + ABC (a) Original Map Bc A o oo nN 10 ° ° 2 1 R/+R] R+R 7 3 A= A+ BCR (b) Combining Squares FIG. 6-34 Variable Mapping .. The map is read as before except that squares with a single R term must be mul- tiled by R in the result. This yields: Z=A+ BCR Note that the R in m, was covered twice. However, our objective is to cover all the variables at least once. Example 6-26: Reduce by mapping: M = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD SOLUTION: We can convert each of the four-variable minterms to three-variable minterms multiplied by a D term: M=m,D +m,D + msD + msD + m,D + m,D + mD + mD Now we can map each, including the D variable, on a 3-variable map IFig. 6-35(a)], Note that I's are entered as D + D. For exampte, my = m,D + mD.Ch. 6 Combinational M= BC + ACD + BCD + ABT FIG. 6.35 Example 6-26 The result is: M = BC+ ACD + BCD + ABé Note that all parts of a | (D + D) must be covered. Example 6-27: Reduce: Z= ABCDE + ABCDE + ABCD + ABCDF + ABCD + ABCD Sovution: Ordinarily, this would be a 6-variable problem. However, we can map it into 4 variables as shown in Fig. 6-36. Ones have been entered in My, Mya and Ms4, tecognizing that m, is E+ £ and m,, is F + F. Reading the map, we have: 2 = ACDE + ABDE + ABB + ACDF Note that this method greatly reduces the work required. cD a8 oo ot " 10 ay 00 oO oO E ov oo of _epeew [a on oO E 1 o ‘ | | ° +— W 1 oO 0 1 wl} owl wl if Ties] 10 oO oO o F 8 } on 0 ACDE + ABDE + ABD + ACDF Fia.6-36 Example 6-27Incompletely Specified Functions The procedure used for previous don’t care problems has to be modified only slightly to accommodate variable mapping. Assume we had a three-variable problem, ‘A, B, and C. Then an entry of 1 on the map represents D + D. An entry of X (don't care) on the map represents XD + XD, a don't care in both the D and the D min- terms. For example, if m, is a don’t care, we are saying that: m, = ABC = ABCD + ABCD = m(D + D) ‘Thus, whereas we would normally enter an X into square 6, we would enter XD + XD. These don’t cares may or may not be covered. They should be used to make 2" squares when covering other do care squares. There is, however, one more case of a don’t care: that of a particular minterm which is multiplied by the variable. Assume a 3-variable problem where ABCD is a don’t care. We have: ABCB = m,b Expressed as a don't care, square 2 would contain an XD. Example 6-28: Solve using 3-variable mapping: W = Dm, +m, + Dm, + d(m, + Dm.) SoLuTION: The map is shown in Fig. 6-37. Study each square carefully and observe how each was entered. The D in m, can only be covered by combining it with the XD of m,. Similarly, the D of m, can only be combined with the D of mg. This leaves the D of m, uncovered. We can combine it cither with the D of ms or the XD of m,. Both yield 3-term results. Reading the map: w= BCD + ABD + BCD Bc “ 5 7 6 FIG. 6-37 Example 6-28 w = BcD + ABD + BCD 175