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    AVD 3 Solutions

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
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    48 views8 pages

    AVD 3 Solutions

    Uploaded by

    Nikhil Hosur
    AVD 3 Solutions

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    of 8
    University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-12:30 Thursday, November 10, 6:30-8:00pm. EECS 141: FALL 2005—MIDTERM 2 Midtevm Solutons NAME Last First Problem 1 (8): Problem 2 (16): Problem 3 (11): Problem 4 (5): Pm [| L 3 bit adder BCS 141: FALL 200S—MIDTERM 2 1 PROBLEM 1: Wires (8pts) Consider RC network shown in Fig. 1. Assume the transmission gate can be modeled as a resistance R3. Capacitance of this gate is included in C3. Fig. 1: RC network. a. Write expressions for the time constants associated with Clk, Clkz, and Clks. (6 pts) +2 | m= Rit (RtRe) Cot RiCst Rt Rt RurG +(RARd) ADL | mR, + CR rRa) Ca t RG + CRtRa)Cy + CR Rarhs) Cs +2 [a= Reve (RitRe) Cg + RCat Ri Cet Riss b. IfR)=Ro=Re=Rs=R, C.=Co=C3=Ca=Cs=C, what value of R; (in terms of R) is required to balance the delays to Clk, Clkz, and Clks? (2 pts) +h Te T= 7Re 44 9Re = Ty= SRe + Rae Re = 4R ECS 141; FALL 2005—MIDTERM 2 PROBLEM 2: Logic Gates (16 pts) Consider dynamic gate shown in Fig. 2. Assume Cgs = Cgd = Cdb = Csb = S * 1fF, where S is the size of the transistor as indicated in the schematic. The input capacitance of the inverter is 20 fF. Vp = 2.5V Fig. 2: Dynamic gate. a. Is it the best to make Vm of the inverter equal to Vpp/2, greater than Vpp/2, or less than Vop/2? (3 pts) Circle one answer: Vm = Vpp/2 Va > Vpp/2 (Gave?) CQ) pF. Briefly explain your answer below: faster pull-down at the output of inverter (1) pt b. What are the logic levels of inputs A and B that create worst-case charge sharing scenario during evaluation phase? Circle one answer: (1 pt) A=B=0 A=0,B=1 A=B=1 (19 pt What is the worst voltage level at node X resulting from charge sharing effects? (4 pts) Cue CCegd *Cae) + (egd+ Cole) + 20 =34F (2) ph Cy= €(Cgs+ Cee) + 6(Cga* Cas) = 24° C1) pt Vee Vdd OY 2 ge ye At cy ogy (1 pt CxtCy 56 EECS 141: FALL 2005—MIDTERM 2 ¢. In addition to charge sharing, assume each transistor connected contributes S* InA of reverse biased diode current. Assume Vu of the inverter is Vpp/2. For how long will the output be valid in the evaluation phase? (4 pts) + Lpts —05 For each Arode (v3) Traua= 1A US OS For signs + Apr - Jav( = Vad -Los4 = ols + pt - Qe Cxttyav= Trt d. Write Boolean expression that describes logic function of the gate below. (2 pts) Fig. 2d: Logic gate. e. Implement gate from part (4) in static complementary CMOS using minimum number of transistors. You may assume both true and complementary inputs. (2 pts) ec Noe + PON bd pa +1 PDN e_4 b-B b—- c E ECS 141: FALL 2005—-MIDTERM 2 4 PROBLEM 3: Logical Effort (11) For logical effort calculation, assume that the PMOS/NMOS width ratio in the unit inverter is 2/1 a. Determine the logical effort of inputs A, B, and C for the gates shown below. Also, determine the parasitic delay of each gate. (5 pts) v, r Ex= “4/3 (0.5 pts) a4 Lee= t/3 (oS ps) 4 Bq oar LEc= Y3 (0.5 pts) coe | Yop 4-qi 2 Out B- Ec [EBCS 141: FALL 2003—MIDTERM 2 b. Sizes the transistors in Fig, 3b so that the circuit provides the same pull-up and pull-down current at the output Out as a unit inverter. The input capacitance of all inputs (4, B, and C) should be equal. (6 pts) Me= 45° Chet) Ms= 3.5 (tpt) Me= 315. Ctpby Out Fig. 3b: Complex logic gate. For the pull-down network * Solvina © and © Hs = t,t21 © for Hy and Ms! My Mo note that inputs A and C ave Maz S++ 0% 2 4s idertical . a MeHg, and Us=Me © Me = Ment combining, © ard © * M= 42 = 2 Fer the pull-up network iL 124 sane PO Hy” Me © ac inverter Hy + M32 Met My © + same tnpet caps Metl =Mo+2 © Hy -l = Ms BCS 141: FALL 2003—MIDTERM 2 PROBLEM 4: Arithmetic Blocks (5 pts) 16-bit (N= 16) Carry Skip Adder is shown in Fig. 4. It is organized in blocks of B= 4 bits, For simplicity, assume fearry = lum = fokip- YOu may ignore fren bits 0:3 bits 4:7 bits 8:11 bits 12:15 4-bit ‘a-bit 4-bit abit block block block block CTT Yes | OPT PPe | Col [PPen] Csf [PPias Co skip skip skip skip > ‘ ¥ Gs z Con + Cou ¥ ‘o1S sum sum sum sum ree a. Implement the skip function using transmission gates and inverters. (2 pts) P a7 ‘nvertey (0.5) ph inputs (0.5) pt |F

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