Reg. No. Question Paper Code: 97046 BE/B.Tech. DEGREE EXAMINATION, NOVEMBERDECEMBER 2014, ‘Third Semester ~~ Computer Science and Engineering 8 6303 — COMPUTER ARCHITHCTURE C A a (Common to Information Technology). », e (Regulation 2013) ~ ‘Time : Three hours & Xo Maximun : 100 marks Anewor ALL quostiiong. 1. State Amdahl's Law. a okey ay Brief about Relative addpoaginemode with an example * 8. ee eae ment. 4. Whatis DMV? oY What isthe nd fe Speculation? 6. Whatis Exception? eae <\ What is Flynn's Classification? “8. Brief about Multithreading. 9. Differentiate Programmed 1/O and Interrupt VO. 10. Whatis the purpose of Dirty/Modified bit in Cache memory? rejinpaul.com (Grow. With UsDownloaded From www.rejinpaul.com } PART B— (5 x 16=80 marks) 11. @) @ Assume a two address format specified as source, destination Examine tho following sequence of instructions and explain the addressing modes used and the operation done in every instruction, (10) (1) Move (Ré)+, RO t @) Add 5), RO (3) Move RO, (Rs) ) Move 16(Rs), Ra C ‘ ee Noe (6) Add #40,R5, (i) Consider the computer with three instruction oad CPL measurements as given below and Instructiép-counts for each instruction class for the same program from oo ferent compilers are given. Assume that the computer's clock Yigte Ys 4GHZ.Which Code sequence will execute faster aczordin ution time? - (6) Code from CPI for this InatiyerionAlass 4A § / CPL L Ms Code from Instruct unt for exch Class * wY c Commie, MY 1 2 contig? Y Ny or (b) G)_—_Explain the edmyongnt® of a computer System @) Gi) State # U performance equation and discuss the factors that affect perfxance (8) 2. @ @ Aliply he following pair of signed nos. using Booth’s bit-pair coding of the multiplier. A = +13 (Multiplicand) and B = -6 ee ao @) Briefly Explain Carry lookahead adder © i Or “\(b) Divide (12)i0 by (21 using the Restoring and Non restoring division Ava algorithin with step hy step intermediate results and oxplain. 6) 18. (a) Explain Data path and its control in detail. 6) Or (b) What is Hazard? Explain its types with suitable examples. (16) 2 97046 2 © Co... Grow With Us14. (a) ) 15. (a) (b) Explain Instruction level parce eee eth chalieng op parallel Processing. (18) e Or Explain the tarms: @ «@) @ a oO a) Multicore Procsssor. Hardware Multithreading. (18) Explain mapping functions in cache memory to determine how memory blocks are placed in Cache ay Explain ia detail about the Bus Arbitration techniques in ey Or “ Draw different memory address layouts and brief abot the technique used to increase the average rate of fetching worlds from the main memory. ie ®) Explain in detail about any two StandartyInfwt and Output Interfaces required to connect the I/O devide to tHe Bus. _ ® » / 5 97046 inpaul.com Grow With Us