LVF Characterization in SiliconSmart

Ning Jin – GLOBALFOUNDRIES Inc

Suhas Subhaschandra – Synopsys Inc

March 31, Year 2016

SNUG Silicon Valley

SNUG 2016 1
 Agenda

Introduction to GLOBALFOUNDRIES 14nm Technology

LVF Characterization in SiliconSmart
LVF Correlation Results
Conclusion

SNUG 2016 2
 Agenda

Introduction to GLOBALFOUNDRIES 14nm Technology

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 GLOBALFOUNDRIES 14nm
FinFET Offers Breakthrough Performance & Power
Device
Lg Performance
Gate length shrink
enables performance
scaling +50%

3D control over the

channel

Double-gate
reduces off-current

Total Power
• Intrinsically operates at lower supply voltage (“FD”
behavior)
• Reduced off-state leakage
• Faster switching speed – high drive current

28nm 14LPP
-65%

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GLOBALFOUNDRIES
 Effect of Random Device Variability

• Delay variability (including CLK-to-Q delay)

– The delay varies for each cell/edge (rise vs fall)/type (early vs late)
– The delay varies based on the active arc/input transition/output load

• Constraints variability (Setup and Hold)

– The constraints vary based on
the slew on both Data_pin and
CLK_pin
• Output transition
– The output transition can vary with
input transition and output load
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 Evolution of Variation Modeling

• Different design margining methodologies have evolved over the course of many years.

AOCV POCV LVF

object_type: lib_cell
delay_type: cell
rf_type: rise
derate_type: early
object_spec: */INV
depth: 1 2 3 4 5
distance: 0
table: 0.89 0.91 0.93
0.95 0.97
ocvm_type : pocvm
object_type: lib_cell
delay_type : cell
derate_type: early
rf_type : rise
object_spec: */INV
coefficient: 0.0366
ocv_sigma_cell_rise(lut_4x4) {
sigma_type : "early" ;
index_1("0.000617, 0.00391, 0.0154,0.0375");
index_2("0.0001, 0.00154, 0.00663, 0.0163");
values("0.00467, 0.0085, 0.0216, 0.0466",\
"0.00675, 0.0107, 0.0239, 0.0489",\
"0.0114, 0.0179, 0.0321, 0.0570",\
"0.0159, 0.0259, 0.0469, 0.0732");
}

• Side file with • Sigmas modeled in Liberty file as tables

• Side file with derates
coefficients
• Simulation at 1 input • Simulation for every input transition/output load
• Simulation at 1 input
transition/output load for every arc
transition/output load

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 LVF Characterization in SiliconSmart

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 LVF Characterization in
SiliconSmart
• Two methods available
– MonteCarlo (MC) – Golden reference method used for accuracy analysis purposes
– Sensitivity-Based Analysis (SBA) – Recommended method to be used in production
environment.

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 Golden Reference
Monte Carlo Method

Generate random samples Estimate sigma from sampled data

following the input distributions early late

P1
Nominal point Delay
(no variation)

P2
Separate early/late sigmas
- Model asymmetrical distributions
- Each side is modeled as a Gaussian

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 Production Method
Sensitivity Based Analysis
Sample the nominal
Sample each parameter at two points (e.g. -3σ,+3σ) delay late
Compute sensitivity to each parameter (sp1,sp2)
P1
early

late
delay
P1

P2

early
P2

Cell delay variation computed by addition in quadrature (also called RSS)

σ delay = (sP1σ P1 )2 + (sP 2σ P 2 )2 +  + (sPNσ PN )2

- If two points are defined, SiliconSmart will model separate early/late sigmas

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 Basics of SBA Characterization
• Uses independent statistical parameter in transistor models
• GLOBALFOUNDRIES technology models variation with 6 independent parameters
• Simulates each parameter independently (P1, P2, … P6)
– At nominal
– At 2 points (e.g. -3σ,+3σ) for every input transition and output load for every timing arc
• Compute sensitivity for each parameter (sp1,sp2, … sp6)
• Example Nominal

D Flip-Flop -3σ +3σ

24 transistors
24 x 6 x 2 = 288 simulations P1
7 x 7 delay table
SBA method total simulations : 288 x 49 + 49 nominal = 14,161
MC method total simulations: 1000 x 49 = 49,000
~3.46X simulation reduction comparing SBA vs. MC!! P2

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 LVF Characterization in
SiliconSmart

• Offers multiple optimization methods to improve throughput while improving

accuracy/runtime tradeoff
– Screening
– Netlist pruning
– Binning
– Reduction factor

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 SBA Optimization
Screening Parameters affecting
cell delay
• Screening simulation will identify

Normalized delay
parameters not affecting cell delay
– These parameters are removed from
further simulations Sensitivity parameters

Screened parameters that do not

impact cell delay significantly
• Screening done for small subset of points
on table
Output load index

Input transition index

1 2 3 4 5 6 7
8 9 10 11 12 13 14
• Other points use results that closely match 15 16 17 18 19 20 21
screening point 22 23 24 25 26 27 28
29 30 31 32 33 34 35
36 37 38 39 40 41 42
43 44 45 46 47 48 49

Screening simulation done for

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selected points 13
 Optimization
Netlist Pruning

• Removes inactive nodes from the sensitized path Cell AO21

– For arc BZ, transistors not affecting netA in the AND

gate will be removed
– netA is set to an appropriate voltage
• Pruning results in faster simulations by using:
– Reduced netlist
– Reduced number of sensitivity parameters Z
• Observed no affect on accuracy
• Netlist pruning and screening optimizations reduce
14,161 simulations to just 752 for D Flip Flop!!
• 20X reduction in simulations

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 Optimization
Binning

• Reference/baseline library
analyzed to determine if timing
groups for the same arc can be
grouped/binned.

• Tables binned if all individual

points between tables match within
given threshold
• Sigmas characterized for a
single table and modeled for other
binned tables
AOI22 Delay (A->Z) for Cond1
AOI22 Delay (A->Z) for Cond2
• Difference in delays of
Cond1 and Cond2
compared against
1%,1ps threshold
• Cond1 & Cond2 not
binned as all points do
not meet threshold

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 Optimization
Reduction Factor
• SiliconSmart will characterize sigmas for all points in table by default
• Optimization allows to characterize for a reduced number of sigmas and
populate the rest using interpolation
• Provides user with direct control over runtime
Interpolated sigmas

0 1 2 3 4 5 6 0 1 2 3 4 5 6

7 8 9 10 11 12 13 7 8 9 10 11 12 13 reduction_factor=0.6
14 15 16 17 18 19 20 14 15 16 17 18 19 20
Characterizes 60% of
21 22 23 24 25 26 27 21 22 23 24 25 26 27
points
28 29 30 31 32 33 34 28 29 30 31 32 33 34

35 36 37 38 39 40 41 35 36 37 38 39 40 41

42 43 44 45 46 47 48 42 43 44 45 46 47 48

Default = 1.0
Characterize all points in table Characterized sigmas
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 Optimizations Order

• Analyze baseline lib to reduce arcs to be characterized for LVF

Binning • Effective for cells like AOI with large number of arcs with similar data

• Reduce number of transistors in the netlist

Pruning • Effective for cells with large netlists where all devices in a path do not switch
characterize

• Reduce the number of simulations

Screening • Simulate sensitivity parameters with the largest impact

Reduction • Reduce number of points to be simulated

Factor • User control on tradeoff between runtime and accuracy

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 LVF Characterization Results

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 LVF Qualification Setup/Criteria

Liberty file with NLDM + CCSTN data

• Verify accuracy of SBA against reference

Characterize LVF Characterize LVF MonteCarlo
compare
with MonteCarlo using SBA • Compare LVF characterization runtime
libs
against NLDM+CCSTN

Implement ARM®
Cortex®-A9 Processor

Timing analysis in • Compare PT results against spice

PrimeTime simulation to verify accuracy
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 LVF Library Qualification
Criteria for Accuracy Evaluation

• Experiment to compare accuracy of MonteCarlo results against Sensitivity Based Analysis

• Based on a subset of cells in the GLOBALFOUNDRIES 14LPP library

Library of 139 cells (66% Combinational - 34% Sequential)

1 cell per family used in the analysis

LVF Liberty File LVF Liberty File

Using MonteCarlo Using SBA

compare_library

• Library validated using compare_library in SiliconSmart

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 LVF Library Qualification
Accuracy Experiment Results
• Comparison using Monte Carlo vs Sensitivity Based Analysis
Distribution of delay sigma delta Distribution of slew sigma delta Distribution of constraint sigma delta

Frequency
Frequency

Sigma difference (ps) Sigma difference (ps) Sigma difference (ps)

Delay sigma tolerance : 5%,2ps Slew sigma tolerance : 5%,2ps Constraint sigma tolerance : 5%,5ps
Pass rate : 99.9% Pass rate : 99.9% Pass rate : 96%
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Constraint resolution : 5ps 21
 LVF Library Qualification
Criteria for Runtime Evaluation
• Based on all cells in the GLOBALFOUNDRIES 14LPP library

Library consisting of 809 cells

(80% Combinational - 20% Sequential)

NLDM/NLPM/CCST/CCS-
Noise Library Generation
Runtime compared between the
50 CPUs baseline library and the LVF
add-on characterization
Add-On Flow for LVF using
Sensitivity Based Analysis

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 LVF Library Qualification
Runtime Experiment Results
• Optimizations allowed 10x reduction in runtime with negligible impact on accuracy

no optimization

binning

pruning

screening

reduction factor

• LVF characterization with optimization is comparable to baseline characterization

Run Time (hrs)
CCSTN + NLDM/NLPM 12.6 1X runtime
LVF with SBA 10.3
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 LVF Correlation Results

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 PrimeTime Correlation Experiments
Setup

Implementation of ARM® Cortex®-A9 Processor

Using baseline library

Static Timing Analysis in PrimeTime SPICE MonteCarlo simulations (Golden Reference)

Using baseline library with LVF add-on (µ+3σ) calculated for setup

Compare

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 PrimeTime Correlation Experiments
SPICE Accuracy – Setup Analysis
Setup MonteCarlo-based STA to SPICE Correlation
0.0%
0 2 4 6 8 10 12 14 16 18 20
-1.0%

-2.0%

-3.0%
%Difference

-4.0%
SPICE(µ+3σ)
-5.0%
STA(µ+3σ)
-6.0% SPICE MEAN

-7.0%

-8.0%

-9.0%

-10.0%
Path ID

• Setup analysis for 20 paths shows an average difference of 2.1% between STA using
LVF library and SPICE MonteCarlo simulations
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 Conclusion

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 Conclusion

• LVF provides a fine grain representation of timing variation.

– It is the recommended variation methodology if reduced design margining is needed
– It’s exhaustive nature presents a challenge to characterization runtime

• SiliconSmart LVF characterization provides an optimal balance between accuracy and runtime.
– SiliconSmart has multiple features that allow LVF characterization to be done in a time that is around
1X of baseline library characterization time
– User control over the tradeoff between accuracy and runtime

• SiliconSmart characterized LVF library yields close correlation (< 5%) between static timing
analysis and SPICE MonteCarlo simulations.

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 Acknowledgement

GLOBALFOUNDRIES Design Methodology Team

Tamer Ragheb Ramya Srinivasan

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 Thank You

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 Evolution of Variation
Characterization
• Which method to use? Pessimism Reduction
 Global flat derate  On-Chip Variation (OCV)
 Table based granular derates  Advanced OCV OCV
90nm and above
(AOCV)
 Parameterized approach  Parametric OCV (POCV)
 POCV with slew/load dependency  Liberty Variation AOCV
Format (LVF) 65nm and below

• SiliconSmart allows the characterization of POCV/LVF

AOCV, POCV and slew/load based POCV 14nm and
below
(LVF)
– Allows the generation of AOCV/POCV from LVF

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 Experiment Setup

• We used an ARM® Cortex®-A9 Processor implemented at low-power 14nm

technology node

• Used SiliconSmart for Characterization and PrimeTime for timing

– SiliconSmart version 2015.06-SP2
– PrimeTime version 2016.06-BETA

• Library characterization corner: SS, 0.72V, 125C

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