library ieee;

use ieee.std_logic_1164.all;
entity motor_dos is
port (
RST: in std_logic;
CLK: in std_logic;
CM: in std_logic;
CE: in std_logic;
STF: in std_logic;
STL: in std_logic;
M: out std_logic;
Y: out std_logic_vector (1 downto 0)
);
end motor_dos;
architecture simple of motor_dos is
signal Qp,Qn: std_logic_vector(1 downto 0);
begin
combinacional: process(Qp,CM,CE,STF,STL)
begin
case Qp is

when "00" => if(CM='1') then Qn<="10";

elsif(STL='0') then Qn<="01";
else Qn<="00";
end if;

when "10" => if(STL='0') then Qn<="11";

else Qn<="00";
end if;

when "01" => if(CM='1') then Qn<="11";

else Qn<="00";
end if;

when others => if (CE='0') then Qn<="00";

elsif (STF='1') then Qn<="00";
else Qn<="11";
end if;
end case;
Y<=Qp;
if (Qp="11") then M<='1';
else M<='0';
end if;
end process combinacional;
secuencial: process (RST,CLK)
begin
if(RST='0') then
Qp<="00";
elsif (CLK' event and CLK='1') then
Qp<=Qn;
end if;
end process secuencial;
end simple;