it illator (or a timer) an AND-logic gate with an SCL "Nn gate Fig. 4260, in normally connected winding as a blocking oscillator, I ; leap fain as shown in could generate a pulse train as sl My a uffer stage. is cannot drive transistor Q; directly, and a buffer stage Fee before the transistor. in Fig, 425 or Fig. #26 is normally comecieg suits nt The output of fate thede along with other gale protecting Capability of Sawai ECT The resistor Ry in Fig. 427a increases Or ding and latching. ; fr ; lat cea reduces the turn-off time, and ine re quen y noise compo- currents. The capacitor Gy in Fig, 427b or lay time. The diode D, in Tents and increases dv/d? capability_and_gate Beever, for asymmetrical Fig. 4-27c protects the gate from negative voltage. te voltage to improve the SCRs, it is desirable to have some amount of Degalive Bate ol an be “doldt-capability and also to reduce the turn-off time. hee pulsed meee as shown fa Fig. 4-27d, where diode D, allows only the positive pt i d Timi current. and Rj damps out any transient oscillation and Timits the gate curre 4-12 UNWUNCTION TRANSISTOR The unijunction transistor (UJT) is commonly used for generating trigwer; nals for SCRs. A basic UST-triggering circuit is shown in Fig. 4.28, A Udy “Three terminals, called the emitter E, base-one B,, and ba: “two By. Between B, and B: the unijunction has the characteristics of an ordinary resistance. This resistance is the interbase resistance Rg» and has values. in the range 4.7 to 9.1 KO. The static characteristics of a UJT are shown in Fig. 4-28b. ” a hen the de supply voltage V, is applied, the capacitor ig charge resistor R since the emitter circuit of the UJT is in the open state. eee constant of the charging circuit is 7, = RC. When the emitter }, the same as the capacitor voltage Uc, reaches the Peak voli on and capacitor C will discharge through Ra at a rate constant 12 = RyiC. 7 is much smaller than 7). 4\ decays to the valley point V,, the emitter ceases t u and the charging cycle is repeated. The waveform, Iv voltages are shown in Fig. 4-28c. The waveform of the triggering voltage Van is identiogl current of capacitor C;, The triggering voltage. y, sig- has T voltage Ve, which is tage V,. the UIT turns ae determined by the time hen the emitter voltage Ve ‘© conduct, the UT. turns off, 8 of the emitter and triggering to the discharging designed to be ‘m Should be(a) Circuit {c) Waveforms Ve 4 Cutoff _ | Negative Saturation, region eeaion region Ve Peak point / Ves = 10V > ~ Valley point eN - Ve isat) Ww (b) Static characteristics Figure 4-28 UIT triggering circuit. sufficiently large to turn on the SCR. The period of oscillation, 7, is fairly inde-— pendent of the de stipply voltage V,, and is given by (4-23) oan i or Sec. 4-12 Unijunction Transistor Tat¢ value of 7 lies oe tio. Thi where the parameter 7 is called the intrinsic stand-off ratio. ~ between 0. nd 3MQ. The upper limit on i v V, intersects the R is set by the requirement that the load Jine formed by R and WY, Iterscts device characteristics to the right of the peal of he valley int. If the load line fails to pass to the right of ited to a value between 3 kQ al k point but to tt ‘the peak point. the q\ttbAurn on. This condition will be satisfied if Vs ~ ,R > Vo- That ls. -V, (4-24) acct ( ton At the valley point Jj. = Jy and Vz = V, so that the condition for the lower limit R to ensure turning off is V, ~ 1.R < Ve. That is, off is Vy ~ JR < Ves The recommended range of supply voltage V, is from 10 to 35 V. For fixed values of », the peak voltage V, will vary with the voltage between the two bases, Van- V, is given by a V, = Van + Vol= 0.5 V) ~ nV, + Vo(= 0.5 V) (4-26) iode forward voltage drop. The width t, of triggering pulse where Vp is the o1 is (4-27) In general, Rar is limited to a value below 100 0, although values up to 2 or 3. kQ are possible in some applications. A resistor Rm is generally connected in Example 4-5 Design the triggering circuit of Fig. 4-28a. The parameters of the U)T are Wo 51, fp = 10 WA, Vp = 3.5 Vand f, = 10 mA. The frequency ofo Ue Bows ‘f= 60 Hz, and the width of the triggering pulse is t, = $0 ps scillation is Solution T= I/f = 160 Hz = 16.67 ms. From Eq. (4-26), y., 158 V. Let C= 0.5 uF. From Eqs. (424) and (425), the lieing vase Rare o 30 - 15.8 are 10 BA fo-3.5 Ro Ama 265 KO R< 42 MO. From Eq. (4-23), 16.67 ms = R x 0.5 wF x In[1/(1 ~ 3), 0. a Which falls within the limiting values. The peak gar. 2); Which gives R = 46.7 kQ, Bate voltage Vay = V, = 15.8 V. epee Thyristors Chap. 4From Eq. (4-27), From Eq. (4-28), - pete 0151522530 aac 4:13 PROGRAMMABLE UNNJUNCTION TRANSISTOR | / | Laasd se The Programmable unijunction transistor (PUT) is a small thyristor shown in Fig. 4-29a. A PUT can be used as a relaxation oscillator as shown in Fig, 4-29b. The gate voltage Vg is maintained from the supply by the resistor divider Ry and Rz, and determines the peak point voltage V,. In the case of the UJT, V» is fixed for a device by the de supply voltage. But V, of a PUT can be varied by varying the resistor divider R; and Ry. If the anode voltage V, is less than the gate voltage Vg, the device will remain in’its off-state. If V4 exceeds the gate voltage by one diode forward voltage Vp, the peak point is reached and the device turns on. The peak current /, and the valley point current J, both depend on the equivalent impedance on the gate Rg = RiR/(Ri + R2) and the de supply voltage V,. In general, R, is limited to a value below 100 2. V, is given by (4-29) which gives the intrinsic ratio as Vp ___Ra "=v" R+R (4-30) +V5 Anode Gate Anode + PUT Cathode {a} Symbol (b) Circuit Figure 4-29 PUT triggering circuit Sec. 4-13 r injunction Tre eeRand C control the frequency along with R, and Ro. The period of oscillation 7 is given approximately by R? ! = 4. T= zm RCIn Gy, Rc in (1 + F) (431) The gate current Ig at the valley point is given by Vs Ig=(1- D Re (4-32) where Rg = R,R,/(R, + R2). Ry and R; can be found from (4-33) (4-34) Example 4-6 Design the triggering circuit of Fig. 4-29b. The parameters of the PUT are V, = 30 V and Ig = 1 mA. The frequency of oscillation is f = 60 Hz. The pulse width is t, = 50 us, and the peak triggering voltage is Vmx = 10 V. Solution T = 1/60 Hz = 16.67 ms. The peak triggering voltage Vex = V> = 10V. Let C = 0.5 uF. From Eq. (4-27), Ry = t,/C = 50 us/0.5 uF = 100.0. From Eq. (4-30), = V/V, = 10/30 = 1/3. From Eq. (4-31), 16.67 ms = R x 0.5 uF x 4In{30/(30 — 10)], which gives R = 82.2 k9. For Ig = 1 mA, Eq, (4-32) gives Re = (1 ~ ) x 30/1 mA = 20k. From Eq. (4-33), R= Fe ~ 2010 x3 = Kn From Eq. (4-34), = 20k0 x3 = 30K 4-14 SPICE THYRISTOR MODEL Let us assume that the thyristor as shown in Fig, 4-30a is supply. This thyristor should exhibit the following characterien > TO™ a” 2 1. It should switch to the on-state with the application ses voltage, provided that the anode-to-cathode voltage Fe pct postive gate 2, It should remain in the on-state as long as the anode current flows 3. It should switch to the off-state when the anod toward the negative di © Current goes through zero ‘The switching action of the thyristor can be modeled bi switch and a polynomial current source [14]. This is shown in we sso oes turn-on process an be explained by the following step eee rr 124Chapter 3. Thyristors 125 500 A. So. fi = 450 A. Hence from the above equation we get 1+(1.05 x 1073 x 450) + 450R = 0; (0.85 x 107? x 500) +500R solving for R we get pa 14725 - 1.325 S00 459 = 2-952 3.12. Thyristor Firing Circuits In the following sections we discuss about some simple thyristor triggering circuits which may be used in single-phase rectifiers and ACVCs. These circuits are not sophisticated and do not give excellent performance. But still they give some elementary ideas for a novice reader about generating triggering pulses to turn ON a thyristor. R Load v=v,,sinor Figure 3.17.: R firing circuit. | S21. ReFiring Circuit i i i fier. This is | ewe 3.17 shows the R firing circuit used ina single-phase half-wave controlled recifer. Be be simplest triggering circuit. In this circuit the turn-ON will be ‘slow and i bed ety - 0 Voltage, nor will it extend beyond the supply voltage maximum (nm ee Varied to vary the firing angle of the thyristor. Rs is the stabilizing "S/Na ch 126 Power Electronics : A Simplified Approa current should not exc | zero, gate current is limited by the resistance Ri. ™ ae a ced may permissible gate value Ioy.-Bs can therefore be found fro Riz Vn "= Tow d M Vin i — region ' wy - ' Peak Point 1 1 ' ' ' | Valley Point ' —132 Power Electronics : A Simplified Approach (a) (b) Figure 3.25,: UJT relaxation oscillator circuit. where = Rin /(Rmi + Raa) = Roi /Raw is called inyrinsic standoff ratio. The value of 7 lies between 0.51 and 0.82. As long as Ve is less than Vp , the peak voltage, the p-n junction is reverse biased id emi rent is negative dnd very small'of the order of few wA. This is indicated as Igo in Figure 3.24 . The peak voltage is given by Vp = Vip + Vy 3.30) where V, is the cut-in voltage of the diode which is around 0.6 V at room temperature. When Vs becomes equal to Vp the diode starts conducting, /¢ increases, and suddenly Rp; drops. Due to this. Ve suddenly drops to the value Vy , i.e., valley voltage. Typical value of Vy is around 2 V, Further increase in Vz causes increase in Jy. The maximum limit for emitter current is typically around 50 mA as shown in Figure 3.24. The negative resistance characteristic of UJT is used to generale sharp pulses to trigger SCRs — Figure 3.25 shows UJT relaxation oscillator and associated waveforms, When DC supply V is applied in the circuit of Figure 3.25-(a), the capacitor C is charges through R at a rate determined bY the time constant t) = RC. When the emitter voltage Vs — which is same as the capacitor volta8? = Teaches the value Vp , the UJT turns ON and the capacitor C will discharge through Ry at a1 Se by the time constant t = RiC . This causes a sharp pulse of voltage across Ri - This ‘Sed to trigger an SCR. t) is much smaller than t). When the Vg drops down to theChapter 3. Thyristors 133 valley point Vy , the emitter ceases to conduct Fou. {, and the charging cycle is repeated. The period of - oscillation, T is fairly independent of the DC supply voltage V, and is given by when a (3.31) Ry is connected for thermal stability of Vp . Its value is given approximately by R= (3.32) Ww The maximum and minimum values of resistanc € Ry namely Rae and Ryn in the relaxation oscil- lator circuit of Figure 3.25 are given by Vee Brae = ve and Rin “eh 6.33) With the emitter of the UJT open, we have Vag = Leakage current x (Ry +R2+Rgp) Therefore, we have v R= Teakage came ~*~ Row (3.34) The voltage across Rj is used to trigger an SCR. The resistance Rj should be such that the normal leakage current drop across R; when the emitter is kept open should not cause undesirable turn-ON of the SCR. Therefore, we also have VepRi BB cy, Ri +R2.+Rep FF. G35) Where Ver is the minimum gate voltage required to trigger the SCR. Typically, R is in the range 3kQ to 3 MQ and R; is about 100 Q. For proper triggering of SCR, gate pulse should be applied When the SCR is forward biased. The firing angle of SCR should be measured from zero crossing of AC supply voltage. This synchronism is achieved using the circuit shown in Figure 3.26 on the Next page. In this circuit, the bridge rectifier is supplied from the same AC source that is given to the R to be triggered. The zener diode causes a constant voltage V; to be applied to the relaxation Sscillator circuit during every half-cycle of the AC supply voltage. The frequency of triggering Pulses can be varied by operating the potentiometer R. This causes variation of the firing angle of the SCR. The pulse transformer is provided in order to isolate the gate it from the power Stcuit. This isolation is essential in case of ACVC built using two SCRs in anti-parallel. Two “ondaries are provided in the pulse transformer to trigger two SCRs, The waveforms at different Points in the circuit of Figure 3.26 are shown in Figure 3.27 on page 135.134 Power Electronics : A Simplified Approach Pulse Transformer Figure 3.26.: Line synchronized UST triggering circuit. Example 3-19 Design a UST relaxation oscillator for triggering a thyristor. The UST has the following parameters: 1 = 0.72, Ip = 60 nA, V, = 2.5 V, . =4 mA, V = 15 V, and Rag = 5 kQ. The leakage current with emitter open is 3 mA. The triggering frequency is 1 kHz and Ve{min) = 0.3 V. Also calculate the minimum and maximum values of triggering frequency. » Solution Assume C = 0.05 nF arbitrarily. Given that triggering frequency is T = 1/f = 1/1000 = 1 ms. The value of R given by Eq. (3.31) is T 10-3 = cin( 5) 0.05 x 10-6 x In ($33) mike Rp given by Eq, (3.32) is 104 104 Ree ay = aig 725932 The minimum voltage across the gate occurs when the UJT is OFF. Taking this condition, we £ Vein 03 R= fe) 0S" "= Leakage current ~ 3x 19-3 ~ 100%135 Chapter 3. Thyristors or o Figure 3,27.: Waveforms in the UIT firing circuit. ee ee136 Power Electronics : A Simplified Approach Taking V, = 0.6 V, from Eq, (3.30) we get V, = (0.72715) +0.6=114V From Eq, (3.33) we get 15-114 15-25 7 ' = 3.125 kQ Rmor = 5 6OkKQ and Rin = FGA Also, from Eq, (3.31) the minimum and maximum values of frequency are given by 1 I 5 ae —____——- = 261.86 Hz, Sein Rn n(n) 60 «103 0.05 ¥ 10-6 In (yy73 1 Sina : : - 5.03 kHz, 25 x 10° «0.05 x 10-6 In(;-h55) min Rimi In Sree Design a UST firing circuit using an UST having the parameters: 1) = 0.66, Ip = 25 wA, Vo = 2.5, 1, = 10 mA, V = 25 V. The frequency of oscillation is $00 Hz and the width of the triggering pulse is 10 us. >» Solution The period of triggering pulses T = 1/f = 1/500 = 2 ms. Assume C = 0.1 nF. From Eq. 3.31) we get 2x 103 ——___—_—_. = 18.54 k: 0.1 «10° xin (Gy 8.54% From Eq. (3.30) we get Vp = WV + Vy= (0.66 x 25) +0.6 = 17.1 V Now let us check whether the value of R calculated above lies within the limiting values. Rmx = at =316KQ and —-Rmin = wae =2.25k2 Therefore, the required value of R lies within the limits. We also have from Eq. (3.32) Ra casos NV 0.66 x 25 ° and since the width of the triggering pulse is about 5RiC we have py = Nidthof triggering pulse 1010-8 pant 5c ~5x0.1x 10-6 ~Chapter 3. Thyristors 137 312.4. Op-amp Firing Circuit for Single-phase Controlled Rectifiers and AC Voltage Controllers Figure 3.28 shows a single-phase triggering circuit for triggering thyristors in single-phase ac con- rollers and controlled rectifies. The synchronizing signal is taken from the same source from which the thyristor power circuit is fed. This signal is given to the zero crossing detector (ZCD). ‘The square wave signal A obtained from the ZCD is converted into a ramp signal B using an inte- grator. This signal is level shifted using an adder to obtain C. C is compared with an adjustable de oltage D to obtain E which is limited by a zener so that it is TTL compatible. The pulses at F are used to trigger a monostable which gives complementary ouiputs G and H. The pulse widths of G and H are adjusted to be exactly equal to haif- e inusoidal supply voltage (10 ms for 50 Hz and 16.667 ms for 60 Hz). These are ANDed with a high frequency (typi pulse Med pee train I to obtain GI and HL. 2 4 JAE Gand H are complements Syne to each other signal Mono stable |_H. Hm Astable ‘Comparator pone Integrator Monostable gives 1/2 cycle pulses. Astable gives pulse train typically at 10 kHz. Figure 3.28.: Op-amp thyristor firing circuit. _The signals available at GI and HI are then fed to their respective pulse amplifier circuits. This “treuit is shown for G1 in Figure 3.29 on the jiext page. The pulse transformer is connected in Collector circuit of the transistor with a freewheeling diode across it. This diode protects the - sonst azaint large reverse voltages. To protect the gate of the thyristor against large reverse | the 18°: a diode is placed across the secondgry of the pulse transformer. The diode in series Wi | “Sate prevents any reverse current flowing/from the gate during the conduction of the thyristor. erse current flowing ring th ai138 Power Electronics : A Simplified Approach The capacitor atthe secondary ofthe pulse transformer prevents any spurious high frequency yj, from triggering the thyristor. Figure 3.30 on the facing page shows waveforms at different poiny this firing circuit. +Voc SCR to be triggered Gl Pulse amplifier with pulse transformer 4 Similar circuit is used for H1 also. Figure 3.29.: Pulse amplifier circuit. 3.12.5. Triggering Circuit for Single-phase Inverter Circuit Figure 3.31 shows the block diagram of a firing circuit for triggering thyristors in a single-phase inverter. This circuit makes use of an astable and logic gates. The frequency of operation of te inverter can be controlled by the astable signal output, Pulse train generator is also an astable. But it is designed to output sharp pulses at typically about 10 kHz. A transistor pulse amplifier circuit similar to the one shown in Figure 3.29 is used to amplify the triggering pulses available at Gl and HI so as to trigger the thyristors reliably. The pulse transformers provide an i the low power triggering cir ferent points in the circuit. ation betweet uit and the main power circuit. Figure 3.32 shows the waveforms t tal triggering circuit wh used to trigger thyristors in a single-phaSmewoltage controller or cont This ¢ makes use of digital circuits instead of op-amps> r ye counter preset to the decimal equivalent of the n-bit preset Bjnary inpu ECA Each zero crossité “of the synchronizing signal. Typically, the counter dan be of mod-18-with four bits and the lO frequency can be so adjusted as to produce 16 coun in a half-cycle of the supply voltage:Chapter 3, Thyristors igure 3.28. ints in Figure 3. he Fi Wi ferent points in : forms at diffe ~* Figure 3.30.: Wave! 139140 Power Electronics : A Simplified Approach Astable Pulse Train Generator B 10 kHz Figure 3.31.: Thyristor triggering circuit for single-phase inverters. A 0 or A ™ pr an 7 mm or Gl o HI © nm or m Qn i Figure 3.32.: Waveforms pertaining to the circuit of Figure 3.31.Chapter 3, Thyristors M41 zep |e Synchronizing | Hatl-eycle Signal Detector A +>. Reset Load Enable Reset : B a bit Set =| c Oscillator abit Flip FI Logic Clock | Counter [Ge] PFO | ireui flow B LS Preset Input —— Synchronizing signal is taken from the same Stage source which is supplying the power circuit. LI Carrier frequency signal generator is an astable : typically operating at 10 kHz. io oe Driver stage consists of a pulse amplifier and pulse transformer_ Logic circuit for each thyristor is shown below A_I Carri e farrier Modulation To Thyristor and Driver Ti Stage wl >t w >I |» [ and Driver T2 Stage ap Carrier Modulation To Thyristor Figure 3.33.: Digital triggering circuit.142 Power Syne signal lectronics : A Simplified Approach ZCD 4 ' ' ' output Counter 4 Overflow fj With i X=0 ) With X=1) 4 ——_}—_——> 0 ‘hon i” [at [-1=tat 7 “__—_— ee Figure 3.34.: Waveforms in digital triggering circuit of Figure 3.33.Chapter 3. Thyristors 143 counter startscounting down at the rate of clock signal produced by the oscillator, When the counter reaches 2e70, the overflow signal is output by the counter. This signal sets the flip-flop which in tum disables the counter. The flip-flop outputs along with the signals coming from the half-cycle detector. and the selector signal X is processed through at logic circuit and a driver stage to trigger the thyristors. When X = 0 the pulse duration is from ot to m. This is preferable for a cont restifier. When X= 1 the pulse duration is trom a to +a. This is preferable for an ac vo controller. Figure 3.34 shows the waveforms at different points in the circuit of Figure 3 Let the counter be down-counting. If the counter has n-bits, then it has 2* possible states. Let the clock signal frequency be adjusted to give in one half cycle or 180°, Then, for any preset decimal value NV’ of the counter. the delay angle & which corresponds to the instant when the overflow signal becomes active when the & 5 x 180° Nv a é This shows that the higher the initial preset value NV’, more close will be the delay angle to 180°. Nel6, we 1 oh Summary = ae (Ne orenaec ee * Now-a-days when we use the term ‘thyristor’, we are referring mostly to SCR. _— * According to two transistor model of an SCR, to turn ON the device we should make (0 - 0) + 1. To turn OFF we should make (% +c) + 0. * Factors causing tum ON of an SCR are: high temperature, high dv/df, gate current, high forward voltage, light radiation. * The turn-on time of an SCR is given by fon =ta+t,. * After the thyristor turns ON the gate signal should be removed. If it is continuously applied it increases the gate power loss. * When the thyristor is reverse biased the gate signal should not be applied as otherwise the thyristor may fail due to an increased leakage current. * The width of the gate pulse should be longer than the time required for the anode current ‘0 rise to the latching value /,. Otherwise the thyristor will turn OFF once the gate pulse is Temoved. * The SCR turn-oFF time is defined as loff fret byes * The duration for which reverse voltage appears across the SCR after its anode current has become zero is known as circuit turn OFF time f,.