library IEEE;

use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;

entity black is
port(
iG, iG1, iP, iP1 : in STD_LOGIC;
oG, oP : out STD_LOGIC
);
end;

architecture rtl of black is

begin
oG <= iG or (iP and iG1);
oP <= iP and iP1;
end;