library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity decadecnter is
port(clk,rst:in std_logic;
q:out std_logic_vector(3 downto 0));
end decadecnter;

architecture Behavioral of decadecnter is

signal ch:std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if rst='1' or ch="1010" then ch<="0000";
elsif(clk' event and clk='1') then
ch<=ch+"0001";
end if;
end process;
q<=ch;

end Behavioral;