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    Clock IC pin configuration

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    mm5309-5311-5312-5313-5314-5315

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    Clock IC pin configuration

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    8 views7 pages

    mm5309 5311 5312 5313 5314 5315

    Uploaded by

    dnyanesh
    Clock IC pin configuration

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    of 7
    National % L4 Semiconductor aa Digital Clocks J ‘MM5309, ‘MM5311, MMS312, MM5313, MM5314,/MM5315 Digital Clo General Description 7 The dtl docks oe monotie MOS sepratd Circuits vtlelng Pchannel tw trvedoldsethorereene nod an tr plate. dopeen Soh Geren re Gover pron a te lots tera Sale vee typeof coca. Two dilay moses or age) fetta epic eis of sored soporte Tre cheue iets e CED tod ya duces nae ‘nin mininal eiiond conponns, and rear finegt powe ninety. The tnkeeie neon Conran tram hr 860 or 80 He npun ta et Play fomet roy be ster 12 Rous ft nga Stauing) or 28 hur: Outs const of motigena display drives (BCD and 7-segment) and digit enables. ‘he vies cperae crt & pom ply tape ot TY {2°10 and do nat ree steps sap Toe lok packaged data sao Features = 50 or 60 Hz operation 12 oF 24-hour display format cks 1 Leading-zero blanking (12shour format) = segment outputs ingle power supply '= Fast and slow set controls 1 Internat multiplex oscillator * For features of individual clocks, see Table 1 Applications © Desk clocks © Automobile clocks 1 Industrial clocks = Interval Timers Taste a BED Outs x x x x x 8.9% Dply Mode |x x x x x Hols Coun Cont x x x x The Oso x x ‘uroutEnaie contol | x. x x Ret x x Connection Diagrams (oua!-in-tine Packages) Ye }eemenane Peer ema [2eurmawe vs nba masse j/ Onto Numba MMs311N ‘See Package 23 "See Pochage 23 543 3 SLESWWIN ‘VLESWIN ‘CLESIIN ‘ZLESININ ‘LLESIWIN ‘GOSSINIA MM5309, MM5311, MIM5312, MIM6313, MM5314, MM5315 Re mene Eee Absolute Maximum Ratings ‘Voltage at Any Pin * Vgg + 0.3 to Vgg -,20V. Operating Temperature 25°C to +70°C Storage Temperature “1 Hae Lead Temperature (Soletng, 1 seconds) 300°C Electrical Characteristics 1 within operating range, Vsg = 11V to 19V, Vp = OV, unless otherwise specified. PARAMETER CONDITIONS: MIN tye [Max | units Power Supply Voltage Vss (Vo =v) n 19 v Power Supply Current Vg = 14V, (No Output Loads) 10 ma 50/60 He Input Frequency ee | soore0 | 6a He 160/60 H Input Voltage Logical High Level vss-1 | vss Vss v Logical Low Level Yoo | Yop | vss-10 v Multiplex Frequency Determined by External R & C or00 | 10 60 ke All Logic Inputs Driven by External Timebase ae 60 kite Logical High Level Internal Depletion Device to Vs Vss-1 | vss Vss v Logica! Low Level Yoo | voo | Vss-10 v BCD and 7-Segment Outputs Logical High Level Loaded 2&2 to Vo 20 20 |mAsource Logical Low Level 0.01 |mA source Digital Enabte Outputs LLovicl High Level 03 | mA source Logical Low Level Loaded 100 9 to Vss 50 25 mAsink Connection Diagrams (ont) pual-in-Line Packages (Top Views) Ordeg Number wmgain (| ‘Order Namiber MMS313N ‘See Pachage 22 “See Package 23, “=f Pens / sooner { ‘Order Number Maran ~/ ‘Order Nomber MMEDISN ‘See Package 22 "See Package 22 a4 LEME Et Functional Description ‘A block diagram of the MMS309 digital clock is shown in Figure 1. M5311, MMB312, M5313, MMB314 and MMB315 clocks are bonding options of MM5309 clock. Table 1 shows the pin-outs for these clocks [50 oF 60 Hz Input: This input is applied to a Schmitt ‘Trigger shaping circuit which provides approximately BV of hysteresis and allows using a filtered sinewave ingut. A simple RC filter sich at shown in Figure 10 should be used to remove possible line voltage transionts that could either cause the clock to gain time or damage the device. The shaper outpat drives counter chi which performs the timekeeping function. 50 or 60 Hz Select Input: This input programs the Prescale counter to divide by either 60 or 60 to obtain @ 1 Hz timebase, The counter is programmed for 60 Hz ‘operation by connecting this input to Vo. An internal Sepletion device is common to this pin; simply leaving this input unconnected programs the clock for 50 Hz ‘operation. As shown in Figure 7, the prescale counter Provides both 1 Hz and 10 Hz signals, which can be brought out at bonding options ‘Time Setting Inputs: Both fast and slow setting inputs, 42 well 35 2 hold input, are provided. Internal depletion evicés provide the “normal timekeeping function. ‘Switching any of these inputs (one at 8 time) to VoD results in the desired time setting function, ‘The three gates in the counter chain (Figure 1) are Used for setting time. During normal operation, gate A ‘connects the shaper output to a prescale counter (#50 ‘oF +60); getes B and C cascade the remaining counters. Gate A ‘is used to inhibit the input to the counters for the duration of slow, fart or hold time-setting input ‘activity. Gate B is used to connect the shaper output directly to a seconds counter (60), the condition for slow advance. Likewise, gate C connects the shaper output directly to a minutes counter (#80) for fast advance. Fast set then, advances hours information at one hour per second and slow set advances minutes information at one minute per second, 12 or 24-Hour Select Input: This input is used to pro- gram the hours counter to divide by either 12 oF 24, thereby providing the desired display format. The Y2hour display format is selected by connecting this input to Vpp: leaving the input unconnected (internal ‘depletion device) selects the 24-hour format. Output Multiplexer Operation: The seconds, minutes, and hours counters continuously reflect the time of day. Outputs from each counter {indicative of both units and tens of s#conds, minutes, and hours) are time: division multiplexed to provide digit sequential access to the time data. Thus, instead of requiring 42 leads to interconnect 2 6-digit clock and its display (7 segments, per digit), only 13 output leads are required. The mult plexer is addressed by a multiplex divider decoder, Which is driven by a multiplex oscillator. The oscillator ‘and external timing components set the frequency of ‘the multiplexing funetion and, as controlled by the 4 oF select input, the divider determines whether deta will be output for 4 or 6 digits. A zero-blanking circuft suppresses the zero that would otherwise sometimes ‘appear in the tens-of-hours display; blanking is fective only in the 12hour format. The muttiplexer addresses ‘also become the display digitenable outputs. The multi- plexer outputs are applied 10 a decoder which is used © address a programmable (code converting) ROM, ‘This ROM generates the final output codes, Le., {and Z-sogment. The sequential output: order is from digit 6 (unit seconds) through digit 1 (tens of hours) Mattiplex Timing Input: The multiplex oscillator is shown in Figure 2. Adding an external resistor and capacitor to this circuit via the multiplex timing input {as shown in Figure 4a) produces a relaxation oxiliator. ‘The waveform at this input is a quasi-sawtooth thet is squared by the shaping action of the Schmitt Trigger in Figure 2. Figure 3 provides guidelines for selecting the ‘external components relative to desired multiplex ‘frequency, Figure 4 also illustrates two methods of synchronizing ‘the multiplex oscillator to an external timebase. The ‘external RC timing components may be omitted'and ‘this input may, be driven by an external timebase; the required logic levels are the same as 60 of 60 Hz input. Reset: Applying Vp to this input resets the counters ‘to 0:00:00.00 In 12:hour format and 00:00:00.00 in 24-hour formats leaving the input unconnected {internal depletion pull-up) selects normal operation. Proper reset will be ensured when VDD to Vsg slew rate is ‘no faster than one volt per microsscond. This can bbe accomplished with a capacitor fram the reset input to Vss. 4 oF G-Digit Select Input: Like the other control inputs, this input is provided with an intemal depletion pull-up device. With no input connection the clock outputs data for 2 4-digit display. Applying Vpp to this input.pro- vides « 6igit display. Qutput Enable Input: With this pin unconnected the ECD and 7-seqment outputs are enabled (via an internal

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