Pulsed PMOS Sense Amplifier for High Speed Single-Ended SRAM Juhyun Park, Hanwool Jeong, and Seong-Ook Jung Dept. of Blectrical and Electronic Engineering Yonsei University, Seoul, Korea {pnaynh, hanwool87, sjung}@yonset.ac. kr Abstract In this paper, a pulsed pMOS sense amplifier for single-ended static random access memory (SRAM) at low stpply voltage is proposed. Domino logic for single-ended SRAM such as 8T SRAM has a large read delay because a large read bitline swing is required To improve read delay, previously ‘proposed pseudo nMOS based sense amplifier was ‘proposed However, it has a large static current, which causes a lenge energy consiamption With 22- 1m FinFET technology, the proposed pulsed pMOS sense amplifier improves read delay by about 80% compared with conventional domino logic and rechices energy constmption by 40% compared with previously proposed pseudo nMOS based sence ‘amplifier Keywords: ST SRAM, sense amplifier, single-ended reed operation 1. Introduction Inecent years, the battery-operated devices such, as implantable medical and wearable devices are proliferated, which increases the demand for a low- energy system on chip (SoC). Reducing supply voltage (Vinx) is the efficient method for decreasing, energy consumption [1]. However, reducing Vip degrades yield of circuit operation due to increasing threshold voltege (V's) variation Especially, in the satic random eccess memory (SRAM), this degradation is serious because SRAM consists the small szed transistors which have a larger Va, varistion by Pelgram’s law. Thus, in low Vo, to improve SRAM operation yield, ST SRAM bitcell ‘based on [2] is used instead of the conventional 6T SRAM biteel. ST SRAM bitcell uses « one read bitline (RBL) for read operation, which is called as « single-ended, read operation The single-ended read operation is classified into read ‘0’ and ‘I’ operations, as shown in Fig 1. During read ‘0° operation, pre-charged, RBL is discharged by bitcell. Dusing read ‘1’ operation, RBL is maintained to pre-charged level Thus during reed operation, read bitline is not Fig. 1. (a) Read SRAM Ditcell. © Fig. 2. (a) Domine logic, (b) pseude nMOS logics, and (c) pseude nMOS logic with clock. discharged st all times which can reduce energy consumption However, for read ‘O° operation, large billine swing is required which significently degrades «read delay. In low Vp region, the degradation of read delay is serious due to alarge Via, varietion To mitigate degradation of read delay in ST SRAM, a small cell per bitline (CpBL) has been used, which causes @ small density.oie @ @) Fig. 3. Previously preposed pseudo nMOS based sense amplifier. (a) Structure and (6) waveforms, Fig. 4, Proposed pulsed pMOS sense amplifier. To improve reed delay in [3], pseudo nMOS based sense amplifier for single-ended SRAM was previously proposed However, this sense amplifier has a large static current, which causes a lerge energy consumption In this paper, to resolve read speed problem of single-ended reed operation and energy problem of the pseutlo nMOS based sense amplifier, ‘pulsed pMOS sense amplifier is proposed. 2. Previously Proposed Pseudo NMOS Based Sense Amplifier For sensing RBL state duwing read ‘0’ and ‘1” operations, domino logic has been used as shown in Fig 2(@). Dung read ‘I’ operation RBL is maintained to Vip. Thus, OUT node voltage keeps its pre-discharged level. During read ‘0’ operation, RBL is dischuged by bitcell. When RBL is discharged from Van to VopiVard, OUT node voltage is slowly charged because Mpg is operated at sub-Vth region When RBL becomes below Vinx Varo, OUT node voltage is remerkebly charged. However, because RBL node capacitance is lage due to the lerge number of biteell on RBL end long RBL wire, the time thet RBL is discharged to below VanlV ago is large, which degrades read delay. In [3], pseudo nMOS is used to improve read. delay, as shown in Fig 2(t). Mepis fully tumed on because initial condition of RBL is Von Thus as soon as RBL is discharged current of Myo is significantly charged, which quickly changes OUT IsAE=1 ro. sao RaL= tow Isat frev= tow Fig, 5. Process of read ‘0’ operation in proposed pulsed pMOS sense amplifier. sao rac not Fig. 6. Process of read ‘1’ operation in proposed pulsed pMOS sense amplifier. node voltage to high voltage. To prevent static cuent between My and Men, Mpg is tuned off duing pre-charge phase, as shown in Fig 2(6) Although Mpy is tuned off during pre-charge phase,Table 1: Tésny So and energy comparison Voor 5V Conventional domino logic Previoudy proposed ‘AMOS based sense emplifier Tease | Energy 19ine | 9608 o73ns | 14458 ) Fig, 7. Pulsed SAEB signal generate: wasteful cumrent is ocewred duing read ‘0’ and ‘1” operstions because RBL is dowly tuned off duing read ‘0" operation and RBL is kept near Vin during, read ‘I’ operation, which causes a large energy consumption To seduce wasteful current, pseudo nMOS based sense amplifier was previously proposed, es shown in Fig 3. This structtwe uses delay clock signal to eliminate a static cwrent during read ‘1” operation However, static cwrent is sill occured during read, ‘” operstion due to dowly discharged RBL node voltege. In addition, timing margin between delayed clock end original clock signals is required to increases OUT node voltage duing seed “0” operstion It occws static curent before delayed clock is developed dusing ead ‘I’ operation 3. Proposed Pulsed PMOS Amplifier Sense To resolve the energy consumption problem in the previous pseudo nMOS based sense amplifier, pulsed MOS sense amplifier is proposed, as shown in Fig. 4. The proposed structure uses short pulse SAEB sSgnal to prevent static cuxrent from Meu to Mp. ‘Process of reed ‘0’ operation is divided into three phases, as shown in Fig 5. In phase 1 duing read, ‘0’ operation, RBL is discharged by ensbling RWL and then RWL is disabled after sufficient RBL development In phase 2, SAEB signal becomes shortly low, which causes charging OUT node valtege. Charged OUT node enables keeper. In phase 3, SAEB signal is disebled Although Mpg is tumed, off, OUT node voltage can be kept Vim by feedback of keeper Process of reed ‘I’ operation is divided into three phases, as shownin Fig 6. In phase 1 duwing read ‘1’ operation, RBL is maintained to pre-charged level. In phase 2, SAEB signal becomes shortly low. Although, Mpy is tumed on ty SAEB sg, OUT Proposed pulsed MOS sense emplifier 038m: | 8608 node voltage cannot be raised due to week Mro, which keeps PUB Vip In phase 3, SAEB signal is, disabled, which cen reduce static current from Meg to Mm 4. Pulsed SAEB Signal Generator SAEB signal has to become low after RBL is sufficiently dkscharged to tum off Men which cen increase OUT node voltage by week Merv duing reed ‘O° operation Thus, a sufficient time (Tema) from ‘when clock is enabled to when SAEB signal becomes low is required For measwing Tams, Moy gate is controlled by clock instead of SAEB and then time from when RWL is enabled to when OUT node is developed (Toon) is measwed To consider the worst case, the 5a worst time of Toon (Toons) if meanwed In addition, « sufficient tine (Tpy) efter SAEB becomes low is requised to increase OUT node. For messing Try, time thet OUT node is increesed after Tama (Toon) is meeswed To consider the worst case, the 50 worst time of Toon (Toon, +) is measured. Fig 7 shows the pulsed SAEB signel generator. Delay of path 1 and path 2 is defined as Tyan and Tyas, respectively. For meaning Tama end Toy, the following conditions have tobe setisfied. Tass = Tyan =Toomase 1) Pew = Tyan ~ Tat = Tour sse ©) By the vasistion of pulsed SAEB signa generation circuit, the worst case of Tyaat and Tess has to be considered. Thus, the following concitions hhave to be satisfied. Tyati,-se 2 Toms. @ (yaa ~ Tyaas)-se =Tourasse 4) To minimize delay and energy consumption, ‘Teexse and Tew have to be minimized Thus, Tse and Tew are determined es follows Tams = Tyaanto = Tomsse OD Tow = Fyatsr ~ Tpat)-se = Tourrase O5. Simulation Results In this papes, HSPICE simulation tool with the fitted BSIM model to 22-nm FinFET cheractetistic based on [4] is used to compare bebveen conventional domino logic, previoudy proposed pseudo nMOS based sense amplifier and proposed pulsed pMOS sense amplifier Table | shows read delay and energy comparisons Read delay (Tasig) is defined es time from when, RWL is ensbled to OUT node is developed with, CpBL of 128. To achieve a So target yield, the So worst case Tany (Tatyss) is compared Energy consumption is measwed with one-selected read bitline and sensing circuit during Taayse The proposed pulsed pMOS sense amplifier hes « smaller Tanyse by about 80% than the conventional domino logic sensing ciscuit because the proposed structure requires a sueller read bitline swing then the conventional domino logic sensing circwt, In addition, energy consumption of the proposed sruchue is lower by about 10% due to a small Tatyse Moreover, the proposed structure has a smaller Tusgyse and a lower energy consunption by 48% and 40% then the previously proposed pseudo nMOS based sense amplifier because keeper boosts OUT node developing speed and the proposed sruchwe reduces static current, respectively. 6. Conclusion At low Vip SRAM operation yield with the conventional 6T SRAM is degaded 8T SRAM which has single-ended read operation is used to improve SRAM operation yield at low Von The single-ended operation with domino logic hes sgnificently low delay at low Vinp because a large read bitline sving is required. To improve delay, pseudo nMOS based sense amplifier was previously proposed. However, it has a lege enesgy consumption due to # large static current from Vino to VSS. In this paper, to resolve this problem with high speed, pulsed pMOS sense amplifier is proposed With 22-nm FisFET technology, the proposed sruchwe has a snell read delay by sbout 30% compared with the conventional domino logic end & low energy consumption by 40% compared with the previously proposed pseudo nMOS based sense amplifier. Acknowledgment ‘This work was supparted by the IT R&D program of MOTIE/KEIT. [10052716, Design technology development of ultre-low voltage operating circust andIP for smest sensor SoC] References [JA Teman, L. Pergement, ©. Cohen, and A Fish, “A250 mV 8 kb 40 am ultie-low power 9T supply feedback SRAM (SF-SRAM),” IEEE J. Solid-State Cireuits, vol. 46, no. 11, pp. 2713-2726, Nov. 2011 [2] L. Cheng RK. Montoye, Y. Nakamura, K. A Batson, RJ. Eickemeyer, RH. Dennard, W. Haensch, and D. Jamsek, “An ST-SRAM for varisbility tolerance and low-voltage operation in high performance caches” IEEE J. Solid State Circuits, vol. 43, no. 4, pp. 956-963, Apr 2008 [3] H. Jeong T. Kim, T. Song G. Kim, and S. O. Jung “Pseude NMOS based sense amplifier for high speed single-ended SRAM,” in ICECS 2014, pp. 331-334 [4] C. Auth, et al, “A 22 om high performance and Tow-power CMOS technology festwing fully. depleted ti-gate transistors, self aligned contacts and high density MIM capacitors,” in Proc. Symp. VLST Technol, Jun 2012, pp. 131-132