Pin Details: ADDERS X SUBIRAC TORY 4 } \ Half Adder using basic gates: \ 7486 V | Half Adder a falB[s] 6] sm | cw o/o 0 of1{ijo |Pie/eOu|e1ggO7| r{afofifrea | | 7486LS S-A@B GND S=AB+ AB S=A@OB = AB 1 & @2!Full Adder using basic gates: , 1486 S= ABYC (Aq B) Crt C= (ABB) On + a8 Full Adder A| Bj) Cn-1/S| C/ s(v)| cy) 0/0} 0 jolo 0/0} 1 J1J/0 }0;/1! 0 /1/o 0/1) 1 Jo}1 1/0) 0 /1/0 1/O/ 1 foji 1}/1/ 0 [0/1 1/1} 1 /1}i1 -B yor ariment N ent No ae COUNTERS . Realization of 3-bit counters as a sequential circuit and Mod-N count =~ design (7476, 7490, 74192, 74193). m om Apparatus Required: - IG-7498, IC 7476, 1€-7490, IC 74192, IC 74193, IC 7400, IC 7416; ¥6-7432- ete. Procedure: - 1. Connections are made as per circuit diagram. 2. Clock pulses are applied one by one at tae clock UP and the OP is observed at QA, QB & QC for IC 7476. 3. Truth table is verified. Procedure (IC 74192, IC 74193) made as per the cireuit diagram except the connection 1. Connections are from output of NAND gate to the load input. 2. The data (0011) = 3 is made available at the data Vps A B,C&D respectively. ‘The load pin made low so that the data 0011 appears at QD, QC, QB& QA respectively. put of the NAND gate to the load input. 4. Now connect the out d the truth table 1s verified. Clock pulses are applied to “count up” pin an‘ oO 6. Now apply (1100) = 12 for 12 to 5 counter ard remaining is same as for 3 to 8 counter.4S \ oe Pin Details: - ‘Truth Table iO - Clock | QC | QB | QA | o [ololo 1fotol1 2 [olilo 3 [olili 4 {1fofo 6 [ifo[i 6 [1/1] o Tlafili JL LI J e FL. J 1. Q i | | TT] toa Circuit Diagram: - 3-Bit Asynchronous Up Counter ter vec I + T J x «J oe ° ay ws iw S tAHslEoe tet leo te) Heo Looe Clock WP o ——_Leb oak rye | ae Lhcux a 16 Kg Zh ga 0 nd ue rps a7 7 wy lo a, | lo 7 io BY a? a vec o—— Sit Asynchronous up counter Clock | Qc | QB QA o Tololto 1 [ofofi 2 Tolilo 3 [ol[i[1 . ] | 4[1fopo] “ a L 1 Simi a18/208/ BT 6 [ilile = : - MBSE Be: 8 [ofold]ET CLEAR 1. The asynehranous inputs are inactive and the FF is tree to respond to the J. K. and CLK inputs. in otlot words, the Clocked operation can take place peated and Qs snmnediat atter what conditions Pte JK, and CLK inputs, put Cannot affect the FF while PRESET 0, = PRESET 1 CEEVR 0 The CLEAR is acts tleared te 0 independent of the conditions on the J. K, or CLK inputs The CEA input has no etteer while CLEAR 0. © PRESET TTENR 0 This com ed. and Qs vamedutele m should not be wed because it result in ac ambiguous respo 7 The pin diagram of IC 74192 is same as that of 74193. 74192 can be configured to count between 0 and 9 in either direction. The starting value can be any number between 0 and 9. veco— pt —+4,lBols Jel 1d eux s Keepe *vieecume | & po Ld Qc | Qn] Qa ~ apaya isles) apo a = 1 [oto ofata w {of 1 | "o | oto pa o fo [oO aa afatay « ele 1e| 0)