TMS 9995 16-Bit Microcomputer Data ManualTABLE OF CONTENTS INTRODUCTION 1.1 Description 1.2 Key Features ARCHITECTURE 2.1 Memory Allocation 2.2 TMS 9995 Organization 22.1 Arithmetic Logie Unit 22.2 Internal Registers 23. TMS 9995 Interfaces 23.1 TMS-9995 Memory interface 23.2 TAS.9996 Interrupts 233 Communication Register Unit 234 External Instructions 23.5 TMS.9995 Internal ALU/Other Operation Cycles ‘TMS 9995 PIN DESCRIPTION ‘TMS 9995 INSTRUCTION SET 4. Definition 42° Addeessing Modes 4.2.1. Workspace Register Addresing, 422 — Workspace Register Indivect Addeesing, FL 423 Workspace Register Indiact Auto Increment Addressing, “+ 424 Symbolic (Direct) Addressing, @LABEL 425 Indexed Addressing, BTABLE(R) 42.8 Immediore Addeessing 427 Program Counter Relative Addressing 428 CRU Relative Addressing 4.3. Definition of Terminology 4.4 Status Register Manipulation 45 Instructions 45.1 Dual Operand Instructions with Multinie Addressing for Saurce| and Destination Operand 45.2 Dual Operand Instructions with Multiple Addressing Modes forthe Source ‘Operand and Workspace Register Addressing fr the Destination 4.5.3 Signed Multiply and Divide Instructions 484 Extended Operation {XOP} Instructions 45.5 Single Operand Instructions 458 CRU Multiplesit Instructions 45.7 CRU Single Bit Instructions 45.8 Jump Instructions 45.9 Shift instruction: 45.10 Immediate Register Instructions 45.11 Internal Register Load Immediate Instrctions 45.12 Internal Register Load and Store Instructions 45.13 Return Workspace Pointer (RTWP) Instruction 45.14 External Instructions 45.15 Mic Interrupt Codes 46 Instruction Execution 48.1 Mieroinstrction Cycle 452 Execution Sequence 48:3 Instruction Execution Times SeeeeBREs ~ a 2 «6 45 48 48 a7 a7 a a7 48 4TABLE OF CONTENTS (Concluded) 5. ELECTRICAL CHARACTERISTICS 51 52 53 54 55 56 ‘Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics (Glock Characteristics 5.4.1 Internal Clock Option 54.2 External Clock Option Timing Requirements Switching Characteristics 6 MECHANICAL SPECIFICATIONS Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 4 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 23 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 LIST OF ILLUSTRATIONS Word and Byte Formats ‘TMS 9995 Memory Map ‘TMS 0998 Block Diagram ‘TMS 0995 Flow Chart Status Reajster Bit Assignments Workspace Registers Usable As Index Registers Workspace Pointer and Registers "TMS 9095 Memory Interface ‘TMS 9995 Memory Read Cycle Memory Weite Cycle “TMS 9996 Hold State Decrementer Functional Block Diagram ‘Wait State Generation for External Memory, External CRU Cycles, ‘and External Instruction Cycles : External Circuitry for lavoking/Inhibiting Automatic Fist Wait State Generation Feature ‘TMS 9995 Reset Signal Timing Relationships ‘TMS 9095 Nita Signal Timing Relationships Functional Block Diagram of Internal Interrupt Request Latch TMS 9995 CRU Interface CRU Address Map ‘TMS 9995 CRU Input Cycle ‘TMS 9995 CRU Output Cycle Single Bit CRU Address Development LOCR/STCR Data Transfers Pin Assignments Internal Oscillator External Osilator ‘TMS 9995 Clock Timing ‘TMS 9995 Memory Interface Timing ‘TMS 9995 CRU External Instruction Timing ‘TMS 9995 RESET and NMI Timing ‘TMS 9995 HOLD Timing ‘TMS 9995 Interrupt Input Timing ‘TMS 9996 Event Counter Input Timing Measurement Points for Switching Characteristics Switching Charactorsties Test Load Circuit 54 54 54 54 55 58 55 66 56 6 4 4 7 18 18 20 2 2 2 Py 4 2 55 56 37 59 59 59 60 60Tobie 1 Table2 Tables Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 LIST OF TABLES Dedicated Workspace Registers Interrupt Level Data Flog Register Bit Definitions "TMS 9995 External Instruction Codes ‘TMS 9995 Pin Description Definition of Terminology ‘Status Register Bit Definitions Execution Sequence Example Instruction Execution Times : 5 5 Operation Address Derivation Instruction Execution Time Examples 5 26 28 35 48 52 53uw 12 2a. INTRODUCTION DESCRIPTION ‘The TMS 9995 microcomputer is & single-chip 16bit central processing unit (CPU} with 256 bytes of on-chip random access memory (RAM). A member of the TMS 0900 family of microprocesor and perinheral circuits, the ‘TMS 9995 is fabricated using N-channel silicon gate MOS technology. The rich instruction set of the TMS 9995 is bbased upon a unique memory-tomemory architecture that festures multiple register files resident in memory, Memory-esicent register files allow faster response t interrupts and increased programming flexibility. The incl sion of RAM, timer function, clock generator, interrupt interface, and @ flexible tag register on chip facilitates support of small system implementations All members of the TMS 9900 family of peripheral circuits are compatible with the TMS 9996. Providing @ per formance upgrade to the TMS 9800 microprocessor, the TMS 9995 instruction set isan opeode-compatioie super sot of the TMS 9900 processor family KEY FEATURES © 168itinstwetion word © Momory:to-Memory architecture © 65,536 byte/92,768 word directly addressable memory address space © Minicomputr instruction sot including signed multiply and divide instructions © Multiple 16.word register files Workspaces) resign in memory © 286 bytes of onchip RAM ‘© Separate memory and intercupt bus structures © 8Bit memory data bus © 7 pvortized hardware interrupts © 16 software interrupts (XOPS) © Programmed and DMA 1/0 capability ‘© Serial 1/0 via communication register unit (CRU) © On-chip time/event counter © On-chip programmable fags (16) (© Macro instruction deteetion (MID) feature '# Automatic fist wait state generation feature © Single Svolt supply '* 40.pin package [N-Channel silicon gate MOS technology © Onchip clock generator ARCHITECTURE MEMORY ALLOCATION ‘The basic word of the TMS 9995 architecture is 16 bits in length. These 16 bits are divided into &-bit bytes for {external memory in the manner shown in Figure 1. A word i, therefore, defined as two consecutive B-it bytes in memory. All words (instruction opcodes, operand addresses, wordhlength data, et} are restricted to even address boundaries, Le, the most significant haf, or 8 bits, resides at on even address andthe leat significant half resides at the subsequent odd address, Any memory access involving a full word that is directed by software to utilize an odd ‘adres wil result in the word starting with this odd address minus one to be accessed‘The instruction set of the TMS 9995 allows both word and byte operations. Byte instructions may addres either byte as necessary. A byte accass of this type will not affect the other byte of the word involved since the other byte mill nt be accessed during the execution ofthe byt instruction, ‘The TMS 9895 memory map is shown in Figure 2. Shown are the lotions in the memory address space for the Rest, NIM, other interrupt and XOP trap vectors, and the dedicated adress segments for the on-chip RAM and the on-chip memory-mapped 1/0. GEGRESEST nf22 TMS 9995 ORGANIZATION ‘The block diagram of the TMS 9995 is shown in Figure 2. A flow chart, representative of the TMS 9996 functional ‘operation, is shown in Figure 4 Fach —_ meal TEE || ware ina Tew ne eo r t xs Cee -— sce, , [cam seuem FIGURE 3 — TMS9995 BLOCK DIAGRAM ” —_22.1 Arithmetic Logie Unit ‘The arithmetic logic unit (ALL) is the computational component of the TMS 9996. It performs all arithmetic and lonie functions roqured to execute instructions. The functions include addition, subtraction, AND, OR, exclusive OR, and complement. A separate comparison circuit performs the logie and arithmetic comparisons to conto) bits 1 through 2 of the status register. The ALU is arranged in two @bit halves to accommodate byte operations. Each half of the ALU operates on one byte of the operand, During word operand operations, both halves of the ALU, function in conjunction with each other. However, uring byte operand processing sults from the least significant half of the ALU sre ignored. The most significant half af the ALU performs all operations on byte operands so that the stats circuitry used in word operations i alsa used in byte operations. 22.2 Internal Registers The following three |3) internal registers are accesible tothe user {programmer} © Program Counter (PC) © Status Register (ST) © Workspace Pointer (WP) Prosram Counter “The program counter (PC) is a TS:bit counter that contains the word address of the next instruction following the Instruction currently executing, The microprocessor references tis address to fetch the next instruction from memory and ineroments the addess in the PC when the new instruction i executing, Ifthe current instruction in the microprocessor alters the contents of PC, then a program branch occurs tothe location specified by the altered contents of PC. All context switching {see Section 2.2.2.3.2) operations plus simple branch and jump instructions affect the contents of PC, 22.2.2 Status Regieter The status register (ST) i fully implemented 16 bit register that reports the results of program comparisons, in estes program status conditions, and supplies the arithmetic overflow enable and interrupt mask level to the inter rupt priority eieuits. Each bit position in the register signifies a particular function or condition that exiet in the microprocessor. Figure 5 illustrates the bit position assignments, Some insttuctions use the status register to check for 2 prerequisite condition; others affect the values of the bits in the register; and others load the entire status feqister with a naw set of parameters. Interrupts also modify the status register, The descrintion ofthe instruction set ater in tis document deals the elfect ofeach instruction oo the status register (see Section 3} FIGURE 5 ~ STATUS REGISTER BIT ASSIGNMENTS 2223 Workspace ‘The TMS 9995 usos blocks of memory words called workspaces for instuetion aperend manipulation. A work space occupies 16 contiguous words in any part of memory that not reserved for other use. The individual ‘workspace registers may contain data or addres, or function at operand regeters, accumulators, address ceisers, or index registers, Some workspace rosters take on special significance duting execution of certain instructions, “Table 1 lists each of these dedicated workspace registers and the instructions that use them. Figure 6 defines the workspace registers that ae allowed to be used as index registersTABLE | ~ DEDICATED WORKSPACE REGISTERS aeoWTER no, conrenre eco Dunno ° ics von Shimunion BLA 6 fre ste cian Sores tenon pet te 1 ttt Sot hy sot Se ne " ew Asa ttt ton BL en sd owton KP ® cmv Ase ch vn 80, 08,78, toes Sen ar one och BA, A on mera “ no omen oie BUN, TH WonKGPace REGISTERS 2 : ry oontsses FIGURE 6 ~ WORKSPACE REGISTERS USASLE AS INDEX REGISTERS22231 22.232 Workspace Pointer “To locate the workspace in memory, hardware register called the workspace pointer (WP) is used. The workspace pointer is a 18bit register that contains the memory address of the fist word in the workspsce, The address is lefrjustfied with the 16th bit (LSB) hardwired to logic zero. The TMS 9995 accesses each register in the work space by adding twice the register number to the coatents of the workspace pointer snd initiating @ memory re ‘quest for that word, Figure 7 illustrates the relationship between the workspace pointer and its corresponding workspace in memory FIGURE 7 — WORKSPACE POINTER AND REGISTERS For instructions performing byte operstions, use of the workspace register addressing mode (se Section 3,2) will result in the most significant byte of the workspace register involved to be used asthe operand forthe operation, Since the workspacs is aso addressable as « memory addres, the last significant byte may be directly addressed using any one of the general memory addressing modes, Context Switehing ‘The workspace concept is particularly valuable during operations that require # context switch, which isa change from one program environment to anther, a in the case of @ subroutine or an interrupt sevice routine. Such an ‘operation using a conventional multiregster arrangement requires that atleast part of the contents of the register 123 2aa 2ant 20.44 file be stored and celoaded using @ memory eyete to store or fetch each word, The TMS 9996 accomplishes this ‘operation by changing the workspace pointer, A context switch requites only three store eyeles and two fetch cycles, exchanging the program counter, staus register and workspace pointer, After the switch, the workspace pointer contains the stating address of 2 new 16word workspace in memory for use in the new routine. A corre sponding time saving occurs when the original context is restored, Instructions in the TMS 9896 that result in 2 Context switch include: Call subroutine (BLWP), Return from Subroutine (RTWP) and the Extended Operation (OP) instruction. All interupts slso cause a context switch by forcing the TMS 9996 to tap to a service sub ‘TMS 9995 INTERFACES Each TMS 9995 system interface uses one oF more of the signals from one or more ofthe signal groupings given in the pin description list in Section 3. Each interface is described in detail inthe following paragraphs, ‘TMS 9995 Memory Interface ‘The signals used in the TMS 9995 interface to system memory are shown in Figuie 8. ADAN6, AISICRUOUT Beco, !A/MOLDA AND OUD are Nov —- i Since wevony SYSTEMS BUT WILL External Memory Address Space The details of memory accesses that ae external to the TMS 9996 (off-chip acoeres) are given in the following paragraphs. (See Figure 2 forthe addestes that are in the external memory-addhess space) Memory Read Operations To perform a memory read operation, the TMS 9995 fist outputs the appropriate address on A-ATA and AIS) CRUOUT, and asserts MEMEN, The TMS 9995 then places its data bus drivers inthe high impedence state, esserts ‘BIN, and then reeds in the date byte. Completion of the memory read cycle and/or generation of Wait states is determined by the READY input as dataled in Sation 23.1.3, Timing relationships of the memory read sequence are shown in Figure 8. Note that MEMEN remains active iow] between consecutive memory operationscxour Lo L I 1 © | © | Fee ee FIGURE 9 ~ TS8995 MEMORY READ CYCLE [Although not explicitly shown in Figure 8, reading a word (two &-b% bytes) from extemal memory requires two memory read cycles that occur back tobeck {a Hold stote request will not be granted between cycles). f an instruction directs that a byte read from external memory isto be performed, only the byte snecifically adcressed will be read (one memory read eyelel. Extemal words are accested most-sgnficant (even) byte fire, followed By the leasesignificant (oda) byt, During memory read eycles in which an instruction opcode is being read, IAQ/HOLDA is asserted as shown in Figure 9, Note that sinee an instruction apcode ie a word in length, [AQ/HOLDA remaing asserted between the two byte read operations involved when an instruction opcode is read from the external memory address space. 23.1.1.2. Memory Write Operations ‘To perform @ memory wite operetion, the TMS 9995 fist outputs the appropriate address on A-ATS and A15/ CRUOUT, and asserts MEMEN. The TMS 9995 then outputs the date byte being written to memory on pins 00 {through D7, and then asserts WE/GRUCLR, Completion of the memory write eycle andlor generation of Wait states is detormined by the Ready input as detailed in Section 23.1.3. Timing relationships of the memory write sequence ae shown in Figure 10, Note that MEMEN remains active (low) between consecutive memary operations.exxour iT monov0n Q vet ares Beier ara unseat te FIGURE 10 ~ TMSO905 MEMORY WRITE CYCLE Writing @ word (two Bit bytes) to external memory requires two memory write eyeles that occur back-to-back (A Hold state request will not be granted between cycles.) If an instruction directs that a byte write to external ‘memory is t be performed, only the byte specifically addressed wil be written {one memory write cycle). External words are accessed most significant (even) byte first followed by the leastsignificant (odd) byt, 23.1.1.3 Diteet Memory Access ‘The TMS 9996 Hold state allows both external devices and the TMS 9996 to share a common external memory. To gain direct memory access (OMA) to the common memory, the external device frst requests the TMS 9995 10 enter a Hold state by esserting (taking low) the HOLD input, The TMS 9995 will then enter @ Hold state following completion of the cycle (either memory, CRU, external Instruction, or internal ALU eycles) that it i currently performing. Note, however, that a Hold state is not entered between the first and second byte accesses of a full word in the external memory address space, and a Hold state is not entered between the first and second clock cycles of a CRU cycle. Upon entry of 8 Hold state, the TMS 9995 puts its address, data, OBIN, and WE/GRUGLK drivers in the high impedance mode, and asserts 1AQ/HOLDA. The external device can then utilize these signal lines to communicate with the common memory. After the external device has completed its memory transactions, it releaees HOLD, and the TMS 9995 continues instruction execution at the point where it had been suspended. Timing relationships for this sequence are shown in Figure 11 1023.12 4 Sst wor PL saeasnnat 2 Ty @ wort me © crestor tena HOTS man be Quam © seveeve vito ae tat onto gh CLOUT wanton a wtch FUT i ih FIGURE 11 — T™sS9995 HOLD STATE To allow DMA loading of external memory on powerup, the TMS 9996 does not begin instruction execution after 3 Reset state until HOTD has been removed if HOLD was active (low) at the time RESET was taken from ‘ow to high RESET released), External devices eannot access the internal (on-chip) memory address space of the TMS 9995 when iti in the Hold state Since 1A (Instruction Opeode Acquisition) and HOLDA (Hold Acknowledge) are multiplexed on 8 single sign \GUHOLDA, this signal must be gated with MEMEN using external logic to separate 1AQ and HOLDA, When ‘MHENTEN = 0, {AG/MOLDA can indieate 1AQ, and when MIEMEN = 1, 1AQ/HOLDA can indicate HOLDA. Internal Memory Address Space Access of the internal (on-chip) memory address space is transparent to the TMS 9995 instruction set, That is, ‘operands can be read from and written into locations in the internal memary space simply by using the appro: priate addresses via any of the addressing modes in the TMS 9995 instruction set, and instructions can even be executed from the internal memory space by loading the appropriate address into the progrem counter of the ‘TMS 9905, 1"The TMS 9995 indicates to the external world when these internal memory address space accesses are occurring by asserting the same signals used for accesing external memory (see Figure} in a manner very similar to an ex temal memory address space access, There are 2 few differences in thess cycles, however, and these differences are detailed inthe following paragraphs. |When performing an internal memory address space access, the TMS 9995 outputs the same signals thet it woul for an external memory space acces, with the same timing (se Figutes 9 and 10) except forthe following (1) A single eyete (read or write) is output as both interne! bytes are accessed simultaneously. (Externely, it appears. as though 2 single byte memory access eyeleto an internal addrese i occuring) (2) The cycle atways has no Wait states, and the READY input is ignored by the TMS 9905 (see Section 2.3.2.3), (3) During read cycles, the data bus (00:07) output drivers ste put inthe high-impedance mode. During write cycles, the data bus outputs non specific dat, During read eyes to the intemal memory address space, the TMS 9995 does not make the read data available to the external world, If an instruction is executed from the internal memory address space, IAQ/HOLDA is stil ssserted, but only during the one read cycle shown externally while the full word is reag internally When ina Hold state, external devices ae not able to access the internal memory addeess spec. 2.3.1.2. Internal RAM “The 256 bytes of internal random access read/write memory (RAM), the memory addesies of which are shown in Figure 2, ae organized internally a5 128 16-it words. Since the TMS 0995 has 16 it internal data paths, to Bit bytes are accessed each time-a memory acess is made tothe internal RAM. ‘Byte accesses are transparent to the internal RAM, That is, when an instruction addresses a byte in the internal RAM, the TMS 9995 wil: (1) read the entire word but only use tho byte specifically addressed for @ read opers- tion and, (2) only write to the specifically addressed byte and not alte the contents ofthe other byte in the word uring a write operation. 23.1.22 Decramenter (Timer/Event Counter) ‘Accessible via one ofthe word addresses (see Figure 2) ofthe internal memory-mapped 1/0 address space is the de cromenter. The on-chip decremanter logic ean function a a programmable realtime clack, an avent timer, of a8 an ‘extemal event counter. A block diagram of the decrementer that is representative of its functional operation (but not necessarily representative ofits specific logic implementation i shown in Figuee 12. FIGURE 12 ~ DECREMENTER FUNCTIONAL BLOCK DIAGRAM 223.13 “The decrementer is configured as cithor a timer or an event counter using bit FLAGO ofthe internal Flag register ‘The decremontor is enabled/disabled using bit FLAGI of the internal Flag regster, (See Section 2.3.3.2. for de tals ofthe Flag register and sccessing the bits in i} When FLAGO is set to 220, the deeramenter wil funtion at 2 timer. When FLAGO is set to one, the decremente will function as an event counter, When FLAGI is st to zero, the decrementer is disabled and will not be allowed to decrement and request level 3 interrupt trap. When FLAG! is set to one, the decromenter is enabled and will decrement and request level 3 interrupt sraps, It should ‘be noted that when the decrementer is coafiguied as 2 timer, INTA/EC will be usable as an external interrupt level 4 trap request. When the decrementer is configured as an event counter, INTAVEC isthe input fr the “avant ‘counter pulses, and an interrupt level 4 trap request input is no longer available externally or internally ‘he general operation of the decrement is a follows, FLAGO ofthe Flag register ie frst eet ta slect the desired ‘mode of operation, The desire start count is then loaded into the Stating Count Storage Register by performing '& memory write of the count word to the dedicated internal memory mapped 1/0 addeess of the decrementer. (This also loads the Decrementing Register withthe same count The decrementr is then enabled and allowed to start decrementing by setting FLAG! of the Flag Register to one, (Both FLAGO and FLAGI are set to zero witen the TMS 9995 is reset. (See Section 2:32.11.) When the count in the Decrementing Register reaches zero, the {evel 3 internal intereupt request ath i set (see Section 2.3.2.2.3), the Decrementing Register i reloaded from the Starting Count Storage Register, and decrementing continues, Note that writing a start count of 000016 to the decrementer wil disable it When configured as a mer, the decrementer functions asa programmable real-time elock by decreasing the count in the Decrementing Register by one for each fourth CLKOUT eycle. Loading the decrementer with the appro: Priate start count causes an interupt to be requested everytime the count in the Decrementing Register reaches 2010, The decrementer cen also be used as an event timer when contigured as a timer by reading the deeromenter shed by performing a memory read from the dedicated internal memory mapped /0 address ‘of the decrementer) atthe start and stop points of the event of interest and comparing the two values, The dif ference will bea measurement of the elapsed time Wen configured as an event counter, operation is at previously dscutsed exorpt that each high to low transition con INT2/EC wil eause the Decrementing Register 10 decrement. These INTA/EC high olow transitions ean be asynchronous with respect to CLKOUT. Note that INTA/EC can function asa negetive cage tiggeredinerupt by loading start count of one ‘The decrementer should always be accessed asa full word (two Bit bytes). Reading a byte from the dcementer ‘does not presenta problem sinee only the byte specifically addressed wil be red, Writing a single byte to either of the bytes of the deerementer will result in the date by%e being written into the byte specifically addessed and random bits being written into the other byte of the decrement, iit State Generation ‘ait states can be generated for external memory cycles, external CRU cycles and external instruction cycles for ‘the TMS 9995 using the READY input. A Wait state is defined as extension ofthe present cycle by ane CLKOUT {yle. The timing relationships of the READY input to the memory interface and the CRU interface signals are showin ip Figure 13. Note that Wait states cannot be generated for memory eyeles that acces the inernsl memory ‘addeoss space or for CRU cycles that acces the internal CRU addres space, a¢ the READY input wil be ignored ‘uring these cycles. ‘The Automatic First Wait State Generation feature of the TMS 0995 allows a Wait state to be inserted in each ex temal memory cycle, regardless of the READY input, as shown in Figure 13. The Automatic First Wait State Generation feature can be invoked when RESET is assertad. If READY is active (hgh) when RESET goes through 8 lowto-high transition, the first Wait state in each external memory eyele will be automatically generated, I READY is inactive (low) when RESET goes through @ low-to-high transition, no Wait state will be inserted auto ‘matically in each external memory cyele. There i a one and one-half CLKQUT cycle time minimum setup time reauirementon READY before the RESET love-tohigh transition. Therecommended external citcuitry for invoking oF inhibiting the Automatic First Wait State Generation feature is shown in Figure 14, Note thot this festure does rot apply to internal memory address space accesses, external instruction cyeles, or any CRU cycles, Wait states feannot be generates during internal ALUfother operation cyces. The READY input is ignored during these cycles aFIGURE 13 ~ WAIT STATE GENERATION FOR EXTERNAL EXTERNAL INSTRUCTION CYCLES FIGURE 16 EXTERNAL CIRCUITRY FOR INVOKING/NNBITING ‘AUTOMATIC FIRST WAIT STATE GENERA TURE "232 ‘TMS 0995 Interrupts ‘The TMS 9995 implements seven prioritized, vectored interrupts, some of which are dedicated to predefined func tons and the remsining are user-definable. Table 2 defines the source internal or external, stsignment, priority level, trap vector location in memory, and enabling/etuting status register interrupt mask values foreach interrupt ‘TAOLE2~ INTERRUPT LEVEL DATA vecroR | WASk VALUES paioniry Location |" ToRNABLE ASENAEL mony mae qosmaane arrentanine | SOURCE AND tinovaerot ric) | aaa, | Tweinrennurr | THEINTERRUPT | ASSIGNMENT tvs) | tstiztHnustisy [STI THRUSTIS! ° O16 Fre Ext Reet (ne rn) C3 tre note) C3 IFESET sins) mo coo Oem Fe ct ona ie oe note 2) tee Now th on nove 2) eee exwral_Uae wo ee ae 900 ostnes os 2 ‘ow Nowe ZA Sena ExeraUie ' ooo hem rae 00 detnes TT } Sans > 008 Reon Fe ceo Trea | ae tee note 2) teeta te note2) Arena Oven | 3 cove ream rie oon a + one Ares ons antnes OTA Sopa ee Not 4 TREE i nt apt for Lan interes ap aqens Lael 48 net ull wh he Decran o “The TMS 9995 will grant interrupt requests only between instructions (except for Lavel O Reset), which will be ranted whenever it s requested, ie, in the midale ofan instruction), The TMS 9995 performs additional fune- tions for certain interrupts, end these functions wil be detailed in subsequent setions. The basic sequence that the TMS 9995 performs to service al interupt request is a follows (11 Prioritize all pending requests and grant the request forthe highest priority interrupt that is not maske! by ‘the current value of the interrupt mask in the status register oF the instruction that has just been executed, (Soe Section 4.5 for thse instructions.) (2) Make a context switeh using the trap vector specified forthe interrupt boing granted. (9) Reset ST7 through ST11 in the status register to 2er0, and change the interrupt mask (ST12 through ST1S} a8 appropriate for the evel ofthe interupt being granted (4) Resumeexecution with the instruction located atthe new address contained in the PC, and using the new WP. Al interrupts will be disabled until after this fist instruction executed, unles: (a) RESET is requested, in ‘which case it will be granted, or (b) the interrupt being granted isthe MID request and the NA intarunt is /equeste simultaneously {in which case the NMI requost wil be granted before the first instruction indicated by the MID trap vector is executed.) 62321 2321.4 “This sequence has several important characteristics. First of al, for those interrupts that are maskable withthe Interrupt mask inthe status register, the mask will get changed t0 value that will permit ony interrupts of higher priority to interrupt ther service routines, Secondly, status bit ST10 (overflow interupt enable) is reset to zero by the servicing of any interrupt 60 that overflow interrupt requests cannot be ganerated By an unrelated progesm segment. Thirdly, the disabling of other interrupts until after the fist instruction ofthe service routine is executed Permits the routine to disable othe interrupts by changing the interrupt mask with the frst instruction. (The ex ception with MID and NMI is explained in Section 2.3.2.2.) Lastly, the vectoring and prioritizing scheme of the “TMS 9906 permits interrupts to be automatically nested in most case. Ifa higher priority interrupr occurs while in an interupt service routine, a second context switch occurs to service the higher priority interrupt. When thet ‘outine is complete, a retuin instruction (RTWP) restores the saved context to complete processing ofthe lower priority ieerrupt, Interrupt routines should, therefore, terminate with the return instruction to restore original program parameters. ‘Additional details of the TMS 9995 interrupt are suppliod in the fllowing paragraphs External Imerrupt Requests Each ofthese interrupts is requested when the designated signals supplied to the TMS 9995, Joereupt Level 0(RESET) Interrupt Level 0 fs dedicated to the RESET input of the TMS 9995, When sctive (low), RESET. causes the “TMS 9996 to stop instruction execution and to inhibit (take to loge eve high) MEMEN, DBIN, and WE/CRUCLK, ‘The TMS 9996 will remain inthis Reset state as fong as RESET is active, ‘men ESET ie reste (lowto-high transition, the TMS 9995 performs a context switch withthe Level Q inter: rupt trap vector (NP and PC of trap vector are in memory word adresses 000046 and 000216, respectively.) [Note that the old WP, PC and ST ere stored in registers 13, 14, and 16 of the now workspace, The TMS 9895 then reaats ll status register bits, the internal interrupt request latches (sb0 Sections 2.3.2.1.8 and 2.3.2.2. for details ‘of these latches), Flag Register bits FLAGO and FLAG (sce Section 2.3.3.2.1 for datals of tho Flag Resiser), and the MID Flag (see Section 2:3.3.22). After this, the TMS 9095 stars execution with the new PC. It HOLDA is active (high) due to HOLD being active (low) when RESET becomes sctive, RESET will cause HOLOA to be released {taken low) at the same time as MEMEN, OBIN, and WE/CRUCLK are taken inactive (high), HOLD an remsin active as long as RESET is active and HOLDA will not be aserted. IT HOLD is active when LESET is released {lowto-high transition), HOLDA wil be asserted before the RESET context switch occurs and the TMS 9995 will remain in this hold state until HOLD is released, This RESET and FOLD priority scheme facilitates DMA loading of external AM upon power-up, Timing relationships of the RESET signal ae shown in Figure 15, oleate of the RESET rignal i igo the time at which the Automatic Fist Wait State function of the TMS 0805 ean be invoked (s00 Section 2.3.1.3. 16© ons care XX nscaes ha any e¥PH of TUSODOS cys ca be aking ce @ RESET ie samplag ot vey igh oom CLOUT tration OBEY i regain 10 be tevinane CUKOUT eycette @ I FERET wae neste nat st © tre cone item ving the Ree ap vcr bein ora CLOUT eve te REEET sae anavig tretnstn (tt FIGURE 15 —TMS9995 RESET SIGNAL TIMING RELATIONSHIPS. 2.3.2.1.2 NonMaskable Interrupt (NMI) ‘The NAM signal is the request input for the NMI level interrupt and allows ROM loaders, single-tep/breakpoint! reintenance panel functions, or other user-defined functions to be implemented for the TMS 9995, This signal and its assocatedintertupt level are named "LOAD" in previous 9900 family products, FRAT being active {low) according to the timing ilustated in Figure 16 constitutes 2 request for the NMI level Intertupt. The TMS 9995 services this request exactly according to the basc sequence previously described, with the priority lve, trap vector location, and enabling/reulting status register interrupt mak values a¢ defined in Table 2. Note that the TMS 9895 will always arant a request forthe NMI lve interrupt immediately after exec: tion of the curently execating instruction is completed since NMI is exempt from the interupt-dzablingatar ‘execution charactaristie of e2raininsteuctions and also the curent value ofthe interrupt mask, It should aso be noted thatthe TMS 9896 implements four bytes of is intemal RAM at the memory address of the NMI vector. This allows usage ofthe NMI level in minimum-chip TMS 9995 systems. It aso requires, however, ‘that this vector must be initialized, upon power-up, before the NMI level interrupt can be equested, ”So mo mr ‘ive time Yor MT a vane acon tthe Inostion bang orcete, Shawn cr oni tn ha @ eo cams wen rn a nn taal ca rin ve iu ii is FIGURE 16 — TMS9005 NMI SIGNAL TIMING RELATIONSHIPS 2.3.2.1.3 Interrupt Levels 1 and 4 (INTT and INT4/EC) The INTT and INT@IEG signal are the request inputs forthe Love 1 and Level 4 interrupts, respectively (Note chat f he decemenia configured ws an event counter, INT@/EG smo loner «Level interrupt requot np however. See Section 23,122) Level 1 and are maskabe use-deinable nerups The INT and INTA/EC interrupt inputs can accept either asynchronous pluses oF asynchronous levels as input signals. An internal interrupt request latch stores the occurrence of a pulse. A block diagram of the TMS 9995 internal logic for these request latches that is representative of their functional operation (but not necessarily representative of their specific logic implementation} is shown in Figure 17, Note that with this implementation only a single interrupt source is allowed ifthe input signal is @ pulse, but multiple interrupt sources can be wired-ORed together provided that each source supplies 2 level as the input signal, (The levels are then removed. fone at time by # hardware/software mechanism activated by the interrupt subroutine as each interrupting source is serviced by the subroutine.) “vac Ho te TY oo For Lae te abut own aes em featng mewn nce Tan emewe mown FIGURE 17 — FUNCTIONAL BLOCK DIAGRAM OF INTERNAL INTERRUPT REQUEST LATCH23.22 29221 232.22 ‘The TMS 2995 services each of these requests exactly according to the basic sequence previously described with the priority levels, trap veetor locations, and enabling/esulting status register interrupt mask values as defines in Tabie 2 Each internal interrupt request latch will get reset when the context switch for is associated interrupt level occurs. ‘Internally Generated Interrupts Esch of these interrupts is requested when the designated condition has occurred inthe TMS 8996, Macro Instruction Detection (MID) Interrupt ‘The acquisition and attempted execution of an MID interrupt opcode will cause the MID level interrupt tobe re: ‘quested before execution of the next instruction beging (MID interrupt opcodes ate defined in Section 45.18). In 2écition to requesting the MID level interrupt, the MID flag is set to one "1" (see Section 2:33.22). The TMS 9996 services this request exactly according to the basic sequence previously described, withthe priority evel, trap vector location, an enabling/resuting status register interrupt mask values af defined in Table 2. Note ‘that the TMS 0995 will alvays rant a request forthe MID level interrupt since MID is not afected by the interrupt _mask and i higher in privity than any other interrupt except for Level O, Reet. If the NAMI interrupt is requested uring en MID interrupt context switch, the MID interrupt context switch will be immediately followed by the [NMI interrupt service sequence before the first instruction iniested by the MID interrupt is executed, This is dane 0 thatthe NMI interrupt can be used for a single-step function with MID opcodes, Servicing the MID interrupt re quest is viewed 28 “execution” of an MID interupt opcode, NMI allows the TMS 9995 to be halted immediately ‘after eneounteringan MID opcode, It should aso be noted that the MID interrupt shares its tap vector with Level 2, the Arithmetic Overflow inter: rupt. See Section 2.3.2.2.2.) The interrupt subroutine beginning with the PC ofthis vector should examine the [MID Fiag to determine the cause of te interrupt, Ifthe MID Flag i sat to "1", en MID interrupt has occurred, ane if the MIO Flag is set to "0", an Arithmetic Overflow interrupt hes occurred, The portion of this interrupt st. outing that handles 41D interrupts should always, before returning from the subroutine, reset the MID Flag ‘The MID interrupt has basically two applications. The MID opcades can be considered to be ileal opcodes, The MID intertupt i then used to detect errors of this nature. The second, and primary application ofthe MID inter '1upt,s tallow the definition of addtional instructions for the TMS 9995, MID opcodes are used as the opcodes {or these macro instructions, Softwar inthe MID intertupt service routine emulates the execution ofthese instruc. tions. The benefit ofthis implementation of macros is that the macro instructions can be implemented in micro ‘code in future processors and software will then be direetiy transportable to these future processor Note that the TMS 9996 interupt request processing sequence does create some difficulties for reentrant usage of MID interrupt macro instructions. In general, to avoid possible errors, MID interrupt macro instructions should ot be used in the NAMI and Level 1 interupt subroutines, and should anly be used in the Reset subroutine if Reset isa complete initialization ofthe system, ‘Aaithmetic Ovetiow Interrupt ‘As the arithmetic overflow as described in this sub-section isnot funetional on current devices, thea flow interrupt ST10 should not be enabled, This will be corrected ata leer date ‘The occurrence of an arithmetic overflow condition, defined as status register bit 4 (STA) getting set to one see ‘Table 7. for those conditions that set STA to one), can cause the Level 2 interrupt to be requested. Note that this ‘quest will be granted immediately aftr the instuetion that caused the overflow condition. The TMS $995 ser vices tis request exactly according to the basic sequence previously described with the priarity level, trap vector location, and enabiing/resulting status register interrupt mask values os defined in Table - thmetic over {mn adcition to being moskable with the intereupt mask, the Level 2 overtlow interrupt request is enabled/isabed by status register bit 10 {ST10), the Arithmetic Overflow Enable Bit (i, ST1O= 1 enables overflow interrupt re- Quest; ST10 = 0 sisables overtiow interrupt request. If servicing the overflow interrupt requests temporarily overridden by servicing of « higher priority interupt, the occurrence of the overflow condition wil be retained in the contents of the status register Le, ST4 = 1, whieh is raved by the higher priority context switeh. Returning from the higher priority interrupt subroutine via an RTWP instruction causes the overflow condition to be re loaded into status register bit ST4 and the overflow interrupt to be requested again (upon completion of RTWP Instruction). The arithmetic overtion interrupt subroutine must reset ST4 or ST10 to zero in the status word ‘saved in register 1 before the routine is complete to prevent generating another overflow interrupt immediately ‘after the return, 19232.23 2a It should also be noted that the Level 2 arithmetic overflow interrupt shares its trap vector with the MID inter- ‘pt, Section 2.3.2.2.1 describes how the interrupt subroutine beginning with the PC ofthis vector con determine the cause of the interupt, Decromenter Interrupt ‘The occurrence of an interrupt request by the decrerenter (se Section 2.3.1.2.2) will couse the Level 3 internal interrupt request latch to get set. This latch is similar to those for Levels 1 and 4 in that its reet by servicing @ Reset interrupt or when the context switch for its associated interrupt level occurs (Figure 17). The Level 3 internal interrupt request latch being set constitutes a request for 2 Level 3 interrupt, and the ‘TNS 9995 services this request exactly according to the basic sequence previously described with the priority level, trap vector location, and enebiing/resulting sttus regis ‘Communication Register Unit Interface ‘The TMS 9995 accomplishes bit VO of varying felé width through the use of the Communications Register Unit {CRU}. n applications demanding abit-oriented 1/0 interface, the CRU performs its most valuable act: transferring 2 specified rumber of bits to or from memory and a designated device, Thus, the CRU is simply @ linking ‘mechanism between memory and peripherals ‘Acting a shit register, the CRU is 9 separate hardware structure of the TMS 9998 microprocessor. This structure ‘can serially transfer up to 16 bits of data between the CPL! and a specified device in a single operation, The 32768:bit CRU address space may be divided into any combination of devices, each containing any number of input oF output bits. When given the bit address of a device, the CRU can test or modify any bitin that unit. Several consecutive addresses can be occupied ty a device. These CRU applications ate controled by single and ‘multile-bit 9996 instructions, Single bit instructions facilitate the testing or modification of a particular bit ina device, The device in whieh a bit isto be tested (TBI, set to zero (SBZ), or set to one (SBO) is designated by the sum of the value in Register 12 and an &-it signed displacement value included as an operand of that instruction, Details of these instructions are sven in Section 4.5.7. Multiplebit instructions control the serial transfer of up to 16 bits between memory and peripherals. The device ‘with which communication is to take place is addresed by Register 12. The memory address to or from which data isto be transferred, os well as the number of bits to be transferred are included as operands of the multiple bitinstruetion. Details of these instructions ate given in Section 4.5.6. ‘The signals used in the TMS 9996 interface to the CRU are shown in Figure 18, The CRU address map is shown in Figure 19, [FIGURE 18 ~ TMS9905 CRU INTERFACE 01 see TTT FIGURE 19 CRU ADDRESS MAP ‘The concept of “CRU space" is the key 10 CRU operations An ideolagea area exist in which perioherl devices Feside in the form of an address. The CRU space is this ideological area: it hes monotonically increasing bit acidresses, Each bit represents a bistable 1/0 point which can be read fram or writton to. CRU address space and memory acidess space are independent of each other. Memory space is byte addressable, and CRU space is bit tddressabie, Therefore, a Usired device Is accessed by placing ts software base adaees in Register 12 and exerci ing the CRU command, CRU nomenclature is built around the four address types involved in Its operation. The software base address, hardware base address, address dsplacement, and CRU bit address interact to link memory to peripherals in bitseial communication vi the CRU. The software base address consists of the entite 16 bits of R12. In R12, the programmer loads twice the value of the CRU hardware addres of the dovice with which he wishes to communicate, Because only bis O through 14 (of Register 12 are placed on the address bus, the programmer needs to shift the hardware base adress let one position (equivalent to multiplying by two. Bits 0 through 14 of Resister 12 form the hardware bate address. For the snglebit instructions, the hardware base adides s added to the address displacement to obtain she CRU bit address, For multiplet instuctions the hardware base address isthe CRU bit adress, a233.1 External CRU Devices To input a data bit from an external (ft-chip} CRU device, the TMS 9996 first outputs the appropriate adress on AO.AI4, The TMS 9996 leaves MEMEN high, outputs logic zeroes on DO-02, strobes DBIN, and reas in the data bit on CRUIN. Completion of each CRU input eycle andr generation of Wat states is dtermined by the READY input a4 detailed in Section 2.3.1.3 Timing relationships of the CRU input cyte are shown in Figure 20, shettw euasts Ghee onthe @ 00.07 exer aut tog sre © swonspecite outer bit © AU int bit must be vt FIGURE 20 TMS9595 CRU INPUT CYCLE ‘To output a data bit to an oxternal (of oar 3 8 Bon . Dee a7 % Dat vss " m8 2 Bos 8 OM ‘ are 8 wR 8 BOM ” mn 8 23 READY 19 22 RESET 20 21 NM aTABLES — TMS 9005 PIN DESCRIPTION SIGNAL aN v0 DESCRIPTION POWER SUPPLIES Yee 10 Supa voltage (8 V Nom) Vss a Ground reterenen cLocks xTaLzvcUxiN 2 ~ ‘ysis! pu pin or ners! xian Algo xTaLt 1 ~ yea putin for nara xiao, euxour a our ‘tock ovtbut sgn. The frequency of tare treaueney ‘ADDRESS BUS a0 Py our Ades: Bu AD it most sian it of a 2» our the 1 it memory aden sari the 18 bt a 26 our ‘CRU acres bus. AA is the Zealot ait as 2 our can bit of te 16 bi marory aan bus and ae 2 our the 158 of te 155t CRU aces ts, Te as a our seress bus assumes he high impednce ae as 2» our han the TMS 9985 en te Hol ae ar 2 our ae = our a9 ™ our ao 2% our at 26 our ar a” our ate 2 our ANsicRUOUT 40 our ‘dees bit 1SICRU cutout dota ‘ORUOUT isthe LSB of he 16 Bit memory ‘drs bus ane the output dt in for CRU, ehh imoedonn sate when the TMS 9868 fein the Hol tu bo 2 v0 ‘ete Ba. During menor eles AEMTER ot " v0 tue 0D Ihe MSE) shraugh 07 he LSB 02 ° v0 sews 0 water dat trom he extern 05 a v0 memory system, During ronmaery eyeee on > v0 (GEREN nse) DO, OF ard O2 are used os 6 10 to ndcatewnether he TMS 9896 perform 26 5 0 inga CRU eye o an extemal insti or 4 No The dota bus etme na ih impadince state whan the TMS 9995 inthe Hol tts crun a Ww ‘OAU ino ta, During CRU eyes, CRUIN‘TABLE 5 — TMS 9895 PIN DESCRIPTION (Continued) SIGNAL 1 0. DESCRIPTION CONTROL mae ~ our Memory sable. When sei ow HTENER inceats tht WEICRUGCR, DBIN, ard he ‘memory evel, Wen native than) EMER Indicates that WE/CRUCLR, DBIN an the {ORU cycle, o are incating hat the “Ti 9895 is performing an external ist ‘Son MEMIEN does no eure the high i> adoro sae when the TMS 9995 in she Den ” our ‘ata busin, During marry reed eve, ‘DBT i acive ot naa hat ne "TS 9995 hat dab its dts hus output Stat owes that output deta onto the ata bu. Ouring CRU input cyl, BET ‘an nou evel. DBT ese the igh i cance sate aan the THES 0908 inthe WeORUTK 19 our (ite anabitinurted CRU cock. When active Nom), WEIGRUCLR incste nat memory rie dati avase onthe data bu he IERIEN - 0) or mat CAU dat out ae fn AIS/CRUOUT Inten EMER # ana 100 = D1 = 02}; that an extrait FHERTEN = 1 204.00, 01, ond 02 ar at cue 1001. WE/CRUCTR atsome the Wah Impodance state nen se TMS 99988 she Hota sat READY 2 " Fes. When ative high, READY indeatas ternal instution evel roady 1 be completes ‘When not ready ic indeted, 2 Wait sate (eine ss extensian ofthe praant eyele by one CLKOUT yee entered, At tw ond ofeach Wt state READY isoxumined so determine If anoth I ro be competes‘TABLE 5 — TMS 0995 FIN DESCRIPTION (Continued) SIONAL, 0. DESCRIPTION IAQIHOLOA 3 | 8 n ™ CONTROL (Gontah ois at request. When active low, HOLD \ndicats eo the TMS 9995 nat an externa controler desist se thoes and dat ses. Upon sensing Hoe equ, te Tis 9995 wil ener 3 Hold tte asfned at suspension of instruction execution! att as completes its rear yee ee Stein 23.1.43 for deals of entry into Mole stat). Atte pining of the Hola, the Ti 8995 places DBI, WE/RUCLK, ano the adress and dots burro th ah met ance state, an then respond by string TAQIOLDA. When HOLD is removed the “Tis 9995 etuns 1 nara operation, Insaco sauisiton meld acknowteae.t 'AQIMOLDA i ative righ) when EMER (0, he TMS 9995 sinccatng tat she memory rea vee progres i that of red an lon opcode. 1 AQIMOLDA i aeH8 han HEMTEN = 1, 4 TMS 9995s neating ‘htitisin he Hor state one hot BBN, WEP (CRUCLR, ac he adress nd date buses or In menighimpadnce sa nTeRAUPTS, Fact When actve low! RESET causes the ‘TMS 9005 1 enters RESET stat ie Section 23.211) an inhibit EMER, BBN, onc WE) TROGIR. When RESET ireesed ne TMS 9905 itits soe 4a interuptv- ‘utnce that acquires WP and PC fom momary word addresses 0000 and 0002, and bene ‘inate an ii sae. RESET ica Semi Nom oskaie interrupt When sv ‘lo, ‘ART causes the TMS 9995 to excout non ector I and PC) in memory word 3 ress FEF and FFE. RIT wil terminate an lle state i recognises only onc for ‘30h hghoow transition RH must be vind Inert ne, When atv lw TF caus the TS 9995 to execte see! one Interrupt ee ot mashed by she satus register 304a 42 ‘TABLE 5 ~ TMS 9995 PIN DESCRIPTION (Concluded) SIGNAL en uo DESCRIPTION 1 " Inrapt ourfent counter, When ithe the TRT/EE being civ a wl case “TM 9995 to execute a lve! four Interrupt | ‘ra ev Tov masked bythe sat reer. ne te dcrererteri erable | entire a an event cote, eign taraon on INTEIEC wil cute he cunt ie ‘he ceromentr tobe deeremented by or. (Sue Section 23.122 fr deta of nating ancontiquing the dcrmanar ‘TMS 9995 INSTRUCTION SET DEFINITION ach TMS 9995 instruction performs one ofthe following operations ‘+ Arithmetic, tsical, comparison, or manipulation operations on dats ‘© Loading or storage of internal registers (program counter, workspace pointer ar status) (© Data transfer between memory and external devies via the CRU © Control functions ADDRESSING MODES ‘The TMS 9995 instructions contain a variety of avalable modes for addresing random memory deta, 6. pro- ‘ram parameters and flags, or formatted memory data {character strings, data liste, et.) These addressing modes © Workspace Register Addressing © Workspace Register Indirect Addressing © Workspace Register Indirect Auto Increment Addressing ‘© Symbolic (Direct) Addressing ¢ Indexed Addressing © Lmmediote Adcressng © Program Counter Relative Addressing © CRU Relative Addressing uThe following figures graphically describe the derivation of affective address foreach addressing made, The apples bility of addressing modes to particular instructions is described in Section 4.5 along withthe description of the ‘operations performed by each instruction. The symbo's following the names ofthe adresting modes (R, °, “Rb, @LABEL or @TABLE (Rare the general forms used by TMS 9996 assemblers to select te addressing modes for register Workspace Register Adaresing, Workspace Register F contains the operand REGISTERR “The Workspace Register adéressing mode is spciled by setting the tworbit Tila (Ts or Tp} ofthe Instruction word equal t0 00, Workspace Register Indiceet Addressing, °R. Workspace Register contains the adress ofthe operand. The Workspace Register Indirect addressing mode is specified by setting the twobit T-eld (Ts oF Tp) inthe Instruction word equa 1001 Workspace Resistor Indirect Auto Increment Addressing, *R Workspace Register R contains the adores of the operand. After acauiting the address of the operand, the con tents of Workspace Register Rate incremented, The Workspace Register Indirect Auto Increment addressing made is specified by setting the tworbit Tild (Ts (or Tp} inthe instruction word equal to 11 2424 Symbolic (Direct) Addrewsing, @LABEL “The word following the instruction contains the addree of the oparand, insTAUCTION. \etwo-bit Teld (Tor TD} in the insteuetion word equal {0 10 and setting he corresponding Sor D fied equal to 0 4.2.5 Indexed Addressing, @TABLE (R) “The word following the instruction contains the base addres, Workspace Register F contains the index valve. The sum ofthe base address and the index value result inthe effective acess of the operand, ‘OPERANO (woo “Tho indexes addressing mode is specified by etting the two bit Tiel (Ts or Tp) ofthe instruction word equsl to 10 and setting the corresponding Sor D field not aqua x00. The value in the Sor D fied isthe register which com tains the Index value, 4.2.6 Immediate Addressing The word following the instruction contains the operand, 42.7 Program Counter Rel ive Addressing The cightbit signed displacement in the sight byte (bits through 16) of the instruction is multiplied by 2 ond ‘udded to the undated contents of the program counter. The results placed inthe PC, PROGRAM COUNTER (F CODE ose Le2- ose 3428 4a 4a 45 45.1 CRU Relative Addresi ‘The eight signed cislacement in the right byte of the instruction is added to the CRU base addres (its © throush 14 of workspace register 12), The esut is the CRU addres of the slected CRU bit nsraucrion ° 7 cruerr REGISTER 12 DEFINITION OF TERMINOLOGY “The terminology used in describing the instructions of the TMS 9995 is defined in Table 6 STATUS REGISTER MANIPULATION Various TMS.9995 machine instructions eect the status egatr, Figure 6 shows the status register bit assignments ‘abe 7 lst the instructions and their effect on the status register INSTRUCTIONS. ual Operand Instructions with Multiple Addressing for Source and Destination Operand cmel 0 1 7 9 4 § 6 7 8 8 WN 2 DB MW Os 1 8 = 1, the operands are bytes an the operand sdareses are byte acirestes, If B = 0, the operands are words and the LSB of the operand addres is ignore, ‘The addressing mode for each operand is determined by the T-feld ofthat operand { Ts0'% Soro [ADDRESSING MODE NOTES 0 aris Wetapne rear Indact 10 ° symbote ‘ 0 hats dene 2a " ats orkince eit indies 3‘TABLE 6 — DEFINITION OF TERMINOLOGY ren DEFINITIONS ° Byte incaor (= bye: 0 = wor « Bit coum . Destination ae ba Desnnation adios 10? Innmecite operand se Lestsigniiant nt mont bia eb 1158 iy Monegan et mut ito Int " Don eer % ‘Propam Courter emt Fest of eperation parformesby instruction s Source ace ote ey Source ness sr suas egser sta Bien of sts regiter 8 Sour sactens moder i content tn oo sie wantered 0 + rithms saon| ano Lees AND ~o Loaeat complement of nTABLE 7 ~ STATUS REGISTER BIT DEFINITIONSt ‘CONDITION TOSET 81T To 3, OTHERWISE sane Imernucrion Serroaron wernurron sre. anon iso arte or omen InSeRUTOns AND TENRUPS 0 ‘one coe Ta 6A)= 1a EB (08-00 cme ts tb ot ron toa) al a TSW TOPS is as tor aaa tort TEER ware a Tao ar oTERT or Tov steesed WT am AA Temi Ore, ech Ons rs. wo fe 3000 sn see sce, Cone We 8 oa oe me tom) tan a TH 9 ETT "hs abt oP neo tore) con TA A= Oa ATO. an oer oF irate ET a AN Ti ret Ose 7 See ech wr wee Imus, foes, sae Seawon ‘Be not act he tus bios Nowe H‘TABLE 7 ~ STATUS REGISTER BIT DEFINITIONS (Continues) ‘CONDITION TO SET BIT TO 1, OTHERWISE inernucrion Ser Too FoR NSTAUCTION USTED, a a Aso, Twe EFFECT oF OTHER IneTRUCTONS avo TERRUPTS zl iio oe iis a BHI ze isla a Tea raged RU aS EE wusal=d ra i a wT or Tia oad WAT oo two ote. oFen tov, move, ne ons 38,018 nv, ne ner Inv, ata, 300 foc sn. ne Sh, son se sn x08 ceo Teeny TT a Dee. ofc me, nen. 38 3c SR SRL TF tke THe Toe aTwATET ist Tor fete ET Fe redial ae er = owen | Nae 18 6) OA a Sei m8 A) a TT T= 8 To sie oH TH 68 OR a Sirsa oe) BEE BEST Tas oa = a TCT Tie RET Te Ta na T= Ba Ts oor dng av Tessa nas OAT=T te a= He Da nd (x)= ove The tens tere Yoon sony 00rd motia none a, nea 16a) = 9004 TH Treva or Teele aaa Desay st SD ‘Do not afet oe statu ew Note 7) a”TABLE? ~ STATUS REGISTER BIT DEF! {TIONS (Conclude wernucion | SET ron nernucnow Ua. on vate nor so, mierrcr or oTveR \naTAUOTINS AND WTERRUPTE 7 om ca.nove TSA a ate ven ee tH eben altar oT Wesoascts wemonsteren nmarattatecoaesbe team sce or Tae oh TT Se co om oe sr Treen ate eed TAT Be XRT Fae eT To sno] me La eT Gene Cae Tanase ET oa | ene ewesguag OF 1 oe or Terresrningerafeeaea aT = 1 Roar Theat st oe ecfor cove |e resutt | status enone MEANING jcompaneo| airs DescairTion o12|s Too | AFFECTED a [101 fol aa Ye 04 [say ioar~ com aa |r ot |1| Adsoves vee 05 | (sa) ioai~ (0a) c |1 0 0 Jo] comare No 02 | Compare ISA} 1 (Al art eet soprooriste natu ie 8 [1 0 0 [1] compare oes No 028 | Compare SA) #9108) ana set s fot 1 Jol subisct Yer 04 | 108) ~(6a1~ 10a) se fo 11 || subwect bie vet 05 | 1Dal—isai-+ioa soc |1 1 1/0 serons corresponding vet 02 | iDalonisal-+toai socs |1 1 1/1] setonescorespondingbyies | Yer 025 | (oalonisal~ (oa sec [0 1 0 |0| serzeror commending ves 02 | (DAL AND BA)~=104 secs [0 1 0 [1| setemonscareiponding bys | Yer 025 | (al AND A}~(04 mov |1 1 0a] Mow vet 02 | ISA) (oar mova_[1_1 0 [1] ove byes yet 025 | isa)~(oat 45.2 Dual Operand Instructions with Multiple Addressing Modes forthe Soures Operand and Workspace Register ‘Addressing forthe Destination Gow 0 1 2 3 4 5 6 7 8 8 won wo wo Forma (F CODE, ° 1s s ‘The addressing mode forthe source operands determined by the Ts fel, 1s 5 [ADDRESSING MODE ‘wores 00 Otte Workeace vai o ors, Worksoace reir ncact 10 ° Symboie 10 12.8 Indeed 1 i os Workspace epsterinctet suo nermant 2(or cove ResuLT | sTaTus mnemonic meaning |comraneo| errs DESCRIPTION o12345 Too jarrecteo oe [001 0.0 ofcompweone | No 2 10) to drermine 14 ar in ech it corressoncing position where aren (SA, 40, 88 2 cz |0.01 00 1|Comuezeot| No 2 | rest 10) to determine arin each it eorerponaing oiion where's awn (SAD, 40,00 72, xon [00101 0/excuseon | Yer 02 |ioai @ tsar-10) wey [00111 oman No ~ | matey uesignd 1D) ay unsigned SAL and lece urged 32 predue in D Imo onicent) and D1 eats antca, 1 MRIS 15, the next wor in memory ater WANS wil ow Joo14s tJowiee No 4 | eananee (SA) ee han requ to ursigned (0), perform no operation an set $74, Other, vide anes (0) and (D1 by units (SA ‘Quotient (0, remainder = (048). 11D = 15, ed fr the reine, 48.3 Signed Multiply and Divide Instructions (oF GOD 7s s ‘The addressing mode forthe source operand is determined by the T field T, 5 ‘ADDRESSING MODE ores 00 Ore ‘orkapar repr 7 1 ors, Workspace register incrsct 1 wo ° Symbolic 1 10 12S dered 12 " ots Workspace egstrincireet, 13454 (or cove: ‘aesuut | sTarus mveMonte meanina | companco| errs DESCRIPTION o123456789 too | arrecteo evs [oo 0000011 1|Sama Yer 0.2 | mutiny saned e's com Muteoty lant ices WFO by Inceer {SA an place signed 322i product in WRO imost eizent anc WA ast slontieane ows |o 00000011 0lsigma vee 0.24 | te me quotient cannot be Divige rested 5 ined 16 bit quantity 18000 he) i val rege number et ST merase, ide santa S904 complement integer in AO on WT By the signed so complement ing SA) and \WAO and the Sane reminder in WAI. The sgn ofthe auo- Vint ie aetermined by algo ivi and | REMAINDER) IDIVISOR Extended Operation (XOP) Instruction Gre) 0 1 2 3 4 5 6 7 8 9 WH 1 MS roma: [o 0 4 9 1 7+ 2 Ts 5 ‘The Ts andS fields provide multiple mode addressing capability forthe source operand. When the XOP is executed, the following transfers occur (40g + 40) ————+ we} (4245 + 40) ———+ ro SAF (now WRI (old we) ———+ fnew WR13) (old Pc} ——— (new WR4) (old St) ———* (now Wr5) ‘After those transfers have been made, STS is set to on and ST11 ate al set to 22r0, . and ST7, $T8, S79, ST10 (Overflow Interrupt Enable, ‘The TMS 9995 doos not sorvice interrupt trap requests (except for the Reset and NMI Requests) at the end of ‘the XOP instruction. a455 Single Operand Instructions Gmest 0 4 2 3 4 85 6 7 8 9 wo eB ‘The Ts and fields provide multiple mode addressing eapsbility forthe source operand. ‘oP CODE RESULT] STATUS vemonic ucaninc | companeo | arts escaiprion o12a4s6789 Tozero |AFFecTED| 8 [oo 0001 000 %| eum no = | sa-eor a fo 0 0 0 01 1 0 4 Ol arene ko = | er nvernisa ici siwe | 0 0 0 0 0 1 0 0 0 O|B:nn No = | tsar wer: isa + 21 eer ‘deed (oid WP) = in WR workapace (old PCI (now WR on (ast) — (nan Wt8), “The THS 9995 doe nox Request sheer ofthe LWP instruction cua foo 00010014 t\cew 0 ~ | ontsat operand sero fo © 00015 1 0 olsaw No ~ | Freee ~tsat mv [00000101 0 1{Imen ve 02 | GA tsa nec | 0 0 0 0 0.1 0.1 0 0] Neue Ye ot | teal osar ass [0 0 0 003 1 4 0 1) Abu No 04 | usan—tsat sw |0 0 0 001 1 0.1 1] sum No ~ | tsatvieome 7 tsa res bite @ hr 15:18), is 8 hrs 15+ (8), we [0 0 0 0.0 + 01 4 of tncrmen| ver oa | (sans sisay wer |0 0 0.0.01 0.1 4 1] ineromen| ver oa | toars2sisay by exo pec [0 0 0 0 0 1 1 0 0 0) Dunmen| ve 04 | tara pect fo 0 0 0.0 1 1 0 0 4] Decrement] Yes 04 | tsa)-2-1sa1 br wo © 000.01 001 of exscuw No = | extent th intrucion asa. il be ecmed trom PC andthe PC wil be vpdstesaccoraingl. The Inriclon acuta signal AG) wil ne be tue ene 2456 CRU MultipleBit Instruction ment 0 1 2 39 4 5 6 7 8 9 oH BO 6 Format ‘or cove c a 3 The C field specifies the number of bits to be transferred. If C = 0, 16 bits wil be transferred. The CRU base renister(WR12, bits 0 through 14) defines the starting CRU bit address, The bits are transferred serially and the ‘CRU addres is incremented with each bit transfer, although the contents of WR12 are not affected. Ts and $ pro Vide multiple mode addressing capability for the source operand, If eight or fewer bits are transferred (C = 1 through 8), the source address is byte address. f nine or more bits are transfered (C = 0, 9 through 15), the source address 9 word address. If the source is addressed in the workspace restr indirect auto increment mode, the workspace register is incremented by one if © = 1 through 8, and is incremented by two otherwise, Ifthe source is addressed in the register mode, and if the transfer ight bits or lei, bits 16 are unchanged, ‘or cove resurt | status anemone meaninc | comareo | errs | oescmiprion o 12 a4 s roo _| arrecreo tor foo 1 4 0 0 | to ve 025° | Besnning with ‘communication 3B of A), vaginer rant tne fis tom (6A srr [0 0 1 1 0 1 | Store ve 025° | eeinning wih communication LSB oF A, secited number ofits tom he RU 0 (88, postion with. 45.7 CRU SingleBit Instructions Geenl 0 1 2 3 4 8 6 7 8 9 1 2 Bo MOS Format: (0° CODE SIGNED DISPLACEMENT ‘The signed clsplacement is added to the contents of WR12 (bits 014) to form the addres of the CRU bit to be selected.‘oP CODE ‘STATUS vemonte meawina | arts | oescrierion ° a4 AFFECTED 580 ° 74 srroince = Sete lst sez ° +4 sabiese - Sethe selctes 210 cutout B10, 8 ° soa Tent bit 2 Hoe sete [CRU insur t= Lee sT2:if ne slot CRU in put 0,s0t 12 =o 458 Jump instructions Genera 24 6 6 CL Forma: ‘oF coe “SIGNED DISPLACEMENT Jump instuctions cause the PC to be loaded with the value selected by PC relative addressing ifthe bits of ST are at specified values, Ocherwise, no operation occurs and the next isituetion is executed since the PC points tothe ‘next instruction, The signed displacement field is @ word count to be added to PC. Thus, che jump instruction has 4 range of ~128 to 127 words from memory-wotd addres fellowing the jump instruction [No ST bits ae affected by jump instructions ‘OP CODE uvemontc MEANING STCONDITION TO LOAD Fe o 1 2 3 «4 6 6 160 oo 0 1 0 oO 4 ump eal stat wt o 0 0 1 6 4 Jampareaertmen | stt=+ a” o 0 0 1 1 oO 8 ump nian s10-tanssT2=0 awe o 6 0 + o + 2 ump ignores! | ST0=4 arsT2=1 a o 0 0 1 1 oa sump iow st0-Osnasr2-0 we 0 0 8 1 oo Jumpiow reais! | sT0-0orst2=1 aur fo 0 © + 0 0 0 Jump es a5 sti =mnsst2-0 we |o 0 0 1 0 0 © Jumpurcenitons! | Unconaivons ane oo o + oa Jump na eaery sto ane oo 0 + ot sump not ecu st2-0 wo fo 0 0 tt oo tumproovesion | st4=0 woe oo 0 + 1 8 Jump on carey stat sor oo ot to Jump odd party | srs=4459 Shift Instructions ‘ones IC = 0, bits 12 through 15 of WRO contain the shift count. fC =O and bite 12 through 15 of WRO - 0, the shift, count is 16. ‘OP cODE, mesuLT | STATUS vemonte meanine | compares | ars | bescaterion. ° 2 s 67 roo | arrecteo sua fo ° 010 | swnen ve oa | shia, snnmese vacated saa fo ° 0 6 6 | sninvins ves 03 | smite ov ats oF, sac | o ° 0+ a | sno yer 09 | smite a, 18 ino 8. su fo ° 0 0 1 | sntenane ves 03 | shew rane, o 45.10 Immediate Register Instructions ° 2 45 6 7 68 9 wo BR ‘cenerat ‘oP CODE @ w Format: oF ‘oF cove ResuLT | STaTus mwemonte meaninc | companeo| sits | Description on 456789 0 Too | AFFecteD a feo © 0 1 0.0.0 1 [radmin | ven os [ow sio2 0m anol foo © 0 1 0 0 1 0 faNDimmadie| ves 02 amano ror aw a foo © 0 1 0 4 0 0 |eompueimme | Yes 02 | commer nv 0 ute OP and et ore u foo © 10 0 0 0 |tosaimmediat | Yee 02 rea oni__|o 0 © 0 0 0 1 0 0 1 1 loRinmedie | Yes 02 | wor icra45.411 Internal Ropister Load Immediate Instructions ot 2s ¢ 8 6 7 8 8 we He ws Genes ‘oF cove oo oo 8 Fomat 10? ‘oP cove wemonte Meaning DESCRIPTION o12 3 4 5 6 7 8 8 wr [oo 0 0 © 0 + 0 1 1 4 | tontwoteone | 10? iWPl.costow oinerimmeate | atacea, um | 0 © © 9 2 © + 1 0 @ © | tosainterunt — | 10, bits 12:0 15 mae ST:2 musts, 45.12 Intemal Ropister Load and Store Instructions mest 0 1 2 3 4 5 6 7 8 8 oH wo Foomat: ‘oF CODE w ‘oF cone ‘STATUS MNgMonte meanne | errs | oescrirrion o12s 4s 678 9 oH AFFECTED sir foe 0 0 0 0 1 0 4 1 0 0 | Suen ~ [isa wr fo 0 0 0 6 0 0 0 + 0 0 o | tons | 0x6 | esr Regier swe | 0 0 0 0 © 1 9 1 0 1 © | stommork = | ewer wwe fo 0 0 0 0 0 0 0 1 0 0 4 | Losdmork = | ce 45.13 Return Workspace Pointer (RTWP! Instruction Gee 0 1 2 3 4 5 6 7 8 8 wh 2 wos romt [oo 0 0 0 0 1 4 7 0 0 0 @ 0 0 0 ‘The RTWP instruction causes the following transfers to occur: (wars)-*(sT) (wara)-e(ecy «warg)->(0P)45.14 External Instructions Gest 0 1 7 9 4 5 6 7 8 8 ww we ee : Ce ee) External instructions cause three data lines {D0 through D2) to be set to the levels described below, and the WE/ {GRUCER tine oe puted, slowing external control functions tobe initiated, "—ereone : wane | neon canna | ars | oescririon | _oaraaus o1zaese7000 arrecreo Bo [+] 02 we fooooooe1101 0 | Soomotusea | cpm | | tecroction nection | |i nser 0 0 0 00011044 | pot was fonsriasns | | w | exor [0 0 0 0 0 0 1 11 1 0 | Umrdetnes : wate cxon Jo 0 0 0 0.011 1 04 | mrdetns - fafa unex _|o 0 0 0 0 0 + + 1 11 | umrdetnes - a[afo 45.15 MID Interrupt Opcodes 46 464 ‘The instruction opcodes thst will cause an MID interrupt request (see Section 2.9.2.2) are (hex numbers): (0000.007F 0301.033F ooa0.017F 0361.035F o210021F 0361-037F o230023F (0981-039F 0250.025F 03A1-9038F 0270027F 03c1.030F o290029F 03E1.03FF 0280.028F 078007FF ‘0200020F ocoo.orFe O2E1-02FF INSTRUCTION EXECUTION Miroinsteuction Gyele Esch TMS 9995 instruction is executed by a sequence of machine states (micrainstruetions) with the length of| ‘ch sequence depending upon the specific instruction being executed, Each microinstruction is completed in one CLKOUT cyele unless Wait states are added to a memory or CRU eyete. (Also, each external memory space access of @ word and each external CRU cycle requires at feast two CLKOUT cycles but will be accomplished with a single microinstruction) a162 462 Execution Sequence ‘The TMS 9995 incorporates an instruction prefetch scheme which minimizes, and in some eases eliminate, the time required to fetch the instuction from memory. Without the prefetch, @ typieel Instruction execution sequence iss follows: (1) Fetch instruction (2) Decode instruction (8) Fetch source operand, if needee (8) Fetch destination operend, if needed 18) Process the operands (6) Store the results, if required ‘Tho TMS 9905 makes use of the fact that during Step 5 the memory interface Is aot required therefore, the fetch ‘of the next instruction can be accomplished in this time, Ths instruction is then decoded during the steele) that isla} required to store the results ofthe previous instruction, which crates even more execution overlap. Table 8 ilustrates the case of maximum efficiency for an Add instruction {instruction opcades and operands are located in the internal RAM). Note that it effectively takes only four machine states to perform all sx steps ‘TABLE ~ EXECUTION SEQUENCE EXAMPLE sver cart MEMORY CYCLE INTERNAL FUNCTION fi Fon nection Pres Previous Oparance 2 7 Wee Rene (ecace insetion 3 2 Fete Sours ‘ a Fath Osainaion 5 _* eth Next istsction a [It should be noted thatthe instruction prafetch scheme employed by the TMS 9995 can cause self modi software to execute incorrectly. Incorrect execution will result when an instruction is supposed to generate the ‘opcode of the very next instruction to be executed. (The TMS 9995 will begin the fetch of the opcode of the next instruction before the currently executing instruction stores the results ofits execution ‘TMS 0995 Instruction Execution Times Instruction execution times forthe TMS 9995 area function of: (1) Mechine state time, 62. (2) The location ofthe instruction opcode (interna or external memory) (3) The location of the workspace andthe operands (internal or external memory) (4) Addressing mode used where operands canbe fetchec vie multiple addressing modes (5) Number of Wat states introduend, 2 appropriate,Table 9 lists the number of clock cycles required to execute each TMS 8996 instruction for various combinations of on-hip/ottchip location of instruction opcodes, operands, and workspace. (Other combinations can be ex tropolated trom the ones listed.) For instructions with multiple aciressing modes for either or both operands, Table 9 lists CLKOUT cycles and associated off-chip memory acceeses with all operands adcresed in the work space reister mode. To determine the total number of CLKQUT cycles and associated offchip memory accesses required for other addressing maces, the appropriate valves from Table “A (Table 10) are added to the base amounts for that instruction. ‘Tre total execution time for an instruction is T= seg (on +c2 +WixMT + xMa}) were T = ‘total instruction execution time tez_= CLKOUT cycle time Ci = bate CLKOUT cycles €2__ = additional CLKOUT cycles for operand address derivation (alues in Table"A” ace for one ‘operand only) number of Wait states per off-chip (byte length} memory eyele base off chip (byte lenath) memory cycles adeitional off.chip (byte length) memory cycles ‘or operand acdree derivation (values in Table "A" are for one operand only) Several examples ae listed in Table 11TABLE ~ INSTRUCTION EXECUTION TIMES ‘opcode Opcodes 8 | Operands OFF Immediew | Chip Soure InstRUCTION Operearot | Operand Of Oncodes | chip: Other | ChiprDestnaton | Opcode & | Operant ‘Aiopmranas | OperandsOn |” Operana'On” | At Operands | Areas ‘oncne ie ‘che ‘Offchin | Derivation ® @ Gi [ xi | Sonnee [owe ae Aas 8 a a ‘cKON cz iv (Ste esti IVS 1ST i DIVE (Sra ioe = Toe Tai mc 2 JUN TAI Tr nnroevor LOCA E=01 LOGR |>]>]0]2[e\e[=]2)-]2]g|~Ja/efolela|@ al feof fafr}ns|u fafa ]ay la||=]=]afo) =| lofo}or|a >}>|>]>[>|>f>l>]>|. | Toe e[s[ata "Thaw vty wil poly to Rte sar flowing Rasalan 8 (Revison © pars waive bys "BI the dae code of he aymBOTTaTON| fon} fale osfasfefe al fen] fon} fafa] = fof fole=fofefulefe]=[eJn[ofo nfo! «]=[a) = fofm [ol fs holefololg]=fol> ele ol=l 1g] | |||] »|ayfaz]y|=| =] ]oo]o |e] | | =|] fe zfs | =| o> ||| | foINSTRUCTION EXECUTION TIMES (Concluded) ‘oncodes INSTRUCTION Operands OF Oncode:t | chin: Ail Ott |chi; Oertnation | Opeoder& | Operand ‘AN Operands | “OpwandsOn | Opwand On| AllOpernde ‘once ‘hin ‘ci often a = «ols t2ts [s fs} sta la 580) EO [sez a[ of se [2 fs [2 tol.«t- | [sero 7 aef ee ps Pe ts pa 4 SHIFT ICZO) Boo | e¢ [> [oo] [ec] e SHIFT (6-0, ois 218 ofwRO-_| [0 | | 2 | | -2~] 77 | SHIFT IC=0, is 1215 of WRO-NZOL | FN | a [ wi] “2 ew] 2 ew] z soc “Tees a pe fe ts Dep ae ocd a [of s [2 fs | 3 Ps [sy «a STOR (6-07 apo [a 6 |e [at] STER a-{ef~ t— Inver Cone Sich IForSay intro, incudng Ret, ww. oti0, | 14} 0@] 7@ | @ | 76} e@ | 20@| 129) and orton! L {© “Adio cycles toot edd appranvae arene in @ vo vector oft eis: Naw mortspace onc. TootesA (Tae vt {© Reamer tor regntr ony nnvocion arom eho (Shift © Wahcok crce sur enecton Canteiaccouen te inecevont ane sn cael ogc areas oe © Stucrrainin ae Ste vot am uated otras Fes rose sere ‘Set arei = aumow o KOU ver eo Q fiom nine sanan ema @ Exaction tine own donno nla eaction ine ot ‘Vroo arene New woranser on oie " 5‘TABLE 10 OPERAND ADDRESS DERIVATION (TABLE “ “ Workspace Rept, Workspace Roners oe Adios For ‘On Chie bee ‘Wr chin Soe ‘ae Addn For avonessincmooe | Iniecdiveed Adare or dex: | Adar For nde Index Aden Operands ‘dred Opa | Addroand Oprecs Sperands Symbote(bned | AndSymbote Ove: | AndSyrbot Ovect) | Spa fee Ares On hi ‘Atérases OChp” | “Adéremes On Chia _| Adena Of Chip we o |e o | © o | o o |e (or To = oo | - WR nase 1 1 | o 1] oo 2 [2 2|2 (tserTo-o0) ‘sto incre a|o a} oo s]« sf (ree I Sybao - — (ts9°T9=10, 1] 0 2} 2 r}o 2] 2 (30-79-10, a] af a} s fa Sord#0) i 82© [eave TaEvis AoW © | _eu) seve 1a AoW = “Ta8vT8 IW AOH Za 1H AOW | so} sesppe ose spond, ‘Sa Tawvxa aN. NOLLNDaXa NOLLONWISNI~ 44 aTa¥E 55, ‘TMS 9995 PRELIMINARY ELECTRICAL SPECIFICATIONS. 5.1 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)* Supply votone, Vect 03107 Allinput voltages 031020 Output voltage 0.3107 Continuous power disipation 1 Operating fees temperature range Oc to 70°C Storage temperature range -s8°C to +150°C 52 __ RECOMMENDED OPERATING CONDITIONS PARAMETER a Wom waar Sup tan Ve 3 7 Tow iv put aap. Va ae oes TAT RTO =o oe-bv Towrive cet outa. Va =a 3a-[v Tigevel tpt eure gy ek og 100} To ive ouipt Save ta a St [me 53 ELECTRICAL CHARACTERISTICS OVER RECOMMENDED FREE-AIR TEMPERATURE (UNLESS OTHERWISE NOTED) PaRRRETER TERT CONDITIONS an wax [oT Vou Wheat onpet vlan Veg Minow WAX 28 v Wot tom tan Vee MIN To = WAX aa ea[ Vv oz Ottawe ouput euvent veo wax PYOmae 2h 1 nut current Wie vss Veo _ 250 [wa [Sr Caecione | acters t= 1M a 5 ea Tro Goon Canam] Or Bs citersne OV ca Aes _ 10 *auttypical aun are at Vee = SV. Ta = 28°e11 taestont roe tT Tv eee ti Pa ae a eae A rel =a 55srs 9998, XTAL2ICLKIN xTALt EXTERNAL OsciLLaToR FIGURE 26 - EXTERNAL OSCILLATOR 55 TIMING REQUIREMENTS OVER RECOMMENDED OPERATING CONDITIONS PARAMETER Mn _wow_ Max [unr ia rtp une, READY ore 10 ELKOUT (memory eva 100 ns rs Told ime, READY ster CLOUT Inemory and GRU eee @ a * Snap une, Detar fo CLOUT ws ne tat Setup ime, CRUIN rir CLOUT 700) me na Tol ie, CRUIW pict CLKOUT ° ne i Srup ine, READY pri 101 GLKOUT RUG io rm ‘i Setup tire, FOTD por COROUT 12 m7 6 Setup ine, RESET ang NH porto, CCROUT 130 = WL Fale ein erp np Wer 1a Fal ine OF TTA np lm on Fae mis, ET input 7a cI wus, Pus icin EE put ow 180 a va Gye ter, Fit EY cm 568 SWITCHING CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS (See Figure 34) PARAMETER Test conomTions [ww max _Jowrs] Tal Bao re CURIN «wo CLOUT = om Ta Rie tine CLROUT oupun aoe ig Fathi, COROUT ovat 20 “i? Pale wih gh, CUROUT ona Tata my Tic2 Pole whom, CLOUT etput eam a 42 Oa in, 1 COROUT oar TE Tey Tage oe gg___ Dette, + CUROUT To MENTE Tot see Tre Tgp 40 [os ‘ga Det Wie1 CLKOUT 19 MEER Woh FIGURE 35 Tea Teg 165 Osay tne, TCLKOUT 9 BBN Tow o 20 [ re 13g Oaby ine 1 CLKOUT 1 DUTT Aya 24 o sore ‘7 Dela tine, CUROUT wo ROIHOLDA TAR fp-2en ° 20 [om Tg Dely ine CUROUT 16 TAGHOLDA To eu 100 0F ° 50 [oe gg Delay ti, FELKOUT 0 dts stout wi ° 0 | 10 Oey tir CUROUT ro WERERUCTR Tor ° 20 [re git Det ie, 1 CUROUT to WERERUCTR Wish o sof eg Fa tne, WETERURTR op se TAGE ACE ine memory re eves Bas om Tha Wold tne, dare and CRUOUT aut Tapa oF Ts le tne, date output Tegal oe ‘iL Pale wit on, WE/CRORTR oxioat Tea oe Tar Outer bie ine geo |FIGURE 20 - TMS 9995 MEMORY INTERFACE TIMING 7! U I Wi I rd |=jh baramarl fee FIGURE 30 ~ TMS 9995 RESET AND NM TIMING LAST CYCLE CONTROLLED. NEXT CYCLE CONTROLLED BY TNS 0085, BY TRS 9995 FIGURE 31 ~ 15 9995 FOLD TIMING FIGURE 32 — TMS 0095 INTERRUPT INPUT TIMING — fs I f+} is 4 FIGURE 33.~ TMS 9995 EVENT COUNTER INPUT TIMING 59ws 9905, ourrurs 2ave. — Yow tn cove 4 You max) a ‘Tus 9995 inputs. FIGURE 34 — MEASUREMENT POINTS FOR SWITCHING CHARACTERISTICS FIGURE 25 ~ SWITCHING CHARACTERISTICS TEST LOAD CIRCUIT