582 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 67, NO.
3, MARCH 2018
Phasor Estimation Algorithm Based on Complex
Frequency Filters for Digital Relaying
Babak Jafarpisheh , Student Member, IEEE, Seyed M. Madani , Senior Member, IEEE,
and Farzad Parvaresh , Member, IEEE
Abstract— This paper presents a new filter-based algorithm
to estimate the fundamental phasor of fault currents, using the
proposed complex frequency filter. The presence of decaying dc
component (ddc) in fault currents causes large error in discrete
Fourier transform (DFT)-based phasor estimation methods. The
proposed filter discriminates the ddc from dc and sinusoidal
signals. In this algorithm, first, the ddc is filtered out by the
proposed filter. Then, the fundamental phasor can be precisely
extracted by applying DFT. Second and fourth order of the
complex frequency filter and their design method are presented.
To evaluate the performance of the proposed algorithm, several
test signals are used. The algorithm is also compared with recent
DFT-based and mimic-DFT methods, using four performance
indices. The simulation results demonstrate the robustness of
the proposed algorithm against harmonics, noise, multiple ddc
components, and off-nominal frequency. It also offers faster
convergence speed. The proposed complex frequency filter can
also be used for the phasor estimation of harmonic components
in the presence of ddc with no need to readjust its parameters.
Index Terms— Complex frequency, decaying dc compo-
nent (ddc), digital filter, digital relays, discrete Fourier trans-
form (DFT), phasor estimation.
I. I NTRODUCTION
A CCURATE estimation of fundamental phasor plays an
important role in digital relays, phasor measurement units
(PMUs), and wide area monitoring, protection, and control.
To precisely estimate the fundamental phasor, several methods
have been investigated. The phasor estimation methods must
provide high convergence speed and low computation burden.
The methods must also be robust against harmonics and noise.
The fundamental phasor can be estimated by using various
digital signal processing (DSP) techniques, such as discrete
Fourier transform (DFT), discrete wavelet transform, cosine
filters, least square error, and intelligent techniques [1]–[9].
From the viewpoints of convergence speed, accuracy, and
simplicity in implementation, DFT is the most commonly
used technique for phasor estimation [10]. For a periodic
Manuscript received July 22, 2017; revised September 26, 2017; accepted
September 29, 2017. Date of publication January 16, 2018; date of current
version February 8, 2018. The Associate Editor coordinating the review
process was Dr. Niclas Bjorsell. (Corresponding author: Seyed M. Madani.)
The authors are with the Department of Electrical Engineering, Faculty of
Engineering, University of Isfahan, Isfahan 81746-73441, Iran (e-mail:
babak_jafarpisheh@yahoo.com; madani104@yahoo.com; f.parvaresh@
eng.ui.ac.ir).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIM.2017.2783099
0018-9456 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
signal, the DFT can be used to estimate the fundamen-
tal phasor and filter out the harmonics. However, decaying
dc component (ddc) of fault currents, which is aperiodic,
causes significant error in DFT-based phasor estimation meth-
ods [11]. Therefore, several studies have been presented to
reduce the DFT phasor estimation error caused by the ddc,
which are mainly classified into two groups.
In group one, first, ddc parameters (magnitude and time
constant) are estimated using various calculation methods.
Then, the undesired ddc value is subtracted from fault current
signal. Finally, DFT is applied on the remaining signal to
estimate the fundamental phasor [12]–[25]. In this paper, this
group is called calculation-based methods. In [12], two partial
sums are used to estimate the ddc parameters and subsequently
the fundamental phasor. The performance of this method is
degraded in the presence of harmonics and noise. In [13]–[15],
the fault current samples are divided into odd and even
strings. The fundamental phasor is estimated based on DFT
of these strings, which results in heavy calculations. Another
calculation-based method is presented in [16], which requires
one and a half cycle length of data samples. In [17], the ddc
parameters are calculated using three consecutive DFTs, which
causes heavy computation burden. This method also requires
more than one cycle length of samples for each phasor
estimation. In [18], the undesired ddc value is subtracted using
two DFT calculations, which causes heavy computation. Other
DFT-based methods presented in [19]–[21] require one cycle
length and two additional samples to estimate the fundamental
phasor. Reference [22] calculates the ddc value using the
integration of fault signal. However, the estimated phasor has
large error in cases of small ddc time constant because of its
ddc linear approximation. To enhance the phasor estimation
performance of [22], other DFT-based methods are presented
in [23]–[25]. These methods suffer from heavy computation
burden due to matrix and logarithmic calculations. Most of the
above-mentioned methods do not have appropriate accuracy
either for large or small values of ddc time constant. Another
calculation-based phasor estimation algorithm is presented
in [26], which improves the mentioned disadvantage of the
phasor estimation methods. In general, heavy computation
burden is the main disadvantage of the calculation-based
phasor estimation methods.
In group two, first, the ddc is suppressed by a filter. Then,
the rest of the signal (consisting the fundamental component,
harmonics, and noise) is given to DFT for fundamental phasor
JAFARPISHEH et al.: PHASOR ESTIMATION ALGORITHM BASED ON COMPLEX FREQUENCY FILTERS FOR DIGITAL RELAYING
estimation [11], [27]–[29]. This group is called filter-based
methods in this paper. Mimic filter is a commonly used solu-
tion for filtering the ddc. However, the mimic is a high-pass
filter, which magnifies harmonics and noise, and causes large
oscillatory error in phasor estimation [11]. Reference [27]
presents a modified notch filter to mitigate the ddc. However,
its performance is degraded in the presence of harmonics and
noise. References [28] and [29] present an auxiliary signal,
which consists of attenuated ddc. Then, the fundamental pha-
sor of this auxiliary signal is estimated by using DFT. Finally,
the fundamental phasor of fault current signal is obtained
based on the estimated fundamental phasor of the auxiliary
signal. This method results in oscillatory error for small
values of ddc time constant. The finite-impulse response (FIR)
high-pass filters can also be used for filtering the ddc [4].
However, their performance is degraded for short ddc time
constants. High-order FIR filters cause long delays, which
is not tolerated for digital relays. Sensitivity to harmonics
and noise is the main disadvantage of the filter-based phasor
estimation methods.
This paper presents a new filter-based algorithm to extract
the fundamental phasor of fault currents, using the proposed
complex frequency filter. For this purpose, first, the ddc is
filtered out by the proposed filter. Then, the fundamental
phasor can be precisely extracted by applying DFT. The
proposed filter suppresses the ddc for wide range of ddc
magnitude and time constant, avoiding heavy computations.
Second and fourth order of the complex frequency filter and
their design method are presented. To evaluate the performance
of the proposed algorithm, several test signals are used.
The algorithm is also compared with recent DFT-based and
mimic-DFT methods, using four performance indices. The
simulation results demonstrate the robustness of the pro-
posed algorithm against harmonics, noise, multiple ddc com-
ponents, and off-nominal frequency. It also offers faster
convergence speed. Furthermore, the proposed algorithm sig-
nificantly reduces the computation burden in comparison with
the calculation-based phasor estimation methods. The pro-
posed complex frequency filter can also be used for the phasor
estimation of harmonic components in the presence of ddc
with no need to readjust its parameters.
The rest of this paper is organized as follows. Section II
describes the proposed filter-based phasor estimation algo-
rithm. Section III evaluates the performance of the proposed
algorithm using several test signals. Finally, Section IV con-
cludes this paper.
II. P ROPOSED F ILTER -BASED A LGORITHM
A. Decaying DC Component in Fault Current Signals
A typical fault current consists of a ddc and sinusoidal
components as [26]

P axis of the S-plane. However, dc signal has zero frequency,
i (t) = I0 · e−t /τ + Ik cos (kω1 t + θk ) (1)
k=1
in which I0 and τ denote the magnitude and time constant
of the ddc (ddc parameters), k and P are used for harmonic
number and maximum harmonic number, respectively. The
583
Fig. 1. Complex frequencies of fault current signals in the S-plane.
magnitude and phase angle of the kth harmonic are also
denoted by Ik and θk . The fundamental angular frequency
is ω1 .
The fault current signal given in (1) is discretized as [13]

N/2−1  
−nt /τ 2πk
i [n]  i (nt) = I0 e + Ik cos n + θk
N
k=1
(2)
where N and t denote the number of samples per cycle and
sampling interval, respectively. To prevent the aliasing phe-
nomenon, a low-pass prefilter is used. Therefore, the maximum
harmonic number P is considered to be N/2 − 1 [13], [26].
During faults or disturbances, the ddc exists in power system
currents besides the fundamental and harmonic components.
Current transformers (CTs) may also generate the ddc, due
to their burden [13], [14]. The time constant of ddc varies
from 0.5 to 5 cycles, depending on the fault resistance, fault
location, and power system structure [11].
DFT is a widely used DSP technique for phasor estima-
tion in digital relays and PMUs. It accurately estimates the
fundamental phasor of a periodic signal. Because of aperiodic
property of the ddc, it causes oscillatory error in DFT-based
phasor estimation methods.
B. Complex Frequency
A new concept of complex frequency is introduced in this
section. As mentioned previously, the fault currents typically
contain sinusoidal components and ddc. In the existing lit-
erature, phasor estimation methods treat ddc like a constant
dc value. However, these two components are different in
nature, which is shown in Fig. 1 by representing frequencies
in the S-plane.
As shown in Fig. 1, frequencies of sinusoidal or periodic
signals are located on the imaginary axis of the S-plane. The
frequency of ddc is equal to −1/τ , and it is placed on the real
which is located at the origin of the S-plane. Since the ddc
time constant varies from 0.5 to 5 cycles, the ddc frequency
varies from −100 to −10 (1/s), for 50-Hz power frequency.
This real frequency interval [−100 −10] (1/s) is called the
ddc frequency region in the rest of this paper.
584 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 67, NO. 3, MARCH 2018

It may seem that the implementation of FIR high-pass filters

can be useful for suppressing the ddc. However, these filters
have the following drawbacks [4], [11] as follows.
1) They cannot efficiently suppress the ddc, especially for
the cases of short ddc time constants (or large ddc
frequencies). Using wider stopband for FIR high-pass
filters affects the fundamental component (50 Hz).
2) FIR filters have to be high order and consequently cause
long delay which is not tolerated for digital relays.
3) Their estimated fundamental phase angle has large error,
during off-nominal frequency conditions.
To overcome the above-mentioned disadvantages, a new
complex frequency filter is proposed in Section II-C for ddc
suppression. Fig. 2. Locations of zeros and poles for the proposed second-order filter.

C. Proposed Complex Frequency Filter

The goal of this paper is an accurate estimation of funda-
mental phasor of fault currents. As mentioned earlier, the ddc
causes error in this estimation. Therefore, the main idea of
this section is to design a filter to attenuate (or remove) the
ddc of fault current signal.
The general transfer function of the proposed complex
frequency filter is

(s − z 1 )(s − z 2 ) · · · (s − z m )
G(s) = K (3)
(s − p1 )(s − p2 ) · · · (s − pm )

where m is the order of the proposed complex frequency
filter and also denotes the number of zeros and poles in the
filter. In this paper, zeros and poles are denoted by z and p,
respectively. The filter gain is also denoted by K .
The proposed filter must remove/suppress the ddc, which is
done by inserting zeros on the ddc frequency region. On the
other hand, the filter must not shift the fundamental phase
angle, which is done by inserting poles at the left-hand side
of the S-plane.
In this paper, the proposed filter is designed based on
general power system structures in which the ddc frequency
varies from −100 to −10 (1/s). However, for a specific
power system, the ddc frequency region can be considered
shorter, based on the system parameters and configuration.
Zeros are placed at the ddc frequency region in such a way
that minimizes the multiplication of zeros distance to any
frequency in the ddc frequency region. For simplicity, in this
paper, zeros are distributed evenly over the ddc frequency
region, as shown in Figs. 2 and 3 for the proposed second-
and fourth-order filters, respectively.
In order to compensate phase shifting due to the added
zeros, it is necessary to insert poles at appropriate locations in
the S-plane. These poles must be far enough from the zeros,
not to neutralize the ddc attenuation by zeros. On the other
hand, these poles must be far enough from the fundamental
imaginary frequency ( j 100π (1/s)), not to affect the funda-
mental estimated phasor.
In Sections II-D–II-F, the design of the second- and fourth-
order filter is described.
Fig. 3. Locations of zeros and poles for the proposed fourth-order filter.
D. Designing Second-Order Complex Frequency Filter
The design of the second-order complex frequency filter is
done in three steps as follows.
Step 1: Two zeros at −32.5 and −77.5 (1/s) frequencies
are chosen to distribute zeros evenly over the ddc frequency
region, as shown in Fig. 2.
Step 2: In order to compensate the phase-shifting effect
of the two added zeros on the fundamental frequency
(± j 100π (1/s)), it is necessary to insert two poles. Two pos-
sible locations are: 1) inserting two conjugate poles between
the two zeros, based on Section II-C, which are shown by
p1 and p2 in Fig. 2 and 2) inserting two poles outside the
ddc frequency region. The only solution for this location is to
insert two poles on both sides of the ddc frequency region on
the real axis, which are shown by p1 and p2 in Fig. 2.
According to several simulation results obtained by chang-
ing the ddc time constant, better attenuation of ddc and
estimation of fundamental phasor can be achieved by the latter
location of poles (i.e., p1 and p2 ).
The resulting transfer function for the second-order complex
frequency filter is
(s − z 1 )(s − z 2 )
G 2 (s) = K . (4)
(s − p1)(s − p2 )
In order to prevent the phase shifting due to the pro-
posed filter, summation of zeros angles must be equal to the
JAFARPISHEH et al.: PHASOR ESTIMATION ALGORITHM BASED ON COMPLEX FREQUENCY FILTERS FOR DIGITAL RELAYING 585

summation of poles angles, at the fundamental frequency,
as shown in Fig. 2
α1 + α2 = β1 + β2
where
α1 = tan−1 (100π/32.5) = 84.09°
α2 = tan−1 (100π/77.5) = 76.14°
β1 = tan−1 (100π/x 1)
β2 = tan−1 (100π/x 2).
Substituting (6) into (5) yields
tan−1 (100π/x 1) + tan−1 (100π/x 2 ) = 160.23°.
Taking tangent from both sides of (7)
better attenuation of ddc and estimation of fundamental phasor
can be achieved by the latter location of poles, which is shown
in Fig. 3. The resulting transfer function for the fourth-order
(5)
complex frequency filter is
(s − z 1 )(s − z 2 )(s − z 3 )(s − z 4 )
G 4 (s) = K    . (13)
(s − p1 ) s − p1∗ (s − p2 ) s − p2∗
To prevent the phase shifting due to the proposed filter,
summation of zeros angles must be equal to the summation of
(6) poles angles, at the fundamental frequency, as shown in Fig. 3
α1 + α2 + α3 + α4 = β1 + β2 + β3 + β4 (14)
(7)
where

tan(tan−1 (100π/x 1) + tan−1 (100π/x 2 )) = −0.36. (8) α1 = tan−1 (100π/21.25) = 86.13°

After some trigonometric simplifications, we have α2 = tan−1 (100π/43.75) = 82.07°
(100π/x 1)+(100π/x 2) 100π(x 1 + x 2 ) α3 = tan−1 (100π/66.25) = 78.09°
= = −0.36.
1 − (100π/x 1)(100π/x 2) x 1 x 2 − (100π)2 α4 = tan−1 (100π/88.75) = 74.22°
(9) β1 = tan−1 ((100π − y1 )/x 1 )
Thus, the locations of the poles must satisfy (10) β2 = tan−1 ((100π + y1 )/x 1 )
β3 = tan−1 ((100π − y2 )/x 2 )
0.36x 1 x 2 +100π(x 1 + x 2 ) − 3600π 2 = 0
β4 = tan−1 ((100π + y2 )/x 2 ). (15)
Subject to: − 10 < x 1 < 0
x 2 < −100. (10) Substituting (15) into (14) yields
Step 3: The filter gain K is determined using
z-transformation. The Laplace variable s can be emulated tan−1 ((100π − y1 )/x 1 ) + tan−1 ((100π + y1 )/x 1 )
digitally as [11] + tan−1 ((100π − y2 )/x 2 ) + tan−1 ((100π + y2 )/x 2 )
s = 1 − z −1 = 320.51°. (16)

where By taking tangent from both sides of the above-mentioned

equation, (16) is rewritten as
z = e j ωt . (11)
Thus, the total filter gain must be set to unity, at the rated tan[tan−1 ((100π − y1 )/x 1 ) + tan−1 ((100π + y1 )/x 1 )
frequency (50 Hz), by choosing an appropriate value for the + tan−1 ((100π − y2 )/x 2 ) + tan−1 ((100π + y2 )/x 2 )]
filter gain K
= tan(320.51°) = −0.824. (17)
|G 2 (ω = 100π)| = 1. (12)
Thus, locations of poles must satisfy (18) as follows:

E. Designing Fourth-Order Complex Frequency Filter tan[tan−1 ((100π − y1 )/x 1 ) + tan−1 ((100π + y1 )/x 1 )
+ tan−1 ((100π − y2 )/x 2 ) + tan−1 ((100π + y2 )/x 2 )]
Similar to the proposed second-order filter, three steps
are required for designing the proposed fourth-order filter as = tan(320.51°) = −0.824
follows. Subject to: − 10 < x 1 < 0
Step 1: Four zeros of −21.25, −43.75, −66.25, x 2 < −100
and −88.75 (1/s) are chosen evenly over the ddc frequency
0 < y1  100π
region, as shown in Fig. 3.
Step 2: To compensate the phase-shifting effect of the four 0 < y2  100π. (18)
zeros on the fundamental frequency (± j 100π (1/s)), it is
necessary to insert four poles. Two possible locations are: Step 3: Similar to the design of the second-order filter,
1) inserting four poles between the four zeros and 2) inserting the total gain of the proposed fourth-order filter must be set to
four poles outside the ddc frequency region. The best solution unity at rated frequency (50 Hz), by choosing an appropriate
for the latter location is inserting poles on both sides of the value for K
ddc frequency region, as shown in Fig. 3. According to several
simulation results obtained by changing the ddc time constant, |G 4 (ω = 100π)| = 1. (19)
586 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 67, NO. 3, MARCH 2018
Fig. 4. Flowchart of the algorithm for the determination of poles for the
proposed filter.
F. Determination of Poles for the Proposed Filter
The following algorithm, which is shown in Fig. 4, is used to
determine the optimum locations for the poles of the proposed
filter. The algorithm is presented for the proposed fourth-order
filter.
To determine the optimum locations for the poles, the fault
current signal of (2) distorted with noise is used. The ddc
magnitude I0 is considered to be the maximum value, which
is equal to the magnitude of the fundamental component I1 .
Six different test signals (i 1 , . . . , i 6 ) with ddc time constants
of {0.5, 1, 2, 3, 4, 5} cycles are generated.
The total vector error (TVE) index is used, which is defined
in the IEEE C37.118.1 standard published in 2011 [30],
to choose the optimum locations for the poles. This index is
Fig. 5. Frequency responses for both of the proposed filters.
defined as [30]
| Xˆ1 − X 1 |
TVE = (20)
|X 1 |
where Xˆ1 and X 1 are the estimated and actual fundamental
phasors, respectively.
As shown in Fig. 4, in this algorithm, x 1 and y1 (see Fig. 3)
are varied based on the constraints of (18). As mentioned
in (18), the poles must be far from the fundamental frequency
j ω1 , not to affect the estimated phasor. Thus, the maximum
value of y1 (in Fig. 4) is set to j ω1 /10. For each pair of
(x 1 , y1 ), the other filter parameters are obtained using (18)
and (19). For each of the six test signals, the fundamental
phasor is estimated, and its maximum TVE is calculated.
For each filter, the maximum value among the maximum
TVEi s (i = 1, . . . , 6) is stored as maximum TVE (MTVE).
The filter with minimum value of MTVE is chosen, and its
parameters (x 1 , y1 , x 2 , and y2 ) are the optimum locations for
the poles of the proposed filter.
Using the algorithm in Fig. 4, −8 ± 10 j and −102 ±
43.16 j (1/s) are obtained for the poles of the proposed fourth-
order filter.
To determine the poles of the second-order filter, y1 and y2
are equal to zero (see Fig. 2). x 1 is varied from 0 to −10 with
steps of 0.1, and the other filter parameters are obtained from
(10) and (12). The other steps are the same as in Fig. 4. Using
the algorithm of Fig. 4, −8 and −103.94 (1/s) are obtained
for the poles of the proposed second-order filter.
The frequency responses for both the second- and fourth-
order complex frequency filters are shown in Fig. 5. As shown
in Fig. 5, the magnitude and phase angle of the proposed filter
are 1 and 0°, respectively, for frequencies higher than the rated
frequency (50 Hz). In other words, sinusoidal components
with frequencies higher than the 50 Hz pass through the
proposed filter without any magnification in their magnitude
and any phase shift in their phase angle, which is a significant
advantage. Therefore, the proposed complex frequency filter
can be used for special applications for the phasor estimation
of harmonic components in the presence of ddc, with no need
to readjust its parameters.
JAFARPISHEH et al.: PHASOR ESTIMATION ALGORITHM BASED ON COMPLEX FREQUENCY FILTERS FOR DIGITAL RELAYING 587

G. Proposed Algorithm Procedure

In this algorithm, the ddc is suppressed/removed by the
zeros of the complex frequency filter. The filter poles are
located at both sides of the ddc frequency region, as shown
in Figs. 2 and 3. The poles at the right side of the ddc fre-
quency region have very low damping, and their corresponding
signals are highly attenuated by DFT. The other poles located
at the left side of the ddc frequency region have very high
damping, and their corresponding signals are also significantly
attenuated by DFT.

III. T EST R ESULTS Fig. 6. Estimated fundamental magnitude and phase angle for the basic
signal with the longest ddc time constant and θ F = 0°.
To validate the performance of the proposed algorithm,
several test signals are used. The results are shown for both
the second- and fourth-order proposed filters.
The results are also compared with those of the mimic-DFT
method [11], which is a conventional filter-based method, and
a modified DFT-based method [25], which is a calculation-
based method. In [11], a high-pass mimic filter is used to
suppress the ddc. The fault current signal is passed through the
mimic filter and then through DFT, to estimate the fundamental
phasor. In [25], the Prony analysis is used to estimate the
ddc value. Then, by subtracting the ddc from the fault current
signal, the resulting signal is given to DFT for fundamental
phasor estimation. The time constant of the mimic filter used in
this paper (for comparison) is chosen to be two cycles [11]. For Fig. 7. Calculated performance indices for the cases of θ F = 0°.
all the test signals, the number of samples per cycle N is set
to 16, which is equal to the sampling frequency of 800 Hz, for
for the case of θ F = 0°, the ddc magnitude has the max-
50-Hz fundamental frequency. The input signals are prefiltered
imum value (which is equal to the fundamental component
by the second-order Butterworth low-pass filter with a cutoff
magnitude I1 ). At θ F = 45°, the ddc magnitude is equal to
frequency of 350 Hz (as shown in (2)), to avoid the aliasing
0.707I1. In a similar way, the ddc magnitude is equal to zero
phenomenon. For all of the computer-simulated test signals,
for θ F = 90° [13], [14], [23].
the fundamental magnitude I1 and the phase angle θ1 are
The fundamental phasor is estimated for each of the 18 men-
chosen to be 1.0 (p.u.) and 60°, respectively [21], [26].
tioned basic signals, using the proposed, modified DFT and
In sequel, several test signals are used to evaluate the
mimic-DFT algorithms. Since it is not possible to show
performance of the proposed algorithm and compare it with
the fundamental estimated phasor for all the 18 mentioned
the mentioned methods in [11] and [25] from the viewpoints of
basic signals, the estimated fundamental phasor is drawn
speed of convergence and robustness against noise, harmonics,
in Fig. 6 for the basic signal with the longest ddc time constant
multiple ddc components, and off-nominal frequency.
(5 cycles or 100 ms) and zero fault inception angle (the
maximum value for ddc magnitude).
A. Test Signals With Fundamental Component and ddc Four performance indices of rise time t R , settling time t S ,
In this section, the fault current signals containing fun- percentage of overshoot PO and TVE are used for comparison.
damental component and ddc, which are called basic The definitions of these indices are given in detail in many
signals [13], [26], are applied to the proposed and other papers, such as [23], [26], and [30].
understudied algorithms For comparison, each of the 18 basic signals is applied to
  the proposed and other mentioned algorithms to estimate the
2π
i 1 [n] = I0 e−nt /τ − I1 cos n + θ1 fundamental phasor. The performance indices are calculated
N
  for each of the estimated magnitude and phase-angle wave-
−nt /τ 2π
= I1 cos(θ F )e − I1 cos n + θ1 (21) forms. The results are shown in Fig. 7, for the cases of zero
N fault inception angle θ F = 0°. Since the phase angle estimated
in which θ F denotes the fault inception angle. As mentioned by mimic-DFT has phase-angle shift, the performance indices
earlier, the ddc parameters are not constant and may vary based are not depicted for its estimated phase angle. The maximum
on the fault impedance and time [11], [13]. To investigate the TVE is also shown in Fig. 8, for θ F = 0°.
effect of variations in ddc parameters, 18 different basic signals The performance indices are calculated and shown in
are generated by selecting the ddc time constant among: Figs. 9 and 10, for the cases of θ F = 45°.
{10, 20, 40, 60, 80, 100} ms (or {0.5, 1, 2, 3, 4, 5} cycles) and For θ F = 90°, the ddc magnitude is equal to zero. This
fault inception angle among: {0°, 45°, 90°}. As seen in (21), is the simplest case for the phasor estimation algorithms.
588 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 67, NO. 3, MARCH 2018
Fig. 8. Calculated maximum TVE for the cases of θ F = 0°.
Fig. 9. Calculated performance indices for the cases of θ F = 45°.
Fig. 10. Calculated maximum TVE for the cases of θ F = 45°.
TABLE I
P ERFORMANCE I NDICES FOR THE C ASE OF θ F = 90°
For this case, the performance indices of the proposed and
other understudied algorithms are almost similar, which are
given in Table I.
For comprehensive comparison, the maximum values of
performance indices and also the maximum error of the
estimated magnitude and phase angle are obtained among all
six ddc time constants and three ddc magnitudes (all 18 basic
signals) and given in Table II.
As shown in Figs. 7–10, the performance of mimic DFT is
acceptable if the time constants of ddc and mimic filter are
close to each other. On the other hand, the indices calculated
TABLE II
M AXIMUM OF THE I NDICES AND E RROR A MONG THE 18 C ASES
for the modified DFT are not constant and change by ddc
time-constant variations. Therefore, the convergence speed and
accuracy for both modified DFT and mimic-DFT methods
are influenced by time-constant variations, whereas the four
performance indices for the proposed algorithm are small
and independent to the variations of the ddc parameters,
which are significant advantages. Also, as shown in Table II,
the maximum TVE of the proposed fourth-order filter among
all the 18 cases is 0.6823%, which is less than the proposed
second-order and other algorithms. It is also less than the
threshold of 1%, which is suggested by [30].
Thus, the proposed algorithm estimates the fundamental
phasor faster and more accurate than the other understudied
algorithms. It is also less influenced by the variations of the
ddc parameters. These advantages are due to the attenuation
of zeros of the filter, which are located at the ddc frequency
region.
Based on Figs. 7–10 and Tables I and II, for all algo-
rithms, as it is expected, the worst/maximum values of the
four performance indices are at θ F = 0° (maximum ddc
magnitude). The performance indices of the proposed and
other understudied algorithms improve by decreasing the ddc
magnitude or increasing the ddc time constant. Therefore,
in Sections III-B–III-E, the results are depicted for θ F = 0°
and ddc time constant of five cycles [13], [14], [23], [24], [26].
B. Presence of Multiple ddc Components
In practice, the fault currents, as shown in (1), are passed
through the CTs before being used by relays. Because of CTs
burden, another ddc component may be added to the fault
current signal, which may cause uncertainties on fault current
signals and consequently on phasor estimation [13], [26].
Therefore, the CT output fault currents may include two
ddc components. Since the burden of CTs is usually small,
its corresponding ddc component has large time constant.
So, this second ddc remains for several cycles, which causes
significant error in phasor estimation methods.
JAFARPISHEH et al.: PHASOR ESTIMATION ALGORITHM BASED ON COMPLEX FREQUENCY FILTERS FOR DIGITAL RELAYING 589

TABLE III
M AXIMUM OF THE I NDICES A MONG THE 18 C ASES IN THE
P RESENCE OF M ULTIPLE DDC C OMPONENTS

Fig. 11. Estimated fundamental magnitude and phase angle in the presence
of multiple ddc components.

The following test signal with multiple ddc components is

used to evaluate the performance of the proposed algorithm,
due to CTs burden [13], [14], [26]:
i 2 [n] = I1 cos(θ F )e−nt /τ p − 0.1I1 cos(θ F )e−nt /τs
 
2π
− I1 cos n + θ1 . (22)
N
The fault inception angle θ F is chosen to be zero, which
corresponds to maximum ddc magnitude. The time constant
of the first ddc component τ p is also assumed to be five
cycles. The second ddc time constant τs is chosen to be
20 cycles [13], [26]. The estimated fundamental magnitude
and phase angle are shown in Fig. 11.
As shown in Fig. 11, unlike the modified DFT and mimic
DFT, for the estimated magnitude and phase angle, the per-
formance indices of the proposed algorithm are significantly
small. However, the proposed fourth-order filter provides faster
ddc suppression and more accurate results than the proposed
second-order filter. Therefore, in the presence of multiple ddc Fig. 12. Estimated fundamental magnitude and phase angle in the presence
components, the proposed algorithm estimates the fundamental of harmonics and noise.
phasor faster than the other mentioned methods. The attenua-
tion of the second ddc is done by the zeros of the proposed
assumed to be 20 dB [13], [21], [26]. Fig. 12 shows the
filters. It is worth to mention that by inserting additional
estimated fundamental magnitude and phase angle versus time.
zeros in the vicinity of the second ddc frequency, the filter
As shown in Fig. 12, since the mimic filter amplifies
performance will be improved.
harmonics, interharmonics, and noise, its estimated phasor has
The maximum values of performance indices are obtained
large error. The maximum TVE of the proposed fourth-order
among all six ddc time constants and three ddc magnitudes
filter is 0.829%, which is less than the proposed second-order
(18 cases) and given in Table III. The results confirm the
and other algorithms. It can be concluded from Fig. 12 that
superiority of the proposed algorithm in the presence of
better harmonic and noise rejection can be achieved by the
multiple ddc components.
proposed algorithm.
The maximum values of performance indices are obtained
C. Presence of Harmonics and Noise among all the 18 cases and given in Table IV. The results
Due to CT burden, the CT core may be saturated and injects confirm that the proposed algorithm has a better performance
harmonics and noise into CT output signal. Therefore, in this in the presence of harmonics and noise.
section, the proposed algorithm is verified in the presence of
harmonics and noise. The employed test signal is [13], [21]
D. Effects of the Uncertainties Due to Measurement Chain
 I1
N/2−1  
2πk The current signals are passed through the CT and analog-
i 3 [n] = I1 e−nt /τ − cos n + kθ1
k N to-digital converter (A/D) before being applied to the phasor
k=1
estimation algorithms. Therefore, the effects of uncertainties
+ White Random Noise. (23)
due to CT and A/D are studied in this section.
Similar to Sections III-A and III-B, the largest value is As mentioned in Sections III-B–III-C, CT may add extra
considered for the ddc time constant τ . The fault inception ddc component and inject harmonics to the current signals.
angle θ F is also set to 0°. The signal-to-noise ratio is also As shown in Figs. 11 and 12, the proposed algorithm is less
590 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 67, NO. 3, MARCH 2018

TABLE IV
M AXIMUM OF THE I NDICES A MONG THE 18 C ASES IN
THE P RESENCE OF H ARMONICS AND N OISE

Fig. 13. Estimated fundamental magnitude and phase angle during off-
nominal frequency condition.

TABLE VI
M AXIMUM OF THE I NDICES A MONG THE 18 C ASES
D URING O FF -N OMINAL F REQUENCY C ONDITION

TABLE V
C ALCULATED M AXIMUM TVE (%) FOR D IFFERENT
Q UANTIZATION L EVELS

influenced by these components.

CTs may also produce very small magnitude and phase-
angle errors. These errors must be compensated before apply-
ing the signals to the phasor estimation algorithms [31].
Quantization error of A/D is the other uncertainty. To eval-
off-nominal frequency condition, may result in large error in
uate the effect of this error, the previous test signal is passed
phasor estimation methods [23]. To test the proposed algorithm
through an A/D with different quantization levels. The A/D
during off-nominal frequency condition, the signal of (23) is
output signal is applied to the algorithms for phasor estimation,
used by altering its power frequency from 50 to 49.5 Hz.
and the maximum TVE is calculated and shown in Table V.
The estimated fundamental magnitude and phase angle are
It can be concluded from Table V that the phasor estimation
shown in Fig. 13, during off-nominal frequency condition.
error due to quantization is negligible, for all the algorithms.
It can be concluded from Fig. 13 that the performance of
In practice, there is an uncertainty due to deviation of zeros
both modified DFT and mimic-DFT methods is degraded dur-
and poles of the proposed complex-frequency filter from their
ing off-nominal frequency condition. The fundamental phase
optimum locations. To evaluate the effect of this uncertainty,
angle estimated by the mimic filter has a dc error, which is
the locations of the zeros and poles are deviated from their
the common disadvantage of the filter-based phasor estimation
optimum locations by an additive Gaussian noise (with a
algorithms. The maximum TVE of the proposed fourth-order
variance of 0.1), using the test signal of (23). It is observed that
filter is 0.873%, which is less than the proposed second-order
the maximum TVE is slightly increased from 0.829% (of the
and other algorithms. As an advantage, the performance of
optimum locations) to 0.836%. This includes that the proposed
the proposed algorithm is still satisfactory during off-nominal
algorithm has satisfactory performance under this uncertainty.
frequency condition. The reason is related to the frequency
response of the proposed filter (see Fig. 5), which has the
E. Off-Nominal Frequency Condition same gain and phase angle for frequencies around the rated
During some transient oscillations, the power frequency frequency (50 Hz).
may slightly deviate from its rated value. This is due to The maximum values of performance indices are obtained
imbalances between loads and generations, starting and shut- among all the 18 cases and given in Table VI. The results
ting down of generators, and the commutation of large loads. confirm the superiority of the proposed algorithm during
This situation (power-frequency deviation), which is called off-nominal frequency condition.
JAFARPISHEH et al.: PHASOR ESTIMATION ALGORITHM BASED ON COMPLEX FREQUENCY FILTERS FOR DIGITAL RELAYING
Fig. 14. Fault current signal generated by EMTP.
Fig. 15. Estimated fundamental magnitude and phase angle for the EMTP-
generated fault current signal.
Fig. 16. Estimated magnitude and phase angle, after a cycle from the fault
inception time.
F. EMTP-Generated Fault Current Signal
In this section, the performance of the proposed and other
understudied phasor estimation algorithms is evaluated by
using usual fault current signals that might be happen in power
systems. For this purpose, a fault current signal due to a
single-phase fault at the midpoint of a 220-kV transmission
line with 103.47 km long is generated by the Electromagnetic
Transient Program (EMTP) and applied to the proposed and
other mentioned algorithms [19]. The fault current signal is
shown in Fig. 14. The estimated fundamental phasor is shown
in Fig. 15. To magnify the oscillations, both of the estimated
magnitude and phase angle in Fig. 15 are redrawn in Fig. 16,
after a cycle from the fault inception time.
Figs. 15 and 16 show that the performance indices of the
proposed algorithm are considerably smaller than the modified
DFT and mimic-DFT methods.
IV. C ONCLUSION
This paper presents a new filter-based algorithm for fun-
damental phasor estimation, based on the proposed complex
591
frequency filter. The zeros of the proposed filter sup-
press/remove the ddc. The filter poles must compensate the
phase-shifting effect of the zeros. The design of the proposed
complex frequency filter is presented in three steps.
Based on employing various test signals to the proposed and
other understudied phasor estimation methods, the proposed
algorithm provides faster convergence besides less dependence
to variations of the ddc parameters. The proposed algorithm
has robust performance during off-nominal frequency condi-
tion and is less influenced by harmonics, noise, and multiple
ddc components. Moreover, it requires less computation bur-
den than the calculation-based phasor estimation algorithms.
The proposed fourth-order filter results in faster ddc sup-
pression and more accurate phasor estimation than the second-
order filter.
The proposed algorithm can also be used for the phasor
estimation of harmonic components in the presence of ddc
without readjusting the complex frequency filter parameters.
ACKNOWLEDGMENT
The authors would like to thank Siamak Jafarpisheh from
the Department of Electrical and Computer Engineering,
Isfahan University of Technology, Isfahan, for his contribution
to this paper.
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Babak Jafarpisheh (S’16) was born in Isfahan,
Iran, in 1988. He received the B.Sc. degree (Hons.)
from the Isfahan University of Technology, Isfahan,
in 2010, the M.Sc. degree (summa cum laude) from
Bu-Ali Sina University, Hamadan, in 2012, and the
Ph.D. degree (summa cum laude) from the Univer-
sity of Isfahan, Isfahan, in November 2017, all in
electrical engineering, respectively.
Since 2016, he has been teaching some courses
including power system protection and computer
relaying, electrical machines, and special electrical
machines for undergraduate (B.Sc.) students with the Department of Electrical
Engineering, University of Isfahan. His current research interests include
smart grids, wide area monitoring, protection and control, power system
protection and digital/computer relaying, signal processing applications in
power systems, microgrids, renewable energies, control and identification
systems, power quality of power systems, and optimization in power systems.
Dr. Jafarpisheh has been a member of the Power System Planning Center,
Esfahan Regional Electric Company (EREC), Isfahan, as a Consultant Engi-
neer, since 2012. He has been involved in several research and development
projects for EREC. He is a Reviewer of the IEEE T RANSACTIONS ON
I NSTRUMENTATION AND M EASUREMENT and he has been reviewing several
papers for this journal.
Seyed M. Madani (S’97–M’03–SM’17) received
the B.Sc. degree from the Sharif University of
Technology, Tehran, Iran, in 1989, the M.Sc. degree
from the University of Tehran, Tehran, in 1991, and
the Ph.D. degree from the Eindhoven University of
Technology, Eindhoven, The Netherlands, in 1999,
all in electrical power engineering.
From 2000 to 2005, he was with Texas A&M Uni-
versity, TX, USA, the University of Puerto Rico, San
Juan, Puerto Rico, and the University of Wisconsin
at Madison, WI, USA, as an Assistant Professor or a
Visiting Professor. From 2005 to 2011, he was with the Isfahan University of
Technology, Isfahan, Iran, as an Assistant Professor. He is currently an Asso-
ciate Professor with the University of Isfahan, Isfahan. His current research
interests are power system protection, microgrids, renewable energies, and
electric drives.
Farzad Parvaresh (S’99–M’07) received the B.S.
degree in electrical engineering from the Sharif Uni-
versity of Technology, Tehran, Iran, in 2001, and the
M.S. and Ph.D. degrees in electrical and computer
engineering from the University of California at
San Diego, La Jolla, CA, USA, in 2003 and 2007,
respectively.
He was a Post-Doctoral Scholar with the Center
for Mathematics of Information, California Institute
of Technology, Pasadena, CA, USA, from 2007 to
2008, and a Visiting Researcher with the Information
Theory Research Group, Hewlett-Packard Laboratories, Palo Alto, CA, USA,
from 2010 to 2012. He is currently an Assistant Professor with the Department
of Electrical Engineering, University of Isfahan, Isfahan, Iran. His current
research interests include coding theory, information theory, and wireless
communication networks.
Dr. Parvaresh received the Best Paper Award from the 46th Annual IEEE
Symposium on Foundations of Computer Science in 2005 and the Silver
Medal in the 28th International Physics Olympiad in 1997.