S MicrRocHiIP 193.423 93C06/46 256 Bit/IK 5.0V CMOS Serial EEPROM FEATURES + Low power CMOS technology + 1 btmemory organization = 6x 16it organization (93006) +64 16 bit organization (99048) + Single 5 vot oly operation + Sottimed ERASE and WRITE cytes + Automatic ERASE before WRITE + Power onfot data protection culty + 1,000,000 ERASE/WRITE cycles guaranteed + Data Retention > 40 years + pin DIP or SOIC package + Avatabl fot extended temperature ranges: + Commeriak °C t0 470°C 1 Industiak 40°C f0 485°C + Aulomatve: 40°C to +1250 + 2ms program eycle time DESCRIPTION ‘The Microchip Technolegy Ine. 9300846 family of ‘Serial Elocicaly Eraeable PROMS are configured i a ‘x8 organization. Advanced CMOS technology makes these devices dea for low-powor non-volatile memory ‘plleations. The S2C06/4 i avaabo i the standard ‘pin DIP and surface mount SOIC packages. The ‘B9C48X comes as SOIC only “These devices ofr fast (1 ms) byt witeandextended (40°C wo 6125°C) temperature operation. tis recom ‘mended that all other appiaions use Microchip's 46 (© S005 Marat Tecony i, PACKAGE TYPE, sacs 80006 2D vee 7H ne De sD ve e900 89¢46 ORD vee 72 wo eT no SE ves BLOCK DIAGRAM. shove 7B ve sf 00 stoo Dstt s7o6-pape 4193C06/46 1.0 ELECTRICAL CHARACTERISTICS IN FUNCTION TABLE 1.1 Maximum Ratings* Husceet oo eer 0s |chipseeat Alinpus and ouputs wit. Vos. 6 10 Vee +1.0¥ cux | seat clock Stage tempera. vee fSC10 80'S ae ee Anbiontempartre wit power apied 65°C t +1256 Soldeng temperature oflad (10 snd 4900 D0 [ate Ou 0 prtocton ona pins sence vss |erouns ‘Note: Suse sore Rost ned ur Macnam args NC | No Connect Ne ntmal {igen ee treo putin fe avon woe ty [Connection ‘Sr cenen stove ese eed he wana tts Sts seaictan set mote. Exaer lo enna rg ee _|+5V Power Supriy ‘iran or enone pees may aft Sve ret TABLE 1-2: __DG CHARACTERISTICS Vos = 5 (210%) . Gonmeriak Tamb= OCW +706 Industiat = Tamb= 40°C 4850. Automate: __Tamb = 40°C to +425°C (Note 3) Parameter symbot_| min | Max | Unite Conditions Ves detector tweshold ve | 28 | as |v High level input votage va 20_|Veors| Vv Low evel input votage ve | 03 | oe | Vv High evel output votage vou | 24 | — | V_|ton=-s00ua Low love output votage vou = [ee [v_fia=32ma input leakage curent w = [Hee vn = ov to veo ote [Output eskage curent ko = [10 [aa [Vour= ov Voo Note) Itemal capactance cor” | — | 7 | pr | ¥nwvour=ov (ote a) (atlinpusiououts) : Tab = 425°C, f= 1 Mie [Operating current (alimades) | tcowite | — | 4 | mA [Foust Nite, Vor o55V [Standby current eos | — | 100 | pa [os=ov,vec=ssv ‘Nolet: Inimal resistor pallu at Pin 6 [Noto 2: This parameters erocaly sampled and not 100% tested, [Note 3: For operation above &5°C, endurance ls fated at 10,000 ERASE WRITE cycles FIGURE 1-1: SYNCHRONOUS DATATIMING KXXXXXXK) ‘DSN page 4.2 (91995 marecipTeghciogy na,93C06/46 Ac CHARACTERISTICS Parameter Symbol] win] wax [unity [condone creep fax 7 [owe esa on cs eckiow ne Faas ews) eee cp tcp ae ease] a ne chp sect hte ewe on] = ip leone rex [100 [=| ae Ea pt ati tno oa iro) == Ean Roo ine Tow [100 [=| ae Bata cut ay te Te_[ — [a0 | re [exe tg oan oupt suai neem GS=ton) | Tez [0 | 100 | [Dua ope dae tne (em utc) | oor | 0 | 00 | ne Sia val tire ofa cae lee ee Pre ee tre a Ese anata) | we] =~ 2 | me 5 | me |rorerat andra aoe ee a a 2.0 PIN DESCRIPTION CLK cycles are not required during the self-timed Wine a, uo ERASEMTATEN be 24 chinSalectios ter ctcton ot sat concton te specs un beret ceases spacey COW ton vans lvl ace th dvs, ALOM i! dese eemeee ees eae | ioe dawmminpeoct mas enre ae Perce piel tayape ee Rar crepe prec mege ae| Pet pete peter oe a PT om ce rtomcr treo a ‘CS input signal. If CS is brought LOW during a pro- ee toe ee as {1am oyCle, the device wil go into standby mode as Cae Inputs waling for a new start con oe ‘s00n as the programming cycle is completed. = CS must be LOW for 100 ns minimum (Test) between ‘Note: CS must go LOW between consecutive ‘consecutive instructions. If CS is LOW, the intemal ——— instructions. contol logis held a RESET status, 22 Serial clock (CLK) ‘Tha Seria Cock is used to synchronize the commun caton between a master device and tho 93C0046. Opcode, address, and data bis are cocked in on the postive edge of CLK. Data bisa leo clocked outon tho postive edge of CLK. CCLK can be stopped anywhere in the transmission ‘sequence (at HIGH or LOW level) and ean be contin: ted anytime (wth respect to clock HIGH time (Tom) ‘and clock LOW tine (Tex), This gives the controling master treedom in preparing opeode, adress and ata, CtKisa“Dont Care" CSis LOW (device deselected. WS is HIGH, but START condton has not been delectod, any number of cock cyeles can be received by the device without changing Is status (Le, waling for START condor), 23° Datanion Data In Is used to clock in a START bit, opcode, ‘adsres, and data synchronously wih the CLK input 24 Data Out(p0) Data Out is used in the READ mode to output data synchronousy with the CLK input (TP alter the posh This pin also provides READY/BUSY status iforma- tion during ERASE and WRITE cycles. READYEUSY ‘talus infomation is avalable on the DO pin if CS is ‘brought HIGH ater being LOW for minimum chip select {LOW tne (Fest) rom tha faling od fh CL which clockedin the last D bit (00 for WRITE, AO for ERASE) ‘and an ERASE or WRITE operation has been inated. a ee ‘©1885 doco Teena te, S111 756 page 2393C06/46 a The status signal isnot avaliable on 00, i CS Is held LOW or HIGH curing the entre WRITE or ERASE ‘yee. In al other cases DO isn the HIGH-2 mode It satus is checked aftor the WAITEIERASE cyce, poullup resistor on DO Is requled to read the READY sonal and 00 can be connected together to perform a3 Wire terface (CS, CLK, BUDO). INSTRUCTION SET- 93606 Care must be taken with he leading dummy zero which 's ‘urputed ‘after a READ command has ‘been detected. ‘Also, the contoling device most not dive the DIDO bus curing Erase and Write cycles I th READYIBUSY status inormatin is ouputed by the coe, = “opeose F a Teg ck ination | sete | QPFEGE eras jour | Rescue roe 7 SoA AT iso 2 WATE mH 9-0-4 AE ATAD “POVEST) zs ERASE. cH oo AL AEAT AD 7 (OWEEY) 3 EWEN. a To KK = Tighe 3. fEWOS oo oe = gh 3. ERAL eee. = BOvaSTy 3 Waa oe ore xX x] Oise | RV 2 INSTRUCTION SET- 93646 5 ‘peace ae tamberot ] omy Req clk Instruction oror re Dut oot | "Selon ERE oe 7 Tso 7 ware 1 [AS ALAS ALA Ao_| 15-09 —OVEBSH 25 ERASE: S| as na a ae AT AD = POVEEY 2 EWEN ook ee = High = EWS 08 [ “oo x = igh = Er ooo POVEST] = WRAC oo [eK | Boe] OH 2 3.0 FUNCTIONAL DESCRIPTION 34 START Condition ‘Tho START bit is detected by the device if CS and DI are both HIGH with aspect othe postive edge of CLK forthe rst ime. ‘Before START conditions detected, OS, CLK, and Ot may change in any combination (except to that of a START cordon), wihout resulting any device oper laton (READ, WRITE, ERASE, EWEN, EWDS, ERAL, land WRAL). As soon a5 CS is HIGH, the device fe no longer inthe standby mode. An instruction folowing a START consti wil ony be lexecutod ithe requved amount of opcode, adress and data bits for any particular instruction a ioeked in. [Alter execution ot an insrvton (Le, clackin or out of the last required address or data bi) CLIC and Ol become dont are bis unl a new stat condition is detected 32 pupo Its possibi to connec the Data In and Data Out pins together. However with this configuration tis possible for a “bus conflict to eccur during the “dummy zara thatprecedes he READ operation, ADIs a logic HIGH lovel. Under such a contin the votage love seen at Data Outs undetined and will Sepend upon te relative Impedances of Data Out and the signal sour diving ‘AD. The higher the current sourcing capability of AQ, the higher the veliage atthe Data Oxt pn 33 Date Protection. During power-up, al medes of operation are inhibited ‘ntl Yer has reached 2.8. During power-down, tha source data protection ceuity acts to nbRall modes wen Vec has fain below 2.8. ‘The EWEN and EWDS commands ive addtional pro- teofon against acclcentally programming during nor ‘mal operation. Aor powerup, tho davice Is automaticaly in the EWDS mode. Therefore, an EWEN neructon mustbo pertomed before any ERASE or WRITE insiucton ‘canbe executed, Alter programming is completed, tho Ew0Sinsrucionofes added protection aginst unin- tended data changes. ee ‘OSH11708 gogo 4.36 1 1905 Micreap Tectnsogy ne93C06/46 34 READ Mode. ‘The READ instruction outputs the serial data of the dressed memory location onthe DO pin. Acura ‘i (ogical 0) precedes the 16-58 output sting. The ‘output data changes curing the HIGH state ofthe sys- tem clock (CLI. The dummy bis output TPD after tha postive edge of CLK, nich was used to clock In the last adress bit (AO), Therelore, care must be taken If Dl and 00 are connected together aa a bus conteiion wil occu for one cock eel if AO has bean ‘DO will go into HIGH-Z mode with the positive edge of the next CLK cyto. This follows the output ofthe ast data bit 09 or the iow going edge of CS, which ever ‘curs fet. 'DO remains stable between CLK cyele for an ualin- ied time as long as CS stays HIGH. ‘The most signieant data bit (O15) is always output {ist followed by the lower signifcant bts (014 -D0). FIGURE 2-1 READ MODE 25 WRITE Mode ‘The WRITE instuction fs flowed by 16 bis of data which ae writen into the specified adress. The most ‘signieant data bit (O18) has to be clocod in fre, o- lowed by he lower signiicant data its (O14 Dd). ‘aWAITE instucon i recogrizedby he devi anal dala bits have been cocked in, the davies performs an fuiomatc ERASE cycle on the speciied ascress belore the data are wien, The WRITE oyele Is com Pletay seltimed and commences automaticaly ator tho eng edge ofthe CLK for the last ca it (00). “The WRITE cycle takes 2 ms maximum. © 1985 MiecipTechalogy e, DSHTT Tab pape 43593C06/46 36 ERASE Mode ‘The ERASE instruction forces all the dala bts of the specified adioss to logical 1s". The ERASE clo is Completely solttmed and commiances automaticly ‘ser the fst across bt haa been clocked i, ‘The ERASE eyce takes 1 ms maximum. FIGURE 9-3: ERASE MODE 3.7 ERASE/WAITE Enable/Disable. (EWEN. EWDS) ‘The device Ie automatialy in the ERASEAWRITE Disable modo (EWDS) ater power-up. Thersfore, ‘an EWEN instruction has tobe performedbetoe any ERASE, WRITE, ERAL, WRAL instruction is exa- ‘cuted by the device, For added data protection, the device shoud be put inthe ERASE/WRITE Disa ‘mode (EWDS) alter programming operations ar completed. FIGURE 5-4: _ERASE/WRITE ENABLE/DISABLE ew nsTavcrion onsTaNDBY 30) — ee DSHNTTVR gana 4:38 (©1895 Merotp Teomoloy me.93C06/46 —— eee 3.8 ERASE AlL(ERAL) 7 e ‘Tho entre chip wil be erased to logical "Is" this instuction is recov by the device and iis nthe EWEN mode. The ERAL cycles completaysetined ‘and commences after the last dummy acess bit has 7 been clocked in EERAL takes 15 ms maximum, FIGURE 3. ERASE ALL 39° WRITE alownaL ol Tie WRAL covet Rea naomi] The eno cipwt be weit win th data speed SSE cree ace. Ta hat command "The WaAl Sys camouy se Wea acta mit be preceded ya Eedandcormences aero sng sauct NCU RAL incon and he cin ‘for the last data bit (D0). WRAL takes 15 ms maxi- Status in, both C99 % a, mm ‘ee WRAC scons reo ting andr coco Paent FIGURE 3-6: WRITE ALL ee (91888 ccs Teena na93C06/46 93¢06/46 Product Identification System “oder orto cian information, a. on ping deve, eat ute Ines prt umbare, andl to he aca othe ted ‘sins ote 93c06"6 - Prose P00 mt ouay) Pras SOI (120 mi Gay) 1 7 T____| Peta: sh Temperature Bunk = range 1 2 So [SERDI 900 mi By) Boe Pale SO fac? mi Bod) 2 pews Devles: contiguation socte ik cMos Sera cePnoM 546K 1K CluDs Seral EEPROM in aamate pout (SM package) sacost EwoS See EEPROM Cape and Ret 0646T CMOS Sel EEPROM (ape ana Rea) s90H0xT GMOS Seal EEPROM (Tape and Rea) ‘Sales and Support Prose sapated by a pecinay Data Shes may psy Fave an erala faa Gosirbg rr apenonal Taree Aw] rence woharcinds To atumina ta era el eters pare devin, ese orate own ‘Noor oes ero aie fice 2.he MerocipCoorte ante Cala US. AX (62) 7007277 she Merci But oa a oro Campus ner Convene mamtwatip NOT ese Please spect when dee, rovsnct cn ard Dla Sheet (rlie Lert you are ung Forster! von efematn Ss oyrade lar Mine Dero Yon, ats ca 803 75 23450. 602. 705-722, Sit gage 98 1 1985 Merah Tectnoioay ne