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Sequential Logic Implementation: Models For Representing Sequential Circuits
Sequential Logic Implementation: Models For Representing Sequential Circuits
L’ R’ / TR, F
CS 150 - Fall 2005 – Lec #7: Sequential Implementation – 2
Specifying Outputs for a Moore Machine
1/0
Logic
inputs Combinational inputs outputs
for
logic outputs
for Logic Combinational
Next State reg outputs reg
for logic for
outputs Next State
A
out
D Q
B
clock
Q
A
D Q out
B
D Q
clock
Q
A
D Q
B
D Q
Q
clock
out
A
D Q D Q
Q Q
B
D Q D Q
Q Q
clock
Current State
CS 150 - Fall 2005 – Lec #7: Sequential Implementation – 8
Verilog FSM - Reduce 1s Example
0 1
1
two1s
[1]
Announcements
N
Vending Open
Coin Machine Release
Sensor FSM Mechanism
D
Clock
Inputs: N, D, reset N D N D
Output: open chute
S4 S5 S6
S3
Assumptions: [open] [open] [open]
Assume N and D asserted
N
for one cycle
Each state has a self loop S7
for N = D = 0 (no coin) [open]
D1 = Q1 + D + Q0 N
D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D
OPEN = Q1 Q0
One-hot Encoding
0¢
N’ D’ 0¢ N’ D’/0
[0]
N N/0
D 5¢ D/0
N’ D’ 5¢ N’ D’/0
[0]
N N/0
10¢
D N’ D’ D/1 10¢ N’ D’/0
[0]
N+D N+D/1
15¢
Reset’ 15¢ Reset’/1
[1]
endmodule
car sensors
highway
state description
S0 highway green (farm road red)
S1 highway yellow (farm road red)
S2 farm road green (highway red)
S3 farm road yellow (highway red)
CS 150 - Fall 2005 – Lec #7: Sequential Implementation – 27
S0
TL•C / ST TS / ST
S0: HG
TL+C / ST
S1: HY TS' S1 S3 TS'
S2: FG
S3: FY TS / ST TL+C' / ST
S2
(TL+C')'
SA1: HG = 00 HY = 01 FG = 11 FY = 10
SA2: HG = 00 HY = 10 FG = 01 FY = 11
SA3: HG = 0001 HY = 0010 FG = 0100 FY = 1000 (one-hot)
Seq
N
Q1
DQ
Seq
D
Open
DQ
Com
Reset
Q0
DQ
Seq
N
Q1
DQ
Seq
D
OPEN Open
DQ
Seq
Reset