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21295c PDF
21295c PDF
CH0 1 16 VDD
CH1 2 15 VREF
MCP3008
CH2 3 14 AGND
CH3 4 13 CLK
CH4 5 12 DOUT
CH5 6 11 DIN
CH6 7 10 CS/SHDN
CH7 8 9 DGND
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VREF = 5V,
TAMB = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for
VDD = 5V, TAMB = 25°C.
Parameter Sym Min Typ Max Units Conditions
Conversion Rate
Conversion Time tCONV — — 10 clock
cycles
Analog Input Sample Time tSAMPLE 1.5 clock
cycles
Throughput Rate fSAMPLE — — 200 ksps VDD = VREF = 5V
75 ksps VDD = VREF = 2.7V
DC Accuracy
Resolution 10 bits
Integral Nonlinearity INL — ±0.5 ±1 LSB
Differential Nonlinearity DNL — ±0.25 ±1 LSB No missing codes over
temperature
Offset Error — — ±1.5 LSB
Gain Error — — ±1.0 LSB
Dynamic Performance
Total Harmonic Distortion — -76 dB VIN = 0.1V to 4.9V@1 kHz
Signal to Noise and Distortion — 61 dB VIN = 0.1V to 4.9V@1 kHz
(SINAD)
Spurious Free Dynamic Range — 78 dB VIN = 0.1V to 4.9V@1 kHz
Reference Input
Voltage Range 0.25 — VDD V Note 2
Current Drain — 100 150 µA
0.001 3 µA CS = VDD = 5V
Note 1: This parameter is established by characterization and not 100% tested.
2: See graphs that relate linearity performance to VREF levels.
3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”,
for more information.
TCSH
CS
TSUCS
THI TLO
CLK
TSU THD
DIN MSB IN
TDO TR TF TDIS
TEN
DOUT NULL BIT MSB OUT LSB
tF CS
tR
1 2 3 4
CLK
Voltage Waveforms for tDO
DOUT B9
CLK tEN
tDO
Voltage Waveforms for tDIS
DOUT
VIH
CS
DOUT 10%
Waveform 2†
* Waveform 1 is for an output with internal
conditions such that the output is high,
unless disabled by the output control.
† Waveform 2 is for an output with internal
conditions such that the output is low,
unless disabled by the output control.
1.0
1.0
0.8 VDD = VREF = 2.7 V
0.8
0.6 0.6
0.4 0.4
Positive INL
INL (LSB)
INL (LSB)
0.2 0.2 Positive INL
0.0 0.0
-0.2 Negative INL -0.2 Negative INL
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1.0 -1.0
0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100
FIGURE 2-1: Integral Nonlinearity (INL) vs. FIGURE 2-4: Integral Nonlinearity (INL) vs.
Sample Rate. Sample Rate (VDD = 2.7V).
1.0
1.0 VDD = VREF = 2.7 V
0.8
0.8 fSAMPLE = 75 ksps
0.6
0.6
0.4 Positive INL
0.4
INL(LSB)
0.2
0.0
0.0
-0.2
-0.2 Negative INL
-0.4 -0.4
Negative INL
-0.6 -0.6
-0.8 -0.8
-1.0 -1.0
0 1 2 3 4 5 6 0.0 0.5 1.0 1.5 2.0 2.5 3.0
FIGURE 2-2: Integral Nonlinearity (INL) vs. FIGURE 2-5: Integral Nonlinearity (INL) vs.
VREF. VREF (VDD = 2.7V).
0.5 0.5
VDD = VREF = 5 V VDD = VREF = 2.7 V
0.4 0.4
fSAMPLE = 200 ksps fSAMPLE = 75 ksps
0.3 0.3
0.2 0.2
INL (LSB)
INL (LSB)
0.1 0.1
0.0 0.0
-0.1 -0.1
-0.2 -0.2
-0.3 -0.3
-0.4 -0.4
-0.5 -0.5
0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024
FIGURE 2-3: Integral Nonlinearity (INL) vs. FIGURE 2-6: Integral Nonlinearity (INL) vs.
Code (Representative Part). Code (Representative Part, VDD = 2.7V).
0.6 0.6
VDD = VREF = 2.7 V
0.4 fSAMPLE = 75 ksps
0.4
Positive INL Positive INL
0.2
0.2
INL (LSB)
INL (LSB)
0.0
0.0
Negative INL
-0.2
-0.2
Negative INL
-0.4
-0.4
-0.6
-0.6
-50 -25 0 25 50 75 100
-50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C)
FIGURE 2-7: Integral Nonlinearity (INL) vs. FIGURE 2-10: Integral Nonlinearity (INL) vs.
Temperature. Temperature (VDD = 2.7V).
0.6
0.6
VDD = VREF = 2.7 V
0.4 0.4
0.2
DNL (LSB)
0.2
DNL (LSB)
Positive DNL Positive DNL
0.0 0.0
-0.4 -0.4
-0.6 -0.6
0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100
FIGURE 2-8: Differential Nonlinearity (DNL) FIGURE 2-11: Differential Nonlinearity (DNL)
vs. Sample Rate. vs. Sample Rate (VDD = 2.7V).
1.0 0.8
VDD = VREF = 2.7 V
0.8 0.6
fSAMPLE = 75 ksps
0.6 0.4
0.4 Positive DNL Positive DNL
DNL (LSB)
0.2
DNL (LSB)
0.2
0.0
0.0
-0.2 -0.2 Negative DNL
Negative DNL
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1.0
-1.0
0 1 2 3 4 5
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VREF (V) VREF(V)
FIGURE 2-9: Differential Nonlinearity (DNL) FIGURE 2-12: Differential Nonlinearity (DNL)
vs. VREF. vs. VREF (VDD = 2.7V).
1.0 1.0
VDD = VREF = 5 V VDD = VREF = 2.7 V
0.8 0.8
fSAMPLE = 200 ksps fSAMPLE = 75 ksps
0.6 0.6
0.4 0.4
DNL (LSB)
DNL (LSB)
0.2 0.2
0.0 0.0
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1.0 -1.0
0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024
Digital Code Digital Code
FIGURE 2-13: Differential Nonlinearity (DNL) FIGURE 2-16: Differential Nonlinearity (DNL)
vs. Code (Representative Part). vs. Code (Representative Part, VDD = 2.7V).
0.6 0.6
VDD = VREF = 2.7 V
fSAMPLE = 75 ksps
0.4
0.4
Positive DNL
0.2
DNL (LSB)
0.2 Positive DNL
DNL (LSB)
0.0
0.0
Negative DNL
-0.2
-0.2
Negative DNL
-0.4
-0.4
-0.6
-0.6
-50 -25 0 25 50 75 100
-50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C)
FIGURE 2-14: Differential Nonlinearity (DNL) FIGURE 2-17: Differential Nonlinearity (DNL)
vs. Temperature. vs. Temperature (VDD = 2.7V).
2.0 8
1.5 7
VDD = 2.7 V
Offset Error (LSB)
Gain Error (LSB)
-1.5 1
-2.0 0
0 1 2 3 4 5 0 1 2 3 4 5
VREF(V) VREF (V)
FIGURE 2-15: Gain Error vs. VREF. FIGURE 2-18: Offset Error vs. VREF.
0.0 1.2
-0.2 0.8
-0.4 0.4
VDD = VREF = 5 V
fSAMPLE = 200 ksps 0.2
-0.5
-0.6 0.0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C)
FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Offset Error vs. Temperature.
80 80
VDD = VREF = 5 V VDD = VREF = 5 V
70 70
fSAMPLE = 200 ksps fSAMPLE = 200 ksps
60 60
SINAD (dB)
SNR (dB)
50 50
40 40 VDD = VREF = 2.7 V
VDD = VREF = 2.7 V
30 fSAMPLE = 75 ksps
fSAMPLE = 75 ksps 30
20 20
10 10
0 0
1 10 100 1 10 100
Input Frequency (kHz) Input Frequency (kHz)
FIGURE 2-20: Signal to Noise (SNR) vs. Input FIGURE 2-23: Signal to Noise and Distortion
Frequency. (SINAD) vs. Input Frequency.
0
70
-10
60
-20
-30 50 VDD = VREF = 5 V
VDD = VREF = 2.7 V
SINAD (dB)
THD (dB)
FIGURE 2-21: Total Harmonic Distortion (THD) FIGURE 2-24: Signal to Noise and Distortion
vs. Input Frequency. (SINAD) vs. Input Signal Level.
10.00 10.0
9.8 VDD = VREF = 5 V
9.6 fSAMPLE = 200 ksps
9.75
9.4
ENOB (rms)
ENOB (rms)
VDD = VREF = 2.7 V
fSAMPLE = 75 ksps 9.2
9.50 9.0
8.8
8.6
9.25
VDD = VREF = 2.7 V
VDD = VREF = 5 V 8.4
fSAMPLE = 75 ksps
fSAMPLE = 200 ksps 8.2
9.00 8.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 10 100
VREF (V) Input Frequency (kHz)
FIGURE 2-25: Effective Number of Bits (ENOB) FIGURE 2-28: Effective Number of Bits (ENOB)
vs. VREF. vs. Input Frequency.
100 0
60 -30
50 VDD = VREF = 2.7 V
fSAMPLE = 75 ksps -40
40
30 -50
20
-60
10
-70
0
1 10 100 1000 10000
1 10 100
Input Frequency (kHz) Ripple Frequency (kHz)
FIGURE 2-26: Spurious Free Dynamic Range FIGURE 2-29: Power Supply Rejection (PSR)
(SFDR) vs. Input Frequency. vs. Ripple Frequency.
0 0
-10 VDD = VREF = 5 V VDD = VREF = 2.7 V
-10
-20 FSAMPLE = 200 ksps fSAMPLE = 75 ksps
-20
-30 FINPUT = 10.0097 kHz fINPUT = 1.00708 kHz
-30
4096 points 4096 points
Amplitude (dB)
Amplitude (dB)
-40 -40
-50 -50
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
-130 -130
0 20000 40000 60000 80000 100000 0 5000 10000 15000 20000 25000 30000 35000
Frequency (Hz) Frequency (Hz)
FIGURE 2-27: Frequency Spectrum of 10 kHz FIGURE 2-30: Frequency Spectrum of 1 kHz
Input (Representative Part). Input (Representative Part, VDD = 2.7V).
550 550
500 500
450 450
400 400
350 350
IDD (µA)
IDD (µA)
300 300
250 250
200 200
150 VREF = VDD 150 VREF = VDD
100 All points at fCLK = 3.6 MHz except 100 All points at fCLK = 3.6 MHz except
50 at VREF = VDD = 2.5 V, fCLK = 1.35 MHz 50 at VREF = VDD = 2.5 V, fCLK = 1.35 MHz
0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 2-31: IDD vs. VDD. FIGURE 2-34: IREF vs. VDD.
500 120
450 110
100
400
90 VDD = VREF = 5 V
350 80
IREF (µA)
300
IDD (µA)
VDD = VREF = 5 V 70
250 60
200 50
VDD = VREF = 2.7 V 40 VDD = VREF = 2.7 V
150
30
100 20
50 10
0 0
10 100 1000 10000 10 100 1000 10000
Clock Frequency (kHz) Clock Frequency (kHz)
FIGURE 2-32: IDD vs. Clock Frequency. FIGURE 2-35: IREF vs. Clock Frequency.
550
500 VDD = VREF = 5 V 140
450 fCLK = 3.6 MHz VDD = VREF = 5 V
120 fCLK = 3.6 MHz
400
350 100
IDD (µA)
IREF (µA)
300
80
250
200 60
150 40 VDD = VREF = 2.7 V
VDD = VREF = 2.7 V
100 fCLK = 1.35 MHz
fCLK = 1.35 MHz 20
50
0 0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C)
FIGURE 2-33: IDD vs. Temperature. FIGURE 2-36: IREF vs. Temperature.
70 2.0
VREF = CS = VDD VDD = VREF = 5 V
40 1.2
1.0
30
0.8
20 0.6
0.4
10
0.2
0 0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 0 25 50 75 100
VDD (V) Temperature (°C)
FIGURE 2-37: IDDS vs. VDD. FIGURE 2-39: Analog Input Leakage Current
vs. Temperature.
100.00
VDD = VREF = CS = 5 V
10.00
IDDS (nA)
1.00
0.10
0.01
-50 -25 0 25 50 75 100
Temperature (°C)
3.4 Serial Clock (CLK) When operating in the pseudo-differential mode, if the
voltage level of IN+ is equal to or less than IN-, the
The SPI clock pin is used to initiate a conversion and resultant code will be 000h. If the voltage at IN+ is
clock out each bit of the conversion as it takes place. equal to or greater than {[VREF + (IN-)] - 1 LSB}, then
See Section 6.2, “Maintaining Minimum Clock Speed”, the output code will be 3FFh. If the voltage level at IN-
for constraints on clock speed. is more than 1 LSB below VSS, the voltage level at the
IN+ input will have to go below VSS to see the 000h
3.5 Serial Data Input (DIN) output code. Conversely, if IN- is more than 1 LSB
above VSS, the 3FFh code will not be seen unless the
The SPI port serial data input pin is used to load
IN+ input level goes above VREF level.
channel configuration data into the device.
For the A/D converter to meet specification, the charge
3.6 Serial Data Output (DOUT) holding capacitor (CSAMPLE) must be given enough
time to acquire a 10-bit accurate voltage level during
The SPI serial data output pin is used to shift out the the 1.5 clock cycle sampling period. The analog input
results of the A/D conversion. Data will always change model is shown in Figure 4-1.
on the falling edge of each clock as the conversion
takes place. This diagram illustrates that the source impedance (RS)
adds to the internal sampling switch (RSS) impedance,
3.7 Chip Select/Shutdown (CS/SHDN) directly affecting the time that is required to charge the
capacitor (CSAMPLE). Consequently, larger source
The CS/SHDN pin is used to initiate communication impedances increase the offset, gain and integral lin-
with the device when pulled low. When pulled high, it earity errors of the conversion (see Figure 4-2).
will end a conversion and put the device in low power
standby. The CS/SHDN pin must be pulled high
between conversions.
VDD
Sampling
Switch
VT = 0.6V
RSS CHx SS RS = 1 kΩ
CSAMPLE
VA CPIN ILEAKAGE = DAC capacitance
7 pF VT = 0.6V
±1 nA = 20 pF
VSS
Legend
VA = Signal Source ILEAKAGE = Leakage Current At The Pin
Due To Various Junctions
RSS = Source Impedance SS = sampling switch
CHx = Input Channel Pad RS = sampling switch resistor
CPIN = Input Pin Capacitance CSAMPLE = sample/hold capacitance
VT = Threshold Voltage
4
VDD = VREF = 5 V
Clock Frequency (Mhz)
0
100 1000 10000
tCYC tCYC
tCSH
CS
tSUCS
CLK
tCONV
tSAMPLE tDATA **
* After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output LSB
first data, then followed with zeros indefinitely. See Figure 5-2 below.
** tDATA: during this time, the bias current and the comparator powers down while the reference input becomes
a high impedance node.
tCYC
CS tCSH
tSUCS
Power Down
CLK
Start
DIN D2 D1 D0 Don’t Care
SGL/
DIFF
HI-Z Null HI-Z
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9*
DOUT Bit
(MSB)
tCONV tDATA **
tSAMPLE
* After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeros
indefinitely.
** tDATA: During this time, the bias circuit and the comparator powers down while the reference input becomes
a high impedance node, leaving the CLK running to clock out LSB first data or zeroes.
HI-Z NULL
DOUT BIT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Start
MCU Transmitted Data Bit
(Aligned with falling 0 0 0 0 0 0 0 1 SGL/
edge of clock) DIFF D2 D1 DO X X X X X X X X X X X X
MCU Received Data
(Aligned with rising ? ? ? 0 B9 B8
edge of clock) ? ? ? ? ? ? ? ? ? ? (Null) B7 B6 B5 B4 B3 B2 B1 B0
Data stored into MCU receive Data stored into MCU receive Data stored into MCU receive
register after transmission of first register after transmission of register after transmission of last
X = “Don’t Care” Bits 8 bits second 8 bits 8 bits
FIGURE 6-1: SPI Communication with the MCP3004/3008 using 8-bit segments (Mode 0,0: SCLK idles low).
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Data is clocked out of A/D
converter on falling edges
SGL/ D2 D1 DO Don’t Care
DIN Start DIFF
NULL
HI-Z B6 B5 B4 B3 B2 B1 B0
DOUT BIT B9 B8 B7
Start
MCU Transmitted Data Bit
(Aligned with falling SGL/
edge of clock) 0 0 0 0 0 0 0 1 DIFF D2 D1 DO X X X X X X X X X X X X
Data stored into MCU receive Data stored into MCU receive Data stored into MCU receive
register after transmission of first register after transmission of register after transmission of last
X = “Don’t Care” Bits 8 bits second 8 bits 8 bits
FIGURE 6-2: SPI Communication with the MCP3004/3008 using 8-bit segments (Mode 1,1: SCLK idles high).
Device 4
Device 1
Device 3
Device 2
VDD
MCP3004/08
DGND AGND
0.1 µF
XXXXXXXXXXXXXX MCP3004-I/P e3
XXXXXXXXXXXXXX
YYWWNNN 0712027
XXXXXXXXXXX MCP3004ISL e3
XXXXXXXXXXX XXXXXXXXXXX
YYWWNNN 0712027
XXXXXXXX 3004 e3
YYWW 0712
NNN 027
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available characters
for customer-specific information.
XXXXXXXXXXXXXX MCP3008-I/P e3
XXXXXXXXXXXXXX
YYWWNNN 0712030
XXXXXXXXXXXXX MCP3008-I/SL e3
XXXXXXXXXXXXX XXXXXXXXXX
YYWWNNN 0712030
NOTE 1
E1
1 2 3
A A2
L c
A1
b1
b e eB
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e .100 BSC
Top to Seating Plane A – – .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 – –
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .735 .750 .775
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .045 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB – – .430
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
E1
NOTE 1
1 2 3
e
h
b
α
h
φ c
A A2
A1 L
L1 β
Units MILLMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e 1.27 BSC
Overall Height A – – 1.75
Molded Package Thickness A2 1.25 – –
Standoff § A1 0.10 – 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 8.65 BSC
Chamfer (optional) h 0.25 – 0.50
Foot Length L 0.40 – 1.27
Footprint L1 1.04 REF
Foot Angle φ 0° – 8°
Lead Thickness c 0.17 – 0.25
Lead Width b 0.31 – 0.51
Mold Draft Angle Top α 5° – 15°
Mold Draft Angle Bottom β 5° – 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-065B
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
NOTE 1
1 2
e
b
c φ
A A2
A1 L1 L
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e 0.65 BSC
Overall Height A – – 1.20
Molded Package Thickness A2 0.80 1.00 1.05
Standoff A1 0.05 – 0.15
Overall Width E 6.40 BSC
Molded Package Width E1 4.30 4.40 4.50
Molded Package Length D 4.90 5.00 5.10
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle φ 0° – 8°
Lead Thickness c 0.09 – 0.20
Lead Width b 0.19 – 0.30
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-087B
NOTE 1 E1
1 2 3
A A2
L c
A1
b1
b e eB
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 16
Pitch e .100 BSC
Top to Seating Plane A – – .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 – –
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .735 .755 .775
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .045 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB – – .430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-017B
D
N
E
E1
NOTE 1
1 2 3
e
α h
h
c
φ
A A2
L
A1 β
L1
Units MILLMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 16
Pitch e 1.27 BSC
Overall Height A – – 1.75
Molded Package Thickness A2 1.25 – –
Standoff § A1 0.10 – 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 9.90 BSC
Chamfer (optional) h 0.25 – 0.50
Foot Length L 0.40 – 1.27
Footprint L1 1.04 REF
Foot Angle φ 0° – 8°
Lead Thickness c 0.17 – 0.25
Lead Width b 0.31 – 0.51
Mold Draft Angle Top α 5° – 15°
Mold Draft Angle Bottom β 5° – 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-108B
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
12/08/06