RMO3D-5
A Three-Stage Cascaded Distributed Amplifier with
GBW Exceeding 1.5THz
Amin Arbabian (1) and Ali M. Niknejad (2)
(1) Department of Electrical Engineering, Stanford University, Stanford, CA
(2) Department of Electrical Engineering and Computer Sciences, UC Berkeley, Berkeley, CA
Abstract—A three-stage cascaded distributed amplifier is de-
signed in a 0.13µm SiGe BiCMOS process. By optimizing the
amplifier both at the architecture and element level, an extremely
large measured gain-bandwidth product in excess of 1.5THz is
obtained. The core amplifier consumes 75mA from a 3.3V supply
and provides an average gain of 24dB from 15GHz to at least
110GHz (limited by equipment BW). A distributed RF-choke
design is employed to provide the bias current to the three
cascaded stages. The pass-band gain stays between 23 and 26.5dB.
Index Terms—Distributed Amplifiers, Wideband Amplifiers,
Pulse Amplifiers, Millimeter-wave Amplifiers, BiCMOS inte-
grated circuits, Millimeter wave integrated circuits, Distributed
RF-Choke.
I. I NTRODUCTION
Extremely wideband circuits with bandwidths exceeding
tens of gigahertz have applications in various fields such as
high speed links, broadband radio transceivers, high frequency
instrumentation circuitry, high resolution radar and imaging
systems. Silicon is replacing III-V technologies in many of
the microwave and millimeter-wave systems. Silicon’s higher
yields and reliability allow the design of larger and more
complex systems and this has opened many new applications
and design architectures in the microwave and millimeter-wave
areas. This trend, however, is not without its own challenges.
Larger substrate and metal losses together with lower intrinsic
gain and higher noise from the active devices poses new
challenges in silicon-based millimeter-wave circuits.
Distributed amplifiers (DAs) provide a large bandwidth in a
given process with low sensitivity to mismatches and modeling
deficiencies and therefore are a prime solution for extremely
wideband amplification. The operation of a DA relies on a
synthesized transmission line formed by external inductive
elements with the parasitic capacitances from active devices.
The addition of signal currents on the low impedance drain
line leads to a relatively low gain, albeit a large bandwidth.
Numerous CMOS and silicon-based DAs in various forms
have been reported [1]- [5].
Increasing the gain-bandwidth product of the distributed
amplifier beyond 1THz poses challenges in several areas.
Active element design, passive transmission lines, and current
delivery and DC biasing will all have extra complications for
these designs. Additionally, increasing the gain of CMOS DAs
usually comes at the heaviest trade-off in bandwidth. High
bandwidth is achieved through multi-resonant and compensa-
tion techniques that often provide non-predictable peaking and
droops and hence severe group delay variations.
978-1-4673-0416-0/12/$31.00 ©2012 IEEE 211
Here, we introduce a three-stage cascaded distributed ampli-
fier with an integrated, distributed, and wideband RF-choke for
biasing. Each of the amplifier stages consists of 5 cascode gain
elements and are biased independently. Simultaneous device,
gain element, and architecture optimizations lead to a gain-
bandwidth product in excess of 1.5THz.
II. PASSIVE E LEMENT D ESIGN
The design of a wideband DA requires a simultaneously
low-loss and high-impedance line. The two requirements are
contradictory due to the conductive and dielectric losses of the
line as outlined in the literature [3].
In designing the artificial transmission line, the primary
design variables are the initial characteristic impedance of
the line (Z0 ), the final synthesized line impedance (Z0f ),
line segment lengths (lseg ), transistor capacitance loadings
(Cex ) and the wave velocity on the transmission line (vline ).
Loss parameters also play a role in determining the number
of stages and device sizes [3]. The cutoff frequency of an
artificial transmission line is determined by the inductance and
capacitance per line segments (fc = π√1LC ). These parameters
are determined by the length of the segments as well as the size
of the devices. To achieve Z0f =50Ω transmission line at the
input and output lines, the initial Z0 needs to be considerably
higher than 50Ω since the extra device capacitances load
the line and lower the effective characteristic impedance. As
shown by [7] the required segment length which determines
the BW can be derived as follows (assuming short segments):
Cex × vline × Z0
lseg = (1)
[ ZZ0f0 ]2 − 1
In this case, if we fix Z0f =50Ω and vline = 1.5×108 , we can
then derive other line parameters. The previous two constraints
will determine relationships between Z0f , Cex , lseg , and fc .
To show the tradeoff, we first fix fc to 185GHz and plot
the allowable Cex as a function of initial Z0 (Fig. 1(a)).
Next we fix Z0 = 82Ω and plot Cex as a function of fc
(Fig. 1(b)). This specific impedance is selected with regard to
the loss/impedance tradeoff of this SiGe BiCMOS process.
At each point lseg is related to Cex through (1). These
relationships, together with the transmission line properties in
this process, provide the optimal bandwidth for given a power
consumption constraint.
Since the dielectric stack height is sufficiently large in this
process, a microstrip line was used as the element in the
2012 IEEE Radio Frequency Integrated Circuits Symposium
synthesized line. Details of the line losses in this and similar
processes can be found in the literature [8]. The transmission
parameters are shown in Table I.
(a)
(b)
Fig. 1. Cex as a function of Z0 with fc =185GHz (a) and Cex as a function
of fc with Z0 =82Ω (b).
TABLE I
T RANSMISSION LINE PARAMETERS .
Line Width 2µm
Z0 82Ω
Loss (@70 GHz) 0.69dB/mm
eff @100GHz 3.9
III. ACTIVE E LEMENT D ESIGN
The target bandwidth of the amplifier is 130 GHz with
the cutoff frequency of the device at 200 GHz. The cutoff
frequency, however, only determines the current driven re-
sponse of the device whereas in a realistic drive scenario other
poles come into play. For the distributed amplifier, placing
optimal matching networks to obtain the maximum stable gain
(MSG) is not an option. The design is extremely wideband
and assumes a dominantly capacitive input impedance. As
outlined in the literature, the input and output resistances of
the device ultimately limit the DA performance. Therefore,
device topology optimization has to go further than optimizing
the core ft and must, for example, also maximize the total
impedance at the input port.
Compared to CMOS DA designs, the base resistance (rb )
plays a detrimental role in determining the bandwidth of
Bipolar-based DA. As an example, a single finger 1.5µm
device with 2 mA bias current has an input profile of
Cser = 20fF and Rser = 43 Ω @ 80GHz. If we double the
device size and current, we end up with Cser = 42fF and
Rser = 24 Ω @ 80GHz which has a close (although slightly
worst) ωser . This shows the tradeoff between capacitance and
resistance at the input. It is clear that with these values,
obtaining 130GHz of bandwidth is impossible since at and
around 110 GHz we will have a dominantly resistive input.
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In order to reduce the effect of rb , a series input capacitor
can be used. Prasad has proposed using series capacitors for
MESFET DAs to obtain a gain-bandwidth tradeoff as well as
for larger input power handling [9]. Here, we primarily focus
on ameliorating bandwidth reduction effects from series base
resistance. Bandwidth is obtained at the expense of higher
power consumption as will be described next.
In an advanced bipolar device, contacts are placed directly
on top of the emitter to reduce the parasitic resistance on the
emitter side. For a structure with two-sided base contacts we
can approximate this component of the base resistance as:
Rsh We
RB = (2)
12Le
In this process, the emitter width is fixed to 0.27 µm. The
length and number of emitters are scalable. Given that with a
fixed current density the input capacitance scales linearly with
the emitter length, the input series-RC pole will stay constant
(to the first order). As shown in Fig. 2, we will now place
a series capacitor with the input. To explore the trade-offs
inherent in scaling, we will assume the device is scaled by a
factor of m and Cs is selected to be kCπ,0 . With these scaling
factors we have:
mk
Cin = Cπ0
m+k
mk
gm,ef f = gm0
m+k
Idc = mI0
1 k+m
ωser = r = ωser,0 (3)
2π m Cin k
Here, the subscript zero represents default values prior to
device scaling. We keep the input capacitance the same by
first scaling up the device (m > 1), and then adding the
appropriately sized Cs such that Cin = Cπ,0 . From the above
equation, this leads to the condition mk = m + k. With that,
ωser = mωser,0 with m times the DC current consumption. So
with m×IDC , we have a higher input series pole but the same
effective transconductance. Ultimately, this up-sizing is limited
by the fixed parasitics (e.g. trace capacitances) associated with
the device.
CS rb/m
Cπ.m m.gm
Fig. 2. Single gain stage equivalent circuit.
In our design, this technique alleviates the problem but does
not completely solve it especially closer to the cutoff frequency
of the amplifier. Emitter degeneration and capacitor-peaking
(Fig. 3) are used to further extend the usable bandwidth
of the device. Resistive degeneration stabilizes the bias and
operation of the element as well as providing yet another way
of achieving lower input load with the sacrifice of effective
transconductance (or DC power). A shunt capacitor provides
a zero in the transfer function and enhances the high frequency
response of the element.
 Emitter capacitor-peaking increases the potential for insta-
1/Re(Yin)
bility. This capacitor together with Cπ resembles a Clapp

[Farads]
oscillator. Therefore, the quest to reduce the series part of

[Ohms]
the input resistance can ultimately lead to a negative value (at -1/(2!f Im(Zin))
least in some parts of the frequency spectrum) and that can Im(Yin)/2!f
lead to instability. Re(Zin)

To ensure stability, we can confine the real part of the

Frequency [GHz]
input impedance to be positive over the entire frequency range.
Taking Fig. 3 as reference, we would like the input impedance Fig. 4. Input loading from the DA gain element.
after Cs to have a positive real part (Cs will not affect the
series representation of real part). If we assume the operation
frequency of the device to be much higher than ωβt and closer of the devices. For the base, a large series resistor can be used
to ωt , we can simplify the impedance to a form of: since the current is substantially lower. Conventional ways of
biasing the drain/collector lines include external bias-tees or
(1 + s series resistors. Both of these methods are ineffective once the
ωz )
Z(s) = DA is integrated into a larger system that uses the chip supply.
sCπ (1 + ωsp )
Series resistor biasing is inefficient in terms of power and may
1 cause reliability (narrow resistors) or bandwidth limitations
ωp =
RE CE (wide resistors). Additionally, cascaded DA topologies further
1 + gm RE complicate biasing due to need for several bias points as well
ωz = (4)
RE (Cπ + CE ) as AC connection between “collector” lines of previous stages
In the impedance representation above, in order for the real with the “base” line.
part to be positive, the pole has to come after the zero. This Here, we are not interested in providing DC or close to
translates to: DC gain in the amplifier. The final system will cover bands
that will go down to a few GHz and not lower. We therefore
Cπ design a cascaded RF choke using an integrated spiral inductor
RE CE ≤ (5)
gm at the core. The design uses a short high impedance line
Or equivalently, ωE ≥ ωt where ωE = RE1CE . This condition followed by a 4 turn square spiral (1.5 µm spacing between
is conservative since it does not include base losses. In reality turns). The structure is connected to the bias point by a longer
a slightly lower ωE can be safely targeted. In this design RE = trace that provides the low end inductance. The architecture
20Ω and CE = 45f F were chosen. is shown in Fig. 5. The first segment of the high-Z line
together with part of the choke provide adequate inductance
RFout for the highest frequencies. The multi-turn choke provides
the inductance at mid-frequencies. It is designed to have
sufficiently high self-resonance frequency. Capacitor C1 is a
Bias
3X1.5μm local and relatively small capacitor (400 fF) that ensures that
Lpar
the high frequency response is decoupled from the second
5mA high-Z line and whatever comes after that. Capacitor C2 is
45fF a large capacitor that isolates the cascaded-choke structure
3X1.5μm from biasing circuits. For bringing the response down to lower
RFin
frequencies, we could replace the second high-Z line (between
Bias capacitors) with another larger multi-turn inductor.

high-Z line high-Z line To DC

Fig. 3. DA cascode gain element. Bias
To Circuit
C1 C2
Multi-turn
The overall details of the gain element is shown in Fig. 3. choke
In addition to the bandwidth extension techniques discussed,
a series inductor is also placed in the cascode stage to further Fig. 5. Cascaded choke architecture.
improve the bandwidth [10]. Again, the size of this inductance
will affect the input impedance and can potentially cause
oscillations if selected to be too large. V. A RCHITECTURE OVERVIEW AND M EASUREMENT
Simulations for the input loading of the gain stage is shown R ESULTS
in Fig. 4. A three-stage cascaded DA is realized in 0.13 µm SiGe
BiCMOS process. Each stage uses 5 gain elements. The
IV. B IASING cacode stages are biased at 5 mA each and hence the total
Biasing a wideband distributed amplifier poses several chal- current in the active part of the DA is 75 mA. For terminations
lenges. An RF choke is required to provide biasing to the drain on the collector and base lines, m-derived sections are used.

213
 TABLE II
C OMPARISON TO OTHER PUBLISHED WIDEBAND AMPLIFIERS
Ref. Process Gain (dB)
BW (GHz) GBW (GHz) Supply (V) Power (mW) Area (mm2 )
[1] 90nm CMOS 7.4 80 190 2.4 120 0.72
[2] 0.18µm CMOS 20 39.4 394 2.8 250 2.24
[3] 90nm CMOS 14 73.5 370 1.2 84 1.72
[4] 65nm CMOS 22 65 818 1.3 97 0.94
[5] 90nm CMOS 19 73.5 660 1.2 84 1.19
[6] 0.18µm SiGe 20 84 840 5.5 990 0.63
This Work 0.13µm SiGe 24
95 (15 to 110) (*) 1500 3.3 247.5 0.41 (core)
110 (15 to 125) (sim) 1700 (sim) 0.65 (w/Pads)
(*) Measurements limited by equipment bandwidth to upper frequency of 110GHz.

The chip micrograph is shown in Fig. 6. Each of the annotated progress.

stages have independent biasing networks with the distributed
choke architecture. The amplifier occupies an area of 450µm
by 900 µm without the pads and an area of 1050µm by 620µm
including all the pads. The resistive terminations are AC-
coupled using a network of capacitors, ranging from smaller
MIM capacitors to larger MOS capacitors, arranged such that
the desired frequency response is achieved.
VI. C ONCLUSION
A three-stage cascaded distributed amplifier was designed
in a 0.13µm SiGe BiCMOS process. The amplifier provides
a measured 1.5THz gain-bandwidth product limited by the
measurement equipment. Concurrent device and architecture
level optimization leads to the record-level gain and band-
width distributed amplifier in silicon. A distributed RF-choke
topology provides DC bias and current to the collector lines.
At the device level, series input capacitance together with
capacitor peaking and interstage inductor in the cascode device
are utilized for bandwidth enhancement. The amplifier consists
of 3 stages each with 5 gain elements. Altogether, the gain
elements consume 75mA from a 3.3V supply.

Fig. 6. Chip micrograph of the SiGe distributed amplifier.

ACKNOWLEDGEMENTS
The authors acknowledge the contributions of the sponsors
of the Berkeley Wireless Research Center, the NSF Infras-
tructure Grant No. 0403427, the foundry donation of STMi-
20 croelectronics and support under NSF grant ECCS-0702037.
S21
S-parameters [dB]

0 S22
-20
S11
-40
-60
0 20 40 60
Frequency [GHz]
Fig. 7. S-parameter measurements of the SiGe DA.
S-parameter measurements are shown in Fig. 7. The am-
plifier provides an average gain of 24dB and a 3dB corner
frequency that exceeds 110GHz (measurements limited by
the VNA). Measurements include all pads/parasitics and no
de-embedding is done on the DA. The DA has a measured
GBW product in excess of 1.5THz. Simulations show that a
BW of 125GHz is expected. Further measurements beyond
the W-band will assess operation to 125GHz (leading to a
GBW product in excess of 1.7THz). The pass-band gain stays
between 23 and 26.5dB. The simulated noise figure is between
7.4 and 9.5dB in the passband. NF measurements are in
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