Save trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.vturesource.com USN L a ‘Third Semester B.E. Degree Examination, December 2011 Logic Design Time: 3 hes Mi Note: Answer any FIVE full questions, selecting at least TWO questions from each part. PART—A 1a, Draw the truth table and explain how a TTL NAND gate works. Posmans, 1. An asymmetrical signal waveform is high for 2msee and low for the frequency and the duty eyele ofthe waveform. (o4 stares) €. Discuss the positive and negative logic and list the equiy and negative Josie ws Mars) 4. Draw the timing diagram and write a Verilog HDL. sural mode!) forthe Boolean function Y = NAND(Y1, ¥2); where ¥1 = 4 (ws Marla) 2 a. A digital system is to be designed in which the m year is given as inp in four bit form. The month January is represented as“ ‘25 “0001” and s0 oa. The ‘output of the system should be ‘I’ corresponding 10 of the month containing 31 days or otherwise itis “0”. Consider the ‘care conditions. For this system of four ‘Boolean expression in Em and at ‘Write the truth table ‘input beyond “1011” as don’t 1D), find the following : iv) Implement the simplified e: END-NAND gates. (10 Marks) b, Using Q-M method, sieaplify HA, BC, D) = 2(0, 3, 5, 6,7, 11, 14). Write the ‘gute diagram forthe s 1g NAND-NAND gates, (a0 Marks) 3 a. Implement the Boolean ‘by POS, f(A, B,C, D) = nC, 2, 5, 6,9, 12) using 810-1 MUX. (08 Marks) 1b. DrawaPLA circuit realize the Boolean functions Y3 = A’BC’; Y2= AC; Y1=ABIC+A’BC, ‘BC + A'BC + A’B'C' + ABC. (06 Marks) © Implement a full jing a 3-10-8 decoder. (06 Marks) 4 a. Drawithe logic ed ‘D’ flip-flop. Write its truth table, characteristic equation, state diagram and jon table. What is the drawback of SR flip-flop? “Wo Marks) b tt-Tpber transfer characteristic. (06 Marks) c. Ush ‘write verilog HDL code for a ‘D* flip-flop. (04 Macks) PART—B vege triggered JK Hip-flops, draw the logic diagram of a 4-bit serial In - OUi\shift register. Draw the waveform to shift the binary number 1010 into this >, draw the waveforms for four clock transitions when J= K = 0 (assuming the register has'stored 1010 init). (08 Marks) How long will it take to shift the hexadecimal number ‘AB" into the 54/74164 (SIPO) if lock is connected to it? Also, mention the time required to extract an 8-bit number 5 a. Using mporaot Nat: Onsopleog your answers, compulsory raw ciagonal cot ie one rennin lek pages. the same register. (04 Marks) ‘neat diagram, explain a 4-bit universal shift register. (05 marks) ‘Write Verilog code for switched tail counter using ‘assign’ and ‘always’ statements. (03 Marks) Lof2 BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Vturesource Go Green initiativeSave trees use e-Question Paper DOWNLOAD THIS FREE AT www.vturesource.com Go green 10¢! 6 & Mention any two differences between asynchronous and synchronous counter. With block diagram, output waveforms and truth table. Explain a 3-bit binary Rippl ‘Counter constructed using negative-edge trigged JK flip-flops. ‘binary asynchronous counter is connected with a clock of $00 KHz period of the waveform at the output of the first and the last JK flip ¢. Design a synchronous mod-6 counter using JK Alipflop. a. Compare Moore and Mealy model of synchronous sequential cireuit. b. Design an asynchronous sequential logic circuit for state transition diagram Fig.Q7(b). ie @ 20, i os ¢. Reduce state transition diagram (Moore model) of Fig, Qiffe) by. §) Row elimination method ii) Implication ta d. (06 Marks) (We Maris) 8 a, Discuss the two drawbacks ‘output. Draw the schematic, conversion is achieved us ider used in converting digital input fo anslog iy binary ladder and explain how the digital to analog, do Marks) b. Using a schematic block ly explain counter type ADC. (08 Marks) ©. A-counter type 10 bit fed with 7 MHz clock. Find : i) The average ii) The maximum (2 Marks) 2of2 BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Vturesource Go Green initiative