Save trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com usn | | TTTT1 10C833 Third Semester B.E. Degree Examination, Dee. 2013/Jan. 2014 Logic Design Time: 3 hes. Max. Maks: 100 Note: Answer FIVE full questions, selecting atleast TWO questions from each part. PART-A @ 1a, With he id ofthe cru diagram explain the operation of ?— input este os ars) 1 What are univers gtes? Implement the following functions oy (araye)p. (essary © Write the truth table of the logic circuit having 3 inn JP outa output expressed as y=ABC+ABC . Also simplify the extjhision joolean expression and implement the logie circuit using NAND gates? (06 Marks) Bank pages. Amy vevealing of enicton, appl 0 evaluator ad requis writen cp 4218 80, willbe wad Using Q-M method, simpuify the expressions the gate diagram for the simplified expression us Marks) b. A digital system is to be designed in whic form. The month January is represented the system should be ‘I° corresponding of the month containing 31 days or ‘otherwise itis “0° consider the exgasprur the input beyond “1011” as don't care ‘conditions for system of four varias (gfe, D) find the following '), Boolean expression in mar jm ii) Write the ruth table ili) Using K — map, simpli expression ot canonical minterm form iv) Implement the simpli tiolpsing NAND ~ NAND gates. (10 Marks) E(0, 3, 5,6, 711, 14). Write |AND gates, ao ‘year is given as input is four bit “0001” and so on. The output of Write a 4: 1 MUX progROSing conditional ‘assign’ and ‘case’ statement. (06 Marks) b. What are static design hazards fre circuit? Explain with an example, (06 Marks) somparator. (08 Marks) z 2 of clock D ~ flip/fop write its truth table and characteristic gm and excitation table, what is the draw back IK fip/flop. (10 Marks) >. Diterehyte bet Wh combinational circuit and sequential circuits, (05 Marks) © Show hot SR Mip/flop can be converted into T ~ flip. (05 Marks) PART-B I-in-seral-out shift register. Draw the waveform to shift the binary number 1010 into sister. Also draw the waveform for 4 clock transistor when J=K=0. (8 Marks) erp eee oe S BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Viuresource Go Green initiativeSave trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com 10€833 With the help of neat block diagram and timing diagram, explain the working of a mod ripple counter constructed using the edge triggered JK- fip/flop, 8, Design asynchronous counter for the sequence 0» 4 > 1 +2604, R. flip-flop. Marks) Design a sequence detector that receives bindery data stream as its input, X and si ‘when a combinations ‘011” arrives atthe input by making its output. Y highaajich othggwise ‘emai line consider data is coming from left, i. the first bit to be id fond 1 and third 0 ftom the input sequence. Design mealy model? 4 Marks) Realize the sequential circuit forthe state diagram. 16 Marks) Explain 2-bit simultaneous A/D conver (10 Marks) What is binary ladder? Explain th a digital input of 1000. (06 Marks) What is accuracy and resolution, rter? What is the resolution of a 12 bit D/A converter which uses binary lader?gfthiiull scale output is + 10 V, what is the resolution » 20f2 BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Viuresource Go Green initiative