The Problem:

In the semiconductor world we have issues of parts being counterfeited and sold
illegally. In a world where you can surf the web and buy exactly the parts you need
about anywhere you have no way of knowing a counterfeit from a real deal till its to
late... Or can you?
 The
Solution

PUFs! PUFs are the answer to the problem! A PUF is a

small circuit that can be added to a chip without
negatively effecting the chip, each with their own unique
id. By exploiting the random component of manufacturing
error we can have a 50% chance for each bit in the circuit
of being a 1 or a 0…

Not convinced?

A chance between a 1 and a 0 doesn't seem to be much, but

what if we make the number of bits to be very large. Then
for each bit that we add we double our randomness!

What I have in mind is a 32 random bit PUF, and To give

you an idea of how unlikely it is for 2 bits to end up
with the same ID, lets use a formula to calculate the
likely hood of two of the same chip being the same.
The Math:

So for each bit I add I double the likelihood of a unique

value. So the chance that we will have the same value twice is
[1/(2bits)] * 100%.

So for 32 bits we have:

[1/(232)] * 100% == [1/(4,294,967,296)] * 100% ==
(2.33 * 10-10) * 100% == (2.33 * 10-8) % == 0.0000000233%.

So as we can see it is very unlikely to fabricate two thirty

two bit PUFs with the same id, but if your still not convinced
a 64 bit PUF is just a step away!
 The Process:

To create a 32 bit PUF we just need a few simple basic parts.

Minimal sized PMOS and NMOS transistors to build an Inverter.

By placing two Inverters in a serial loop we create a random chance that one side should be 0 and the
other should be 1 in the moment it is fabricated.

Once fabricated it should keep that value whether it is turned on or off within its loop.

Next we tap the value between these Inverters and that is considered a one bit PUF.

If we gather an addition 62 more Inverters for a total of 64, we then have all of the Inverters necessary
for a 32 bit PUF, all for a small price of 128 minimally sized transistors.
Whats
Next? After the creation of the 32 bit Puf I now have a 32
bit output which is a problem because chip ports are
costly.

So in order to counter this I suggest the addition of

a 32 bit shift register which will require: Wait for
it:

ONLY ONE PORT! The decision couldnt be more obvious!

The implementation of the shift register is quite

simple; Using the same Inverters as before and adding
logic for 2 input NAND gates, we can create
Multiplexers and D Latch Flip Flops.

Using these pieces we can create a 1 bit register,

which can be used to make 31 just like it.

By connecting the registers serially and initially

loading them with a PUF value, we can use a clock to
output each value from a single port.

If that sounds like a deal keep following along as I

show you the process step by step.
 Inverter

2 Minimal Sized
Transistors
PUF SINGLE BIT

2 Inverters
= 4 minimal sized
transistors
 PUF 4 BIT

4 PUFS = 8 Inverters = 16 Minimal

Sized Transistors

Static input shows the PUF is connected properly.

PUF 16 BIT
16 PUFs
=
32 Inverters
=
64 Transistors
 PUF 32 BIT

32 PUFS = 64
INVERTERS =
128 TRANSISTORS

Hurray! 32 bits of static...

 Monte Carlos Simulation PUF

Runs the simulation 100 times with random variations of manufacturing defect

Each of the 32 bits gets simulated 100 times

Narrowing the test to a single bit
Still shows variation within that
Single bit.

So the first test is passed

By changing the rise
time of VDD
between 1u, 2u, and
5u, we prove that
each bit is shifting to
a 0 and 1
independent of the
VDD curve.

This proves
that the 0 and
1 draw of the
bits is a
random
chance in the
manufacturing
process of the
chip

So it
works!
Next for that shift register
Two Input NAND Gate

2in * (Pmos + Nmos) = 4

Minimal Sized Transistors
Two Input
Multiplexer

3 * 2 Input NANDS + 1 Inverter

= 14 Minimal Sized Transistors
The Good

And The Bad

 Takes the input value to output on positive edge
The Bad: DFF 1.0
Problem happens when 32 registers try to do
that at the same time.

4* 2 input NAND
= 16 Transistors

To fix we need to add a delay between

inputs and outputs so our registers
don't get washed out completely, each
iteration
 The Good: Positive Edge
Triggered DFF

Outputs only on positive trigger,

releases input only on positive trigger,
output it slightly shifted the input:

IDEAL!

Implementation isnt quite as 5 * 2 input NANDs + 1 * 3 input NANDs

pretty, but it gets the job done! = 26 Minimal Sized Transistors
Three Input Nand Gate,
for DFF
Same idea as a 2 input NAND

Add a third input to parallel

PMOS in the pull up network

And in series to the NMOS

pull down network.

3in * (Pmos + Nmos)

= 6 Minimal Sized Transistors
 Single Bit Shift
Register
Process:

Set SEL to 0, load init with an intial

value

Set Prev to the previous register, …, to

ground

Set Next to the next register, … , to

Vout
SEL is 0 for 2us then snaps
to 1 for the rest of the
simulation

1 MUX + 1 DFF Durring SEL = 0 all mux get

= 40 MS Transistors an initial value which load
each register

Durring SEL = 1 all mux get

< Not a lot to test
with a single reg
a value from a prev reg, … ,
to ground.
Inevetably all register exit vout
by clock until all registers are 0
This Time We Skip to the Good Part!
32 BIT SHIFT REGISTER
<32:0> : 01100100100001110011001010111001 0 Which checks out. Zero represented with gnd

<32:0> : 00101010101001100011011010100101 0 Which checks out. One is represented with VDD

In this test you can see
the output of each
register, which shows
that its clearly shifting
properly.

32 * Reg = 32 * (DFF + MUX)

= 1,280 MS Transistors <32:0> : 00101010001001100111111010001101 0 Which checks out.
So by Monte Carlos testing:

We have a 32 bit value that is random upon fabrication.

By Bulk Testing:

We have a 32 bit shifting by clock

to a single output.

So in conclusion We have:

One 32 bit fully functional PUF

One 32 bit fully functional

Shift Register

So therefore we have:

One functioning 32 bit PUF shifted out of a single

output!
So we got the full mother ship baby!
32 BIT PUF + 32 BIT SHIFT REGISTER = 64 + 1,280 = 1,344 Minimal Sized Transistors
Since we have proven both part worth
efficiently, the final part does not need
a test to suggest that together they can
implement perfectly!

The final piece is workable with a single

output pin, an Enable, CLK, VDD, and VSS.

Since the total transistor count is the

64 for the PUF, plus the 1,280 for the
register. The total transistor count for
implementation comes to 1,344
transistors. Which is a few penny's in a
pond next to a billion transistor chip.

So, if you want to help make the world a

better place with fewer counterfeited
chips, then get your PUF today and secure
your property!