THE FIELD EFFECT TRANSISTORThe Field Effect Transistor The Field Effect Transistor, or FET, is a three terminal unipolar semiconductor device which uses a conductive central channel to control the flow of current through itself by the application of different voltages onto its three terminals. These terminals are labeled the: Source ( S ), the Drain ( D ), and the Gate, (G ) respectively. ‘There are two types of field effect transistor, the Junction FET (JFET) and the Insulated-gate FET known commonly as a MOSFET (Metal-Oxide Semiconduc- tor Field Effect Transistor). The major difference between the two is the con- struction of the Gate region. Both types of FET use the voltage applied to their input terminal, the Gate, to control the current flowing through them resulting in the output current being proportional to the input voltage. As the electrical resistance of the main conductive channel relies heavily on the electric field (hence the name fleld effect) generated by the input Gate voltage, this then makes the Field Effect Transistor a "VOLTAGE" controlled device (un- like the BUT which is a current controlled device) The Field Effect Transistor is simply a single channel of doped silicon that behaves as a resistor with one end of the channel being called the Source terminal, as current is sourced into it, while the other end of the channel is called the Drain terminal, as current is drained away from ty it The electrical current which flows from Drain to Source depends on the resis- tance of the channel, and the Drain to Source voltage Vps. Thus, if the channel is doped evenly, its conductivity will be the same at all points along its entire length with the voltage drop along the channel being linear with respect to the source terminal. There are two basic configurations of field effect transistor, the N-channel FET and the P-channel FET. The N-channel FET channel is doped with donor impuri- ties meaning that the flow of current through the channel Is negative (hence the term N-channel). Likewise the P-channel FET channel is doped with acceptor impurities meaning that the flow of current through the channel is positive (hence the term P-channel). Py Field Effect Transistor"yy ElectronicsTutorials The Junction Field Effect Transistor D JFET Channel Construction Conductive G Channel ~~~ + | Vos Source Source N-channel JFET P-channel JFET The N-channel JFET has a much greater channel conductivity (lower channel resistance) than their equivalent P-channel types, since electrons have a greater mobility through a conductor compared to holes. This makes the N-channel JFET a more efficient conductor compared to their P-channel counterparts.Analogies of terminals and voltages between the unipolar Field Effect Transis- tor and the Bipolar Junction Transistor are given as: Drain Supply (Vou Source (S) Emitter (E) Drain (D) Collactor (C) | Gate (G) | Base(B) Collector Supply (Vee) Drain Current (lo) Collector Current (te) Gate Bias Voltage (Va) Baso Bias Voltage (Va) Depletion Region Ig Gate For a Junction Field Effect Transistor (JFET) to operate correctly, it requires two external biasing voltages. One voltage, Vps is connected between the source and the drain terminals allowing current to flow through the conductive chan- nel. The other voltage source, Ves is connected between the gate and the source terminals. This Veg voltage biases the gate terminal varying the con- ductivity of the channel and hence the amount of current flowing through it. at Field Effect Transistor@ For an N-channel JFET, 2 P-type region called the Gate is diffused into the N-type channel forming a reverse biased pn-junction. It is this pr-junction which forms the depletion region around the Gate area when no external voltages are applied. Note also that this depletion region is wider at the drain end of the channel be- cause the drain-to-source voltage adds to the gate-to-source voltage, creating a higher reverse bias voltage than that appearing actoss the source end of the channel. When the gate terminal is shorted to the source terminal, or at the same volt- age potential as the source and drain, the depletion region is very shallow al- lowing maximum current to flow through the fully open conductive channel. This channel current is called the FET’s saturation current, Ipss (Drain-to- Source-Saturated-Current) and any JFET data sheet will list this maximum |pss_ value. I " When the gate region is made negative with respect to the drain, the reverse-blas condition causes the depletion layer to increase in size and extend across the channel changing its width. The result is a change in the channel resistance between the drain and source limiting current flow through the channel, a sort of “squeezing” effect takes place as the channel is reduced or depleted. Thus JFETs are known as “depletion-type" devices. If the gate terminal is made progressively more negative the depletion layer ex- pands even more reducing further the effective cross-sectional area of the channel and eventually closing or “pinching-off” the conducting channel entirely (cimilar to the cut-off region for a BUT) preventing the flow of current to flow. The voltage point at which this happens is called the threshold or pinch-off volt- age, Vp. Thus for an N-channel JFET, the size of the depletion region is con- trolled by Ves, and as Veg becomes more negative, so too does the depletion region. www.electronics-tutorials. wsThe channel is closed “Pinched-off” Ig Gate Vos >> Vp N-CHANNEL JFET “PINCHED-OFF" Note that the P-channel JFET is complementary so has the same operating characteristics as the N-channel JFET with the main difference being the direc- tion of the drain current (Ip) through the channel, since in a P-channel JFET, the polarity of the bias voltages, Vag and Vps are opposite to that in an N-channel JFET. For a JFET device, the relationship between drain current, Ip and the gate- source voltage, Vs Is given by: l= |, it — esl’ 'D ‘DSS Vp and Vps is much greater than Vp, the channel is saturated Ipss Thus when Ve (Fully-on) and Ip At pinch-off, Ves = Vp the channel is closed and cut-off so no drain current flows and Ip = 0 Remember that Vp will be Negative for N-channel FETs and Positive for P-chan- nel FETS. 6 | Field Effect TransistorTransconductance Curves As a JFET controls the current flowing through its conductive channel using a voltage applied to its gate, it is therefore a “transconductance” (transfer-con- ductance) device. The relationship of input voltage to the output current is given the symbol, gm with the unit of transconductance being the siemens (symbol, S), equivalent to amps per volt, (A/V). By plotting the value of Ip against Vgg for a fixed value of Vps, we can create what is commonly called a transconductance curve of a JFET as shown for both N-channel and P-channel types. N-channel tp Ty P-channel JFET JFET Toss Toss, slope Drain Current Drain Current $ +Vos Vos Gate-source Voltage Gate-source Voltage Notice that the slope is nonlinear since it follows the above equations square law, so drain current, Ip Increases faster due to the opening of the channel as Vos approaches zero (Vgg = 0). Thus for a JFET, changes in Vgg does not pro- duce equal changes in Ip D weave seen thatthe Nchannel ine a le ] SFET acts like a voltage-controlled resistor whose conductive channel has zero resistance (fully-on) when Vos Is zero, and maximum “ON” resistance (fully-off) when the gate voltage is very negative (positive for a P-channel JFET) thus making ‘the JFET a normally-ON device. iahiieciden iBy having specific values of gate-source voltage, Ves applied to the gate and varying the voltage between the drain and source, Vps, we can create a set or family of output characteristics curves for a JFET device, similar to those of the bipolar transistor, showing the relationship between Ip and Vos for different values of Vos. Ohmic, Saturation Region Breakdown a ¢§__ Sain ein eee renee Ves Tpss — Pinch-off points Drain Current, Ip (mA) 4 Vos (Vv) Ve Drain-source Voltage The JFET’s pinch-off voltages separate two major operating regions. The shaded area to the left or below pinch-off Is called the Ohmle Region and the shaded area to the right or above pinch-off is called the Saturation Region. We can define the four areas or regions of operation of the Junction Field Effect Transistor as: 1. Ohmic Region - When Vgg = 0 the depletion layer of the channel is very | small, As Vps increases the current flowing through the channel increases lin- early and the JFET acts like a voltage controlled resistor until the knee point is reached at the pinch-off point. ry Field Effect Transistoray ElectronicsTutoria 2. Cut-off Region ~ This is where the gate voltage, Ves is sufficiently negative to cause the channel to close completely and is independent of Vps. The JFET acts as an open circuit with the channel resistance at its maximum so no drain current flows, | p = 0. 3. Saturation or Active Region ~ The JFET becomes a good conductor with the channel being controlled by Ves resulting in linear amplification. Variations in the drain-source voltage, Vps has little or no effect on changes in channel cur- ent, Ip acting as a constant-current source but changes with Vgg. When biased in this region, the JFET acts as an amplifier. 4, Breakdown Region ~ The drain-source voltage Vps is high enough to causes the JFET's resistive channel to break down because the reverse-biased gate-to- channel pn-junction is damage allowing an uncontrolled amount of current to flow through the channel. Thus a very small change in Vps causes very large uncontrolled changes in Ip. Note then that for fixed values of Vgg, increasing the value of the drain-source voltage causes the JFET to operate between Ohmic region (voltage controlled resistor), Saturation region (constant-current source) and Breakdown region (constantvoltage source). For normal amplifier operation, Vs is biased to be somewhere between Vp and 0.JFET Modes of Operation Like the bipolar junction transistor, the field effect transistor being a three terminal device is capable of three distinct modes of operation and can therefore be connected within a circuit in one of the following configurations. COMMON SOURCE (CS) CONFIGURATION iy In the Common Source configuration (similar to common emitter), the input is applied to the gate and its output is taken from the drain. This is the most common, mode of operation of the JFET due to its high input impedance and good voltage amplification and as such Common Source amplifiers are widely used. The common source mode of FET connection is generally used audio fre- quency amplifiers and in high input impedance pre-amps and stages. Being an amplifying circuit, the output signal is 180o out-of-phase with the input signal. COMMON GATE (CG) CONFIGURATION 4Vpp_(In the Common Gate configuration (similar to common base), the input is applied to the source and its output is taken from the drain. The gate connected directly to Ny ground (Ov). The high input impedance feature of the previous connection is lost in this configuration as the common gate has low input impedance, but high output impedance. This type of FET configuration can be used in high frequency circuits or in im- pedance matching circuits where a low input impedance needs to be matched to a high output impedance. The output is in-phase with the input. ety Field Effect TransistorCOMMON DRAIN (CD) CONFIGURATION Ses, In the Common Drain configuration = (similar to common collector), the input is nea é & applied to the gate and its output is taken . from the source. The common drain or 3 [2+——0'\) “source follower” configuration has a high fn input impedance and a low output impedance with near-unity voltage gain, so o——1____6 pv _ is therefore used in buffer amplifiers. This configuration is referred to as "Common Drain’ because there is no output signal available at the drain connection, the voltage present, +Vop just provides the bias. The voltage gain of the source follower configuration is less than unity so the output signal is always in-phase, Qo with the input signal. DC Switching Applications As with the BJT, the JFET being a voltage-controlled device can be used to provide either DC or ON-OFF switching control of a load current. By having a constant supply voltage, Vpp and using a gate control voltage, Vg we can switch the channel between its cut-off and saturation regions. COMMON SOURCE (CS) CONFIGURATION 40 For a JFET to work as a switch in its common source configuration, the following conditions apply: Vow — Vos Voor Ip = D Io Ouse h The JFET will be “fully-on" when: Vo = 0, and Ip = Ipss The JFET will be “fully-off" wh Vg = Vp, and Ip = 0 Remembering that, Vp is negative for n-channel FETs, and positive for p-channel FETs. www.electronics-tutorials.ws EaThe MOSFET As well as the Junction Field Effect Transistor (JFET), there is another type of Field Effect Transistor available that has no gate-to-channel pnunction, but in- stead the gate terminal is electrically insulated from the main current carrying channel by means of a thin insulating silicon dioxide (Si02) layer and is there- fore called an Insulated Gate Field Effect Transistor or IGFET. The most common type of insulated gate FET which is used in many different types of electronic circuits is called the Metal Oxide Semiconductor Field Ef- fect Transistor or MOSFET for short and just like the previous JFET, MOSFETs ate available with either N-type or P-type channels. However, unlike the Junction FET which was an N or P-channel depletion type device, MOSFETs are available as both Depletion and Enhancement type de- vices and both of these with either N or P-type channels, thus making the MOSFET available in one of four different devices. = N-channel Enhancement MOSFET or E-NMOS FET = P-channel Enhancement MOSFET or E-PMOS FET = N-channel Depletion MOSFET or D-NMOS FET = P-channel Depletion MOSFET or D-PMOS FET The basic difference is that Depletion types are normally-closed devices and a negative gate voltage has to be applied to turn them "OFF". While Enhancement types are normally-open devices so a positive voltage is applied to the gate turn them "ON" so the biasing of the gate with respect to the source varies for each type. MOSFETs are three terminal devices with a Gate, Drain and Source the same as for the JFET. The schematic symbols used to identify the four basic variations of the MOSFET being: cry Field Effect TransistorMOSFET SCHEMATIC SYMBOI Gate Drain Drain Drain Drain Cs Gat | Gat: \ Gat | ate P] ate ate 1 Source Source Source Source D-NMOS D-PMOS. E-NMOS E-PMOS. Depletion Type Enhancement Type (normally-closed) (normally-open) The line in the MOSFET symbol between the drain (D) and source (S) connec- tions represents the transistors semiconductive channel. If this channel line is a solid unbroken line then it represents a “Depletion” (normally-closed) type MOSFET as drain current can flow with zero gate biasing potential. If the channel line is shown as a dotted or broken line, then it represents an “En- hancement” (normally-open) type MOSFET as zero drain current flows with zero gate potential. The direction of the arrow pointing to this channel line indicates whether the conductive channel is a P-type or an N-type semiconductor device.MOSFET Construction AMOSFET structure consists of a lightly doped p-type substrate and two heav- ily dopedn-type regions being the Source, S and the Drain, D regions with the gap between them being the channel. A thin layer of metal-oxide insulating ma- terial between source and drain is covered by a conductive material, forming the Gate, G terminal. Thus giving its physical construction of being a Metal on top of an Oxide on top of a Semiconductor, hence the name MOS. Source (S)@——} © Drain (D) Depletion Substrate Layer Since the gate terminal is electrically insulated from the main current carrying channel, the MOSFET therefore has an extremely high input impedance, similar to that of the JFET. This means then that the MOSFETs gate current Ic is essen- tially zero for DC biasing configurations, hence the name insulated-gate FET (IGFET). Vpg and Veg provide the necessary biasing voltages. As with the JFET, transconductance curves can be plotted to show the charac- teristics of drain current, Ip for variations in gate-source voltage, Vas for a fixed value of Vps in the saturation region for all MOSFET types. 14] Field Effect TransistorDeptevon 4 Ernencemont Enancerent Deplaion Mes o Wes “Vas 0 Nes 0 Wes For the N-channel enhancement-mode MOSFET, (E-NMOS) Ip Is zero (channel- closed) when the gate-source voltage is less than Vp, and increases with posi- tive values of gate voltages. The N-channel depletion-mode MOSFET, (0-NMOS) operates in its depletion-mode when Ves is negative and closes the channel completely (1p = 0) if Ves is made sufficiently negative in value. When Ves is positive in value, the MOSFET changes and operates in enhance- ment-mode allowing the drain current to increase beyond Ipss. Note that Inss Is the drain current value that flows when V¢g = 0 and not the maximum drain current possible. For the P-channel enhancement-mode MOSFET, (E-PMOS) In is zero (channe!- closed) when the gate-source voltage is more positive than Vp, and increases with negative values of gate voltages. The P-channel depletion-mode MOSFET, (D-PMOS) operates in the enhance- ment-mode when Vgs Is negative allowing the drain current to increase beyond Ipss and in the depletion-mode when Vgs is positive. For the D-PMOS FET, the conductive channel closes completely (Ip = 0) if Ves is made sufficiently posi- tive in value. ‘As with the JFET device, we can show the behavior of the channel current by creating a set or family of output characteristics curves to show the relation- ship between the channel current Ip and gate-source voltage Vas for different values of drain-source voltage, Vos. www.electronics-tutorials,ws iaThe |-V characteristics of the N-channel Enhancement MOSFET show that the drain current is enhanced by a positive gate-to-source voltage, and for the P-channel E-MOSFET the drain current is enhanced by a negative gate voltage. Thus the channel conductance is a function of the amplitude of the input sig- nal. Yoo! The I-V characteristics of the N-channel Depletion MOSFET show that the drain current is enhanced by a positive gate voltage and reduced by a negative gate voltage. For the P-channel D-MOSFET the drain current is enhanced by a nega- tive gate voltage but reduced by a positive gate voltage. Thus the channel con- ductance Is a function of the polarity and the amplitude of the input signal. ry Field Effect TransistorThen we can summarised the effect of different values of Vcs on the channel in the following switching table. MOSFET TYPE Ves = +ve Vas = 0 Vos = -ve N-channel Depletion mode ON ON OFF N-channel Enhancement mode ON OFF OFF P-channel Depletion mode OFF ON ON P-channel Enhancement mode OFF OFF ON You may have noticed that the depletion-mode MOSFET can operate with either a positive or a negative gate-source voltage and because of this it is commonly used in amplifier circuits with the Q-point set to correspond when Ves = 0. Thus, if we restrict Ves to small variations around the loss Q-point, the relationship between variations in Ves and the resultant variations in ID will be linear. So when the amplifiers input signal goes positive, Ip increases above Ipss and when the input signal goes negative, Ip decreases below Ipss. Enhancement-type MOSFETs however, cannot be biased using the depletion-modes zero-biasing technique because the gate-source voltage Ves must be greater than Vp to open the channel allowing drain current to flow. This then makes the enhancement-mode MOSFET extremely useful as an electronic switching device as the Input gate voltage can be elther low or high and well above the pinch-off voltage, Vp operating the MOSFET between cut-off and ohmic regions for on- off switching applications.N-channel enhancement MOSFETs are the most widely used FET device for switching applications as their biasing arrangement is very simple to achieve. For example, the drain terminal is always biased positive relative to the source terminal, and the input gate-to-source voltage VGS which is used to control the conductivity of the channel between the drain and source is also a positive sig- nal turning the device is "ON" or “OFF”. Pda Peel Taal = Veg = 0 (LOW) ® Gate-source voltage less than pinch-off voltage Ves < VP = MOSFET is “OFF” ( Cut-off region ) = Maximum Channel Resistance >10MO = No drain current flows ( Ip = 0 Amps ) = Vout = Vos = Vop = “1” (HIGH) = MOSFET operates as an “open switch” When Veg = 0 volts, the channel is closed between drain and source as V Gs > V p, and so the device is switched “OFF” so Ip = 0. When using the E-NMOS device as a switch, the channel resistance in this OFF state Is ex- tremely high, typically over 10MQ, which for most applications is effectively an open circuit condition. The E-NMOS FET will remain in this off condition as long as Vos is zero or negative in value. For a P-channel enhancement MOSFET, the gate potential must be more positive with respect to the source. Field Effect TransistorVio = Vas is HIGH * Gate-source voltage greater than pinch-off Ro Ves > VP Vorz © MOSFET is "ON" ( saturation region ) 0.2¥ = Max drain current flows (Ip = Vop / Rp ) Resiou pg = OV (ideal saturation) Closed - - Saleh = Min channel resistance Rps(oN) < 10 = Vour = Vos = 0.2V due to Ros(on) = MOSFET operates as a “closed switch" When Vs Is made positive (gate positive relative to source), and greater than the pinch-off voltage Vp , (typically 1-to-2 volts for an E-NMOS FET) the conduc- tive channel opens and current flows between the drain and source terminals. Generally a Vs value much larger than Vp is used to turn the device “ON” com- pletely. Even though fully-on, the channel resistance does not drop completely to zero (00) due to the ON resistance RDs(ON) of the conducting channel resulting In a voltage drop of typically less than 1 volt across the drain-source terminals, Vos. ‘Thus a lower Ros(an) value for the channel resistance is a desirable parameter for a MOSFET as It helps to reduce the channels effective saturation voltage (Vps(sat) = !n*Rog(on) ) and the device will therefore operate at a cooler tem- perature. Power MOSFETs generally have a RDS(ON) value of less than 0.010 which allows them to run cooler, extending their operational life span. Thus by applying a suitable drive voltage to the gate of an FET, the resistance of the drain-source channel, RDs(oN) can be varied from an “OFF-resistance” of many hundreds of kQ, effectively an open circuit, to an “ON-resistance” of less than 10, effectively acting as a short circuit. P-CHANNEL MOSFET SWITCH As well as the N-channel MOSFET used as a switch where the MOSFET is placed between the load and the ground allowing the MOSFET's gate drive or switching signal to be referenced to ground (low-side switching). www.electronics-tutorials.wsFor P-channel enhancement-mode MOSFET the load is connected directly be- tween the drain terminal and ground as shown. ae The P-channel MOSFET operates in exactly the same way as the previous N-channel device except that the voltage polarities have been reversed. For the E-PMOS FET conventional flow of drain current is in the negative direction so a negative gate- source voltage greater than -Vp is applied to switch the transistor “ON”. Vorr Vou Thus the E-PMOS device is connected be- tween the load and the positive supply rail (high-side switching) while the drain terminal is connected to the load. Because the P-channel MOSFET is effectively “upside down" with its source terminal tied to the positive supply +Vpp, when the switch goes LOW, the MOSFET turns “ON” and when the switch goes HIGH the MOSFET turns “OFF”. Thus to turn an E-PMOS FET fully “ON’, an input voltage lower than the source voltage and greater than -Vp must be applied to the gate terminal, meaning the voltage at the gate, relative to the source, must be negative. One advantage of this upside down connection for a P-channel enhancement mode MOSFET switch is that it allows us to connect it in series with an N-chan- nel enhancement mode MOSFET to produce what Is called a complementary or CMOS switching device. Field Effect TransistorCMOS Switching To construct a CMOS switching device, two MOSFETs are connected together in series so that the P-channel device has its source connected to VDD (a positive voltage), and the N-channel device has its source connected to ground (a negative voltage). The gate terminals of the two MOSFETs are connected together to produce a common input. The drain terminals of the two MOSFETs are joined together to produce a common output. CMOS INVERTER 4Voq__ When the input is LOW the P-channel MOSFET is switched-ON as its gate-source junction is negatively biased so the output goes HIGH as it is connected to the mu positive +Vpp supply rail (high-side Vex, Switching). Thus drain current, |p1 flows out (current-source) from the MOSFET combination. P-channel MOSFET When the input is HIGH, the P-chan- nel device switches-OFF and the N-channel device switches-ON as its gate-source junction Is positively bi- ased. The output goes LOW as it is connected to ground and Ov, (low-side switching). Thus drain current, Ip2 flows into (current-sink) the MOSFET combi- nation. Then the P-channel MOSFET is used to switch the positive supply to the output, while the N-channel MOSFET is used to switch the negative supply to the out- put. This current-sink, current-source switching action makes the CMOS switch very useful for controlling the direction od DC motors connected to the output terminal. ‘Therefore because of the switching action of the two transistors, the output is LOW when the input is HIGH, and HIGH when the input is LOW effectively invert- ing the input signal so: Your = Vin. www.electronics-tutorials.ws EyField Effect Transistor Comparisons We can summarise the different types of Field Effect Transistor and their oper- ating modes in the following chart. The Field-Effect Metal Oxide Semiconductor FET Junction FET Depletion-mode Depletion-mode ihancement-made | N-channel | | P-channel N-channel P-channel N-channel} | P-channel D D D D D D s s s i} s s Biasing of the Gate for both the junction field effect transistor, (JFET) and the metal oxide semiconductor field effect transistor, (MOSFET) configurations are given as: Depletion Mode Depletion Mode Enhancement Mode Bias: ON OFF ON OFF ON OFF Nechannel | OV “ve av “ve We ov, P-channel | OV ve ov. ne we ov Py Field Effect Transistor@ ElectronicsTutorials® = Q encceririies Ac Create Actensatore capacitors inary Numbers ‘Combinational Logic DeCireits Diodes Electromagnetism Fitore Inductors InputiOvtpat Devices Legie Gates Operational Ampliners 6ec 0000680 00e000606 68 © eo0ooeoedcd @ @ Oxcilatr Power Electronics Power supplies RC Networks Resistors Sequential Logie systems Teandetors ‘Aspencore Media GmbH Copyright. Al rights reserved. Rauwagnersi 5 No pa" of this pudieation may be reproduced in any form o* by ary means 85560 Eberaberg / Germany Without the price exgress writen permission of Aspercore Media GmioH. ‘Akthough wemake every effort to present up-c-date. accurate information, Eorial Contact Electonics utile will nt be reeponsibie for any errs or emission or for Wayne Storr any results cbtalned from te use of such Information. Weto@aspencors.com ‘The digital tutorials will not be lable for any loss caused by the reliance on For Reader inquiries please contact; _infermation obtsined on this site. Wayne Storr wainrgheapcieert oa Furthermore ElectrovesTutoials does not warrant the acuracy oF completeness ofthe information, text graphics in this dgjtal magazine. The ‘opinions expresses inte sricies are those ofthe authors end not necessaily Edhorial Design ena the pinion ofthe publisher [ARTPOOL Communication Services win artpoolde 2s