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Brief Papers_______________________________________________________________________________
Highly Linear Receiver Front-End Adopting MOSFET Transconductance
Linearization by Multiple Gated Transistors
Tae Wook Kim, Bonkee Kim, and Kwyro Lee, Senior Member, IEEE
I. INTRODUCTION
Fig. 3. Schematic illustration of g cancellation using MGTR. The size and gate bias of ST is chosen such that the negative g peak of MT is cancelled by the
positive peak of ST.
Fig. 4. Analyzed CS equivalent circuit and qualitative explanation of combined effect of g and harmonic feedback to linearity.
in the HEMT community [9], and the multiple gated transistor We have shown that MGTR is an effective way to linearize the
method (MGTR) in CMOS community [10]. Note that the su- common-source (CS) MOSFET without increasing DC power
perposition in triode region concept is not suitable for receiver consumption [10]. However, it was also shown that the obtained
front-end because of the large power consumption. IIP DC improvement is much smaller than that expected from
In the area of mixer circuits, the Gilbert cell is certainly one linearity improvement in transconductance, which was shown
of the best candidates suitable for monolithic integration [11]. It to be due to various other harmonic mixing [16].
is composed of an RF transconductance amplifier and switching In this brief, we propose that the use of MGTR combined
stage, and its linearity is mostly determined by that of transcon- with other circuit techniques can indeed improve IP DC by
ductance [12]–[15]. an order of magnitude. First, adopting MGTR combined with
Therefore, it is very important to linearize MOSFET cascode configuration, we show the design and fabrication re-
transconductance for both RF amplifiers and mixer circuits. sults for 900-MHz CMOS LNA with IP DC improvement as
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004 225
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.اﺳت
see in Fig. 2 that has a negative peak value in the gate
drive voltage range of 0.1–0.45 V (gate-to-source voltage range
of 0.76–1.11 V in Fig. 2), which is the usual bias voltage for
high-gain, low-noise, and low-power applications. Thus, lin-
earity degradation is quite severe. In the MGTR amplifier, how-
ever, this negative peak of the of the main transistor (MT) can
be cancelled by the positive peak value of a properly sized sec-
ondary transistor (ST), whose transfer characteristic is shifted
to the right by changing either the gate bias or the threshold
voltage as shown in Fig. 3. Note that, because ST is biased in
subthreshold regime, this linearization method does not con-
sume any extra power.
Fig. 5. Simplified schematic of cascode MGTR LNA. It was shown later, however, that the third-order distortion
caused by the combination of and harmonic feedback be-
comes dominant in the highly linearized transconductance am-
plifier having very small [16]. Therefore, we have to con-
sider the role of various harmonics to further reduce IMD .
The effect of out-of-band termination on intermodulation dis-
tortion was originally analyzed for a bipolar common-emitter
amplifier circuit [17], and repeated for a FET one as follows:
IIP
(2)
Fig. 7. (a) Simplified schematic and plot of impedance versus frequency of conventional current source and LC resonating RF current source. The LC resonating
RF current source has maximum impedance at resonating frequency. Simplified schematic and simple explanation to common node (node A, B, C) characteristics
of: (b) conventional single balance mixer; (c) conventional folded cascode mixer; and (d) LC folded cascode mixer.
(a) (b)
Fig. 8. (a) Photomicrograph of cascode MGTR LNA whose size is
2
400 m 500 m. (b) Photomicrograph of MGTR mixer with tuned load
Fig. 10. IP comparison between conventional cascode and cascode MGTR
2
whose size is 1200 m 800 m.
LNA.
TABLE I
MEASUREMENT SUMMARY AND COMPARISON OF CASCODE MGTR
LNA AND CONVENTIONAL CASCODE LNA
circuit in Fig. 4), and is the unit current cutoff angular fre-
quency defined as . Note that is much
Fig. 9. IMD reduction vs ST gate drive voltage of cascode MGTR LNA. larger than .
In a typical CS FET amplifier, the magnitude of is on
Here, and are the impedance looking into the source the order of . Thus, the second term in the numerator
and into the load, respectively (see the analyzed CS equivalent of (5) is comparable to one. Furthermore, because ,
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004 227
Fig. 11. IP increase versus ST gate drive voltage for MGTR mixer with tuned Fig. 12. IP comparison of conventional mixer and MGTR mixer with tuned
load. load.
in the denominator is the most dominating factor. IV. DESIGN AND FABRICATION OF CASCODE MGTR LNA
Therefore, it is very important to reduce to less than AND MGTR MIXER WITH TUNED LOAD
one. In other words, should be decreased as much as pos-
sible. In [17], the harmonic tuning is used to reduce . In this A. 900-MHz Cascode MGTR LNA
paper, however, we first propose to use cascode configuration to The 900-MHz cascode MGTR LNA, whose schematic
reduce for RF amplifiers, as shown in Fig. 5. In the cascode is shown in Fig. 5, is designed and fabricated using only
configuration, is decreased to . Although this is not as CMOS in 0.35- m SiGe BiCMOS process. Fig. 8(a) shows a
good as the harmonic tuning, our approach is more plausible be- photomicrograph of the cascode MGTR LNA whose die area
cause it provides performance as good as the harmonic tuning is 400 m 500 m. The size of the MT is 360/0.35 m and
method and does not require large passive LC components as in that of ST is 440/0.35 m. The MT is typically biased at gate
[17]. drive (V V V , where V V) of 0.24 V
and V of ST is negative, i.e., ST is in subthreshold regime
when there is no input signal. Fig. 9 shows the measured IMD
III. MGTR MIXER WITH TUNED LOAD reduction versus V of ST, while V of MT is fixed at
0.24 V. Note that maximum IMD reduction as large as 20 dB
A highly linear mixer using MGTR in the transconductance
is obtained. Fig. 10 shows the measured IP at maximum IMD
combined with tuned load, which reduces harmonics at output,
reduction and comparison of conventional cascode amplifier.
is proposed. Fig. 6 shows the circuit schematic diagram for this
Note that IP improvement at least as large as 10 dB is obtained
circuit, which is composed of an LC folded cascode mixer [18]
from the proposed cascode MGTR over the 0.13-V window of
and an MGTR transconductor operating at 2.4-GHz ISM band.
V variation of ST, which is wide enough to cover process
and operate as switchs. and are load resistors
variation. The OIP of the proposed amplifier is 25.6 dBm at
which also work as common-mode feedback circuits with
7.8-mA current consumption. Measurement performance and
and . and reject the local oscillator (LO) signal at IF.
comparison with conventional amplifier are summarized in
Fig. 7 explains why the LC folded cascode mixer is the
Table I. Although it has slightly higher noise figure because of
best configuration for the MGTR transconductor. As shown in
ST, it improves IP by an order of magnitude.
Fig. 7(a), and are resonant at , providing maximum
load for the signal, while small impedance at the second-har-
monic frequency of and frequency as well as at B. MGTR Mixer With Tuned Load
the subharmonic frequency of . As was discussed for the A 2.4-GHz harmonic tuned MGTR mixer with LC folded
amplifier case, it is well known that , components at cascode structure, shown in Fig. 6, is designed and fabri-
the CS node (node A, in Fig. 7) worsen the linearity in the cated using 0.18- m CMOS technology. Fig. 8(b) shows
conventional single balanced mixer, which is greatly reduced a photomicrograph of the MGTR mixer whose die area is
using LC resonating RF current source [see Fig. 7(a)] as shown 1200 m 800 m. The MT is biased at a gate drive of 0.14 V
in Fig. 6. Also, the LC resonating RF current source removes (V V) and ST bias is below V . Input is terminated
the signal, which degrades linearity in conventional with a 50- resistor. Fig. 11 shows measured IP increase
single balanced mixer [19]. It should be noted here that versus V of ST where MT is fixed at V of 0.14 V. Max-
harmonic termination is adopted in [19], while the tuned imum IP increase is 7 dB and IP improvement is 5–7 dB over
load is used here, to reduce the component at the output. a 0.1-V range which can cover process variation. Fig. 12 shows
Moreover, linearization using MGTR is most effective when the measured IP at maximum IMD reduction and comparison
the driver FET used for the transconductance amplifier is in of conventional single-gate LC folded cascode mixer which has
saturation region, i.e., at large V . The folded cascode circuit only one transistor at transconductor stage. The measurement
in Fig. 7(d) helps us to have large voltage headroom for V , results of the conventional mixer and the harmonic tuned mixer
making the driver FET always in saturation region. are summarized in Table II. A higher noise figure is obtained
228 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004
TABLE II
MEASUREMENT SUMMARY AND COMPARISON OF CONVENTIONAL MIXER AND MGTR MIXER WITH TUNED LOAD
Fig. 13. Bias circuitry for MGTR. (a) Voltage bias. (b) Current mirror bias.
Fig. 14. (a) IIP over process, V 6 ( 30%), and temperature variation for voltage bias [Fig. 13(a)]. (b) IIP over process, V (30%), and temperature variation
for current mirror bias [Fig. 13(b)]. MG and SG stand for MGTR and single gate, respectively. TT, SS, and FF stand for typical, slow, and fast model, respectively.
6
Supply voltage variation is assumed 30%.