A NOVEL ARCHITECTURE FOR SUPPLY-REGULATED

VOLTAGE-CONTROLLED OSCILLATORS

A Thesis

Presented in Partial Fulfillment of the Requirements for the

Degree Master of Science in the

Graduate School of The Ohio State University

By

Anu Chakravarty, B. E.

Electrical & Computer Engineering Graduate Program

*****

The Ohio State University

2010

Thesis Committee:
Professor Mohammed Ismail, Adviser

Professor Waleed Khalil


c Copyright by

Anu Chakravarty

2010
 ABSTRACT

Voltage-controlled oscillators (VCOs) are critical components in the design of

phase-locked loops (PLLs) for a variety of applications such as high speed digital

communication systems, on-chip clock generators and RF transceivers. VCOs expe-

rience large supply noise variations due to digital switching currents. This degrades

the jitter performance of the VCO, thus limiting system performance.

Supply noise is a major concern in ring oscillators in particular, since the frequency

of a ring VCO is highly dependent on the supply voltage.

This thesis presents a novel power supply insensitive voltage controlled ring oscil-

lators. This thesis also discusses some previously adopted VCO buffer stage designs

implemented to achieve high supply noise rejection, and compares their results with

those achieved with the proposed architecture.

Based on the concepts developed in this thesis, a differential ring oscillator was

designed in a 0.13-um CMOS technology, to demonstrate the robustness against sup-

ply fluctuation. The VCO operates from 236.66 MHz to 373.33 MHz, and displays

complete rejection to power supply noise.

ii
This is dedicated to my family and friends

iii
 ACKNOWLEDGMENTS

I would like to acknowledge the contributions of people who were very helpful and

supportive throughout my research here at The Ohio State University.

I extend my sincere appreciation and gratitude to my advisor Professor Mo-

hammed Ismail for providing me academic guidance and opportunity to perform

research at the Analog VLSI Laboratory. I am grateful to him for providing me con-

siderable freedom in defining and directing my research. And , am really thankful to

him for being a wonderful mentor.

I am also indebted to my co-advisor, Dr. Waleed Khalil, whose wisdom and

expertise have enabled the successful completion of my thesis. He has helped me

concentrate all my efforts on this work and has provided me constant encouragement

and confidence throughout my research. He has always been there to clear my doubts

and has always inspired me with his enthusiasm to do novel research.

A special thanks to Bou-Sleiman at the Analog VLSI Lab for his continued support

and helpful advice.

I would like to thank my friends at Columbus with whom I have had many in-

teresting discussions and who have made my time at the department enjoyable. I

would like to thank Sarang Vadnerkar, Harsha, Mansi, Bhalchandra and Subhash

in particular for their constant support and encouragement. It has been a pleasure

having all of you around.

iv
 Finally, I would like to thank my family, my mother, my father and my sister for

their continued love and support. I am really grateful to them for providing me a

good home and for encouraging me to study as far as I can. I could not have asked

for better parents and am really thankful to them for never losing confidence in me,

even when I was beginning to doubt my own capabilities.

v
 VITA

January 3, 1985 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Born - New Delhi, India

June 30, 2007 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B.E. First Class with Distinction

Electrical and Electronics Engg.,
Netaji Subhas Institute of Technology,
New Delhi, India
September 2007 - December 2009 . . . . . . . . . . . The Analog VLSI Lab,
The Ohio State University.

FIELDS OF STUDY

Major Field: Electrical and Computer Engineering

Studies in Analog and Mixed Signal Circuit Design : Prof. Mohammed Ismail

vi
 TABLE OF CONTENTS

Page

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii

Dedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

Vita . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x

Chapters:

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.1 Maneatis Delay Cell . . . . . . . . . . . . . . . . . . . . . . 5
1.2.2 Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2. Oscillator Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Criteria for Oscillation . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1.1 Magnitude Criterion . . . . . . . . . . . . . . . . . . . . . . 10
2.1.2 Phase Criterion . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Types of Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.1 Ring Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2 LC-Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Voltage-controlled Oscillators . . . . . . . . . . . . . . . . . . . . . 14
2.4 Oscillator Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 15

vii
3. Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 Maneatis Delay Cell . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1.1 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Wilson and Moon Calibration Technique - Sub-banding . . . . . . . 20
3.2.1 VCO Design . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . 26

4. Voltage-Controlled Oscillator Design and Analysis . . . . . . . . . . . . . 30

4.1 VCO Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.2 Filtering effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2.1 Path from the output of the first stage to the input of the
second stage: . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.2.2 Path from the supply to the input of the delay stage: . . . . 40
4.3 Bias Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.4 Bias Generation Block . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.4.1 Derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.4.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.5 Digital Calibration Block . . . . . . . . . . . . . . . . . . . . . . . 46
4.6 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.6.1 Simulation @ VCT RL = 50 mV . . . . . . . . . . . . . . . . 49
4.6.2 Simulation @ VCT RL = 200 mV . . . . . . . . . . . . . . . . 51
4.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5. Future Work and Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.1 Design Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.2 Future Extensions and Major Contributions . . . . . . . . . . . . . 55
5.2.1 Resistor tun-ability . . . . . . . . . . . . . . . . . . . . . . . 55
5.2.2 Increasing the frequency of operation . . . . . . . . . . . . . 55
5.2.3 Sub-banding . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Appendices:

A. Complete Circuit Schematics . . . . . . . . . . . . . . . . . . . . . . . . 58

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

viii
 LIST OF TABLES

Table Page

3.1 Effect of supply variation on frequency (KF V SU P ) . . . . . . . . . . . 29

4.1 Variation of frequency with change in supply @ VBIAS = 0 volts . . . 37

4.2 Bias Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.3 Bias voltage variation to maintain constant oscillation frequency . . . 43

4.4 Variation of frequency with change in supply @ VCT RL = 50 mV . . . 50

4.5 Variation of frequency with change in supply @ VCT RL = 200 mV . . 51

ix
 LIST OF FIGURES

Figure Page

1.1 Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Differential Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 LC-Tank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.4 LC-VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.5 Maneatis Delay Cell with Symmetric Load . . . . . . . . . . . . . . . 5

1.6 Maneatis Delay Cell with Replica Feedback . . . . . . . . . . . . . . . 6

1.7 Self-Calibration Technique . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Block diagram of a feedback system . . . . . . . . . . . . . . . . . . . 10

2.2 Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Differential CMOS LC Oscillator . . . . . . . . . . . . . . . . . . . . 13

2.4 Definition of a VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Differential buffer stage with MOS symmetric load elements [1], [2], [3] 18

3.2 Symmetric load I-V characteristics, dashed lines show the effective re-
sistance of the loads and highlights the symmetry of the I-V charac-
teristics [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3 Self-biased replica-feedback current source bias circuit for the differen-
tial buffer stage [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

x
3.4 Maneatis VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.5 Voltage-controlled oscillator - Wilson and Moon [4] . . . . . . . . . . 22

3.6 2L operating modes of VCO [4] . . . . . . . . . . . . . . . . . . . . . 23

3.7 Voltage-controlled oscillator - Wilson and Moon . . . . . . . . . . . . 24

3.8 Voltage-current converter . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.9 Current multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.10 ICO - delay stage 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.11 ICO - delay stage 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.12 Reduction in KV CO due to sub-banding . . . . . . . . . . . . . . . . . 28

4.1 Overall VCO block diagram . . . . . . . . . . . . . . . . . . . . . . . 30

4.2 Delay stages followed by RC . . . . . . . . . . . . . . . . . . . . . . . 31

4.3 Delay Stage with RP and RN . . . . . . . . . . . . . . . . . . . . . . 32

4.4 Three Stage Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . 33

4.5 Delay stage with PMOS load . . . . . . . . . . . . . . . . . . . . . . . 34

4.6 Three Stage Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . 35

4.7 Effect of variation in supply voltage @ fixed VBIAS - Frequency spec-

trum (DFT using hamming window) @ VBIAS = 0 V, . . . . . . . . . 36

4.8 Delay stage followed by resistor and capacitor (Filter effect) . . . . . 37

4.9 High-pass filter effect . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.10 HPF - Effect of varying RB and CB . . . . . . . . . . . . . . . . . . . 39

4.11 Low-pass filter effect . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

xi
4.12 LPF - Effect of varying RB and CB . . . . . . . . . . . . . . . . . . . 41

4.13 Bias voltage VBIAS variation with VSU P . . . . . . . . . . . . . . . . . 43

4.14 (VDD − 1.1)0.6 + VCT RL Implementation . . . . . . . . . . . . . . . . 45

4.15 Digital calibration block . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.16 Digital Calibration Algorithm . . . . . . . . . . . . . . . . . . . . . . 47

4.17 Resistor tunability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.18 VCO - voltage output @ VCT RL = 50mV . . . . . . . . . . . . . . . . 49

4.19 Frequency spectrum (DFT using hamming window) @ VCT RL = 50mV 50

4.20 Frequency spectrum (DFT using hamming window) @ VCT RL = 50mV 51

R1X
5.1 Resistor tun-ability (KF V SU P = R0
) . . . . . . . . . . . . . . . . . . 55

5.2 Ring oscillator - adding another stage of RB-CB network . . . . . . . 56

A.1 Manetais VCO with symmetric loads and replica-feedback . . . . . . 59

A.2 Voltage-controlled oscillator - Wilson and Moon . . . . . . . . . . . . 60

A.3 Voltage-current converter . . . . . . . . . . . . . . . . . . . . . . . . . 61

A.4 Current multiplier - Wilson and Moon . . . . . . . . . . . . . . . . . 62

A.5 ICO - delay stage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

A.6 ICO - delay stage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

A.7 Proposed voltage-controlled oscillator . . . . . . . . . . . . . . . . . . 65

xii
 CHAPTER 1

INTRODUCTION

This thesis focuses on the design and simulation of a power supply insensitive

voltage-controlled ring oscillator. The first section presents the reasons to develop

a ring VCO that has high power supply rejection ratio (PSRR). It discusses the

difference between ring oscillators and LC-VCOs, which have better supply noise

rejection by definition. Section 1.2 discusses some of the relevant, existing research.

Some of the techniques in this thesis are derived from the works mentioned here. The

last section lists the format of the remaining thesis.

1.1 Motivation

Voltage-controlled ring oscillators are used in a variety of integrated circuit ap-

plications because of their ability to generate delays with very high precision at high

operating frequencies. They are extensively used in phase-locked loops (PLLs)in high

performance applications such as clock recovery, clock generation and frequency syn-

thesis. In such applications the VCOs jitter performance can impact the output clocks

timing jitter, thus limiting system performance.

With the scaling of CMOS technology, and enhanced levels of integration more

noise is coupled from the switching of digital circuits. This noise translates to jitter

1
at the the output and directly impacts the signal purity [5], [6]. Consequently, the

design of VCOs that are noise tolerant is vital. In particular, for ring VCOs, supply

noise is a major design concern as the oscillation frequency of a ring VCO is highly

dependent on the supply voltage. This thesis, therefore, is the design of a ring VCO

with complete rejection to power supply noise.

Two principal topologies for the modern monolithic VCOs exist. They are the

ring oscillator and LC-oscillator topologies [7], [8]. The ring oscillator, is composed

of a ring of inverters with a net inversion around the loop as shown in Figure 1-

1. This is achieved by using a chain of odd number of inverters. The frequency of

oscillation is a function of the delay through each stage and the number of stages.

To change the oscillation frequency the propagation delay of each stage could be

adjusted in a number of ways, such as varying the current through each stage of

varying the capacitative load at the output of each stage. The ring oscillator could

Figure 1.1: Ring Oscillator

2
also be implemented using differential signaling by flipping the output of the last

stage as it is fed back to the input of the first stage, as shown in Figure 1-2. In this

thesis differential signaling approach is used, as it helps improve noise performance.

The other class of VCOs, the LC-oscillator,is a subclass of resonant oscillators. The

Figure 1.2: Differential Ring Oscillator

circuit oscillates at the resonant frequency of the inductor and the capacitor, ωo =

√1 . In an ideal LC-tank with no resistive losses, the inductor and capacitor oscillate
LC

indefinitely. However, since in practice it is impossible to build lossless passive circuits,

active devices are used to produce negative resistance to cancel out any parasitic losses

in the tank, as shown in Figure 1-3. A simple differential LC-VCO is shown in Figure

1-4.

Figure 1.3: LC-Tank

3
 Figure 1.4: LC-VCO

The LC-tank inherently has excellent supply noise rejection since the frequency

of oscillation is a function of only the values pf the inductor ans the capacitor. These

values do no vary with supply fluctuations hence the frequency of oscillation is rel-

atively stable. Also, the LC-tank inherently filters out frequencies away from the

resonant peak, thus improving phase noise performance. However the tuning range of

LC-VCOs is limited compared to the ring oscillator since tuning is achieved by using

a varactor as voltage controlled capacitance, which has limited tuning range.

4
1.2 Previous Work

To suppress the change in frequency of a ring VCO with supply noise, many

methods have been adopted. Some of them use differential structures [9], voltage

regulators [10] and calibration techniques [4]. Others use compensation techniques to

cancel the VCOs intrinsic positive supply sensitivity with additional negative supply

sensitivity circuitry [11], [12].

This thesis, draws comparison between the new proposed approach and the exist-

ing approaches by Maneatis [1], [2] and Wilson and Moon [4].

1.2.1 Maneatis Delay Cell

The Maneatis delay cell [1], [2], [3] as shown in Figure 1-5 relies on symmetric

loads and dynamic biasing to achieve VCOs with superior power supply rejection

and wide tuning range. The concept behind using symmetric loads is that the load

Figure 1.5: Maneatis Delay Cell with Symmetric Load

5
elements should ideally have linear I-V characteristics which helps provide differential-

mode resistance that is independent of common-mode voltage . Since the delay of the

buffer stage is dependent only on the differential mode resistance, it is not affected

by the common-mode disturbances resulting from the supply noise. However since

adjustable resistive loads made with real MOS devices do not maintain linearity

while generating wide frequency range, Maneatis proposes the concept of symmetric

loads which have symmetric I-V characteristics. This symmetric characteristics helps

inhibit the conversion of common-mode noise into differential-mode noise, and hence

achieves high supply noise rejection. Maneatis also uses the concept of replica-bias

Figure 1.6: Maneatis Delay Cell with Replica Feedback

to vary the current in the buffer delay stage to provide correct symmetric load swing

limits . The replica-bias also helps counteract the effect of finite output impedance

6
of the NMOS current tail source to achieve high supply noise rejection as shown in

Figure 1-6.

1.2.2 Self-Calibration

Wilson and Moon [4] employ the concept of self-calibration techniques to design

low-noise frequency synthesizers. They use a digitally programmable VCO as shown

in Figure 1-7, that helps cover wide range of output frequencies while keeping a very

low control voltage to output frequency gain. This is the sub-banding approach to

achieve lower VCO gain that has been proposed for the new architecture as well,

to achieve lower Kvco, and hence lower jitter at the output. The self-calibration

approach helps overcome a significant amount of process variation. This concept of

self-calibration is also incorporated in this thesis as part of future work. The concepts

Figure 1.7: Self-Calibration Technique

of variable resistive loads to achieve better supply noise rejection and self-calibration

to overcome process variations are used in this thesis to develop a novel power supply

insensitive voltage-controlled oscillator architecture.

7
 The Maneatis and Wilson and Moon, architectures are further discussed in detail

in chapter 3.

1.3 Thesis Outline

The next chapter deals with general oscillator theory, explaining different oscillator

types and parameters.

The second chapter describes the proposed novel voltage-controlled oscillator ar-

chitecture. The simulation results are also presented in this chapter.

Chapter three discusses the Maneatis architecture, its variations and the Wilson

and Moon architecture in detail.

Chapter four compares the simulation results of the new VCO with those achieved

with existing architectures developed to reduce supply noise rejection.

Finally, Chapter 5 reviews the principal contributions of this thesis and includes

a number of suggestions for future work using the ideas presented herein.

8
 CHAPTER 2

OSCILLATOR THEORY

Oscillators have been essential components since Edwin Armstrong discovered

the heterodyne principle, wherein they effect frequency translation by multiplying the

oscillators signal with other input signals. Since then oscillators have been an integral

part of many electronic systems. Their applications range from clock generation to

carrier synthesis, and are one of the most challenging blocks in the design of a PLL.

This theoretical chapter deals with the design of CMOS oscillators, more specifi-

cally voltage-controlled oscillators (VCOs) [7], [8]. It discusses the criteria that must

be fulfilled by a circuit to produce oscillations, introduces the two main types of os-

cillators, the ring oscillator and the LC-oscillator. It further discusses the methods

of varying the oscillators output frequency and finally lists some of the important

performance metrics used to evaluate oscillators.

2.1 Criteria for Oscillation

A simple oscillator produces a periodic output, usually a voltage signal. The

oscillator circuit has no input however it sustains an output indefinitely. This is

possible only if the overall feedback becomes positive in an amplifier. Thus, the

9
behavior of oscillators can be modeled as a feedback system as shown in Figure 2-

1. In the block diagram, block A represents an amplifier and block β represents a

Figure 2.1: Block diagram of a feedback system

feedback network that is connected from the output of the amplifier to its input.

The two conditions that are necessary but not sufficient to make a circuit oscillate

are defined as the ”Barkhausen Criteria”. When using the notations of the model in

Figure 2-1, this criteria can be given as

Aβ = 1 (2.1)

The criteria can be divided into two parts, i.e, the magnitude criterion and the phase

criterion.

2.1.1 Magnitude Criterion

The magnitude criterion for oscillation states that the gain Aβ of the oscillator

loop must be equal to one during standard operation. In practice the loop gain has

to be larger than one for the oscillator to begin to oscillate and for the oscillation am-

plitude to grow. The amplitude will eventually saturate due to device nonlinearities,

reducing the loop gain to one and providing a signal with stable amplitude.

10
2.1.2 Phase Criterion

The phase criterion for oscillation states that the phase shift of the oscillator loop

must be zero or a multiple of 2π. This means that the signals with the same phase

are summed at some point in the oscillator. If the phase shift was an odd multiple of

π, then the signals would have opposite phases and would cancel each other out. In

that case there will be no oscillation.

2.2 Types of Oscillators

2.2.1 Ring Oscillators

Ring Oscillators are a subset of the class of delay based oscillators wherein one

or more delay elements are connected in feedback configuration. A ring oscillator

consists of a number of gain stages in a loop. Figure 2-2 shows the schematic of a

three stage inverter ring oscillator. The oscillation frequency fo of the oscillator can

Figure 2.2: Ring Oscillator

11
be calculated as:
1
fo = (2.2)
3(T1 + T2 )

where T1 is the delay of the rising edge and T2 is the delay of the falling edge. The

delay varies with change in bias current or supply voltage and hence changes the

frequency of oscillation.

Delay based oscillators have poor phase noise-performance compared to resonator

based oscillators. However, since delay based oscillators do not need an inductor to

operate, they can be implemented using small chip area. Ring oscillators also have

another advantage of high tuning-range. Ring oscillators have a major disadvantage

though, i.e, they are highly susceptive to supply noise, which effects the delay of each

stage and hence the frequency of oscillation.

Thus, in thesis, we discuss a new approach to build the ring oscillator such that it

is completely insensitive to power supply noise. This architecture uses the differential

implementation of delay stages, which help cancel out common-mode noise. Differen-

tial implementations also may use even number of delay cells by simply configuring

one cell such that it does not invert. This flexibility demonstrates another advantage

of differential circuits over single-ended counterparts.

2.2.2 LC-Oscillators

LC-oscillator belongs to the class of resonator based oscillators, which are the most

common topology in radio applications. In resonator based oscillators, the oscillation

frequency is determined by a resonance circuit such as an LC-tank. An amplifier

compensates for the loss in the resonance circuit and keeps a sustained oscillator.

12
 Figure 2-3 shows an LC-VCO. Due to the differential architecture and relatively

good phase noise it is one of the most popular oscillator configurations used in fully

differential integrated RF CMOS applications. The LC-VCO contains two major

Figure 2.3: Differential CMOS LC Oscillator

parts, the passive LC tank which determines the frequency of oscillation and the

active devices that compensate the loss in the tank. The LC tank contains an inductor

(L) and capacitor (C). The oscillator will oscillate at a frequency where the reactance

of the inductor cancels the reactance of the capacitor.

The oscillation frequency is given by the equation:

1
fo = √ (2.3)
LC

In order to vary the frequency of oscillation, the capacitor is often implemented using a

voltage-controlled capacitor (varactor) or an array of digitally controllable capacitors,

13
or a combination of both. The other ways of tuning the frequency are varying the

inductance using MEMS or by changing the bias current.

The LC-VCO is highly insensitive to supply noise fluctuations since the frequency

is a function of discrete components L and C only. However, this thesis intends to

develop delay stage architectures for ring VCOs such that the oscillation frequency is

independent of supply noise fluctuations.

2.3 Voltage-controlled Oscillators

Applications such as clock recovery and clock synthesis, require the oscillators to

be ”tunable”. Tunability means that the output frequency must be a function of

some control input, usually voltage. This voltage could be for example the output of

the loop filter in an analog PLL. In an ideal voltage-controlled oscillator, the output

frequency is a linear function of its control voltage.

ωOU T = ωO + KV CO VCON T (2.4)

Where ωOU T represents the intercept corresponding to VCON T = 0 and KV CO denotes

Figure 2.4: Definition of a VCO

14
the ”gain” or ”sensitivity” of the circuit (expresses in rad/s/V). The achievable range,

ω2 − ω1 is called the ”tuning range” as shown in Figure 2-4.

2.4 Oscillator Parameters

Some of the important performance metrics of the voltage-controlled oscillator

are discussed below. These parameters help select the best oscillator for a particular

application.

Oscillation frequency

The oscillation frequency f0 or the fundamental frequency of an oscillator is defined

as the frequency at which the main peak in the oscillator’s output spectrum is located.

Frequency tuning range

The tuning range of an oscillator is defined as the distance between the lowest

and highest output frequencies that the oscillator can produce.

T uning − range = fmax − fmin (2.5)

Tuning voltage or tuning current range

The tuning voltage(or current) range refers to the range of acceptable voltages (or

currents) that can be applied to the tuning circuitry of an oscillator.

Frequency tuning curve

The frequency tuning curve is a graphic representation of what happens to the

oscillators output frequency as the tuning voltage(or current) is swept through the

acceptable range. It is usually desirable that the tuning curve is monotonic.

15
Phase noise

Phase noise is a measure of the frequency stability of an oscillator. It is defined as

the output signal power at a certain offset fm from the carrier frequency f0 and the

power of the carrier, both within a 1-Hz bandwidth. It is usually given in dBc/Hz.

P (fm )
L(fm ) = 10log( ) (2.6)
P (f0 )

Pushing figure

The pushing figure of an oscillator gives the dependence of the output frequency

on the supply volatge. It is usually given in MHz/V.

∆f
P ushing − f igure = (2.7)
VSU P max − VSU P min

Pulling Figure

The pulling figure indicates how dependent the oscillator’s output frequency is on

the value of load impedance.

∆f
P ulling − f igure = (2.8)
RLOADmax − RLOADmin

16
 CHAPTER 3

PREVIOUS WORK

3.1 Maneatis Delay Cell

The voltage-controlled oscillator architecture proposed by Maneatis uses a differ-

ential buffer stage with symmetric load elements and self-biased replica feedback, to

have high supply noise immunity, while operating at low supply voltages. In this ar-

chitecture, digital calibration is not employed to achieve supply rejection, unlike the

architecture proposed in this thesis in chapter 3. The concept is that, high supply re-

jection can be achieved with high output impedances. This can be done by cascoding

the load impedances in the delay stages. However, since cascoding is incompatible

with low-voltage circuit design, Maneatis proposes the use of a current source bias

circuit, thus enabling the buffer stages to have high supply rejection without cascod-

ing. Symmetric load elements are also used in the buffer stages to enable supply noise

cancellation.

Differential buffer stage

The buffer stage used, is based on an NMOS source-coupled pair with symmetric

load elements and a dynamically biased NMOS current source as shown in Figure

17
Figure 3.1: Differential buffer stage with MOS symmetric load elements [1], [2], [3]

3-1. The bias voltage of the simple NMOS cell continuously adjusts itself to provide

a supply independent bias current. Since, the output swing is referenced to the top

supply, the current source helps isolate the buffer from the supply and hence, helps

achieve constant buffer delay.

The load elements are composed of symmetric loads i.e, a diode connected PMOS

device in shunt with an equally sized biased PMOS device. These loads are called

symmetric loads because their I-V characteristics is symmetric about the center of the

voltage swing as shown in Figure 3-2. The control voltage, VCT RL biases the PMOS

device and helps generate the bias voltage for the NMOS current source and hence

controls the delay of the buffer stage.

Current source bias circuit

The current source bias circuit as shown in Figure 3-3, helps set the current

through a simple NMOS current source in the buffer delay stage to provide the correct

18
Figure 3.2: Symmetric load I-V characteristics, dashed lines show the effective resis-
tance of the loads and highlights the symmetry of the I-V characteristics [1]

symmetric load swing limits and also helps adjust the NMOS current source bias so

that the current is held constant and independent of supply voltage. The current

source bias circuit uses replica of half the buffer stage and a single-stage differential

amplifier. The amplifier adjusts the current output of the NMOS current source so

that the voltage at the output of the replicated load element is equal to the control

voltage. This helps set the correct swing limits for the symmetric load.

3.1.1 Implementation

The maneatis delay cell with symmetric loads and replica-feedback bias generator

was implemented in cadence 130-nm. The VCO circuit was modified by shorting the

differential pair tail nodes of the delay cells. This enables their tail node voltage to be

more or less constant and closer to that generated by the bias generator. Simplified

schematic of the voltage-controlled oscillator is shown in this section Figure 3-4, and

the full schematics can be seen in Appendix-A.

19
Figure 3.3: Self-biased replica-feedback current source bias circuit for the differential
buffer stage [1]

3.2 Wilson and Moon Calibration Technique - Sub-banding

The self-calibration technique used by Wilson and Moon [4] enables the design

of low-noise frequency synthesizers without compromising on the frequency range

of operation. Since the output frequency of an oscillator covers a wide range of

frequencies for a limited range of input voltage, the gain of the VCO is high. This

leads to hight output jitter and phase noise.

The digital calibration technique is used to make a programmable VCO , which

covers a wide range of frequencies while keeping a low control voltage to output

frequency gain (KV CO ). This helps reduce the phase noise and output jitter consid-

erably.

The digital word is generated using a self-calibration algorithm. The process vari-

ations are also compensated for by the self-calibration technique. This sub-banding

20
Figure 3.4: Maneatis VCO

21
technique can also be incorporated in the proposed design to reduce th oscillator gain

KV CO and further improve the noise sensitivity.

3.2.1 VCO Design

The VCO is made up of a voltage-to-current converter (V-I), current multiplier

(IX) and current-controlled oscillator (ICO) as shown in Figure 3-5. The VCOs L-

Figure 3.5: Voltage-controlled oscillator - Wilson and Moon [4]

bit programmability is attained by the current multiplier, which controls the current

flowing into the the ICO. The operating range of the VCO is distributed into 2L

modes. This concept is illustrated in Figure 3-6. One of the operating modes is

chosen using the L-bit control word depending on the desired frequency of operation.

This results in a small output frequency to control voltage transfer function and thus

provides low sensitivity to noise.

22
 Figure 3.6: 2L operating modes of VCO [4]

3.2.2 Implementation

The V-I converter, current multiplier and ICO were implemented in cadence 130-

nm, and a five bit control word was used to provide sub-banding. Simplified schemat-

ics of these blocks are shown in this section, and the full schematics can be shown in

Appendix-A. The complete block diagram of the VCO is shown in Figure 3-7. The

building blocks are further discussed in detail in the following subsections.

V-I Converter

The V-I converter consists of a n-channel and a p-channel differential pair as

shown in Figure 3-8. One side of each of the differential pairs is connected VRF which

is equal to half the supply voltage. The other transistor’s gate is connected to VRF or

VLF , based on the output of the comparator. The current from the two pairs depends

23
Figure 3.7: Voltage-controlled oscillator - Wilson and Moon

24
on the voltages VRF or VLF , and finally the summation of the two currents is applied

to the current multiplier.

Figure 3.8: Voltage-current converter

Current Multiplier

The current multiplier is implemented with binary weighted transistors, as shown

in Figure 3-9. The control word used is five bits. The maximum current output of

the multiplier is 31 times the input current.

ICO

The ICO is implemented using three delay stages in cascade. The first stage also

consists of a half-replica buffer to generate the control voltage VCT RL , applied to the

25
 Figure 3.9: Current multiplier

gates of the PMOS loads of the following delay stages. The circuit diagram for the

delay stages are shown in Figure 3-10 and Figure 3-11.

3.2.3 Simulation Results

A five bit control word was used to generate 32 operating modes. The multiplied

current for each of these modes was generated using the current multiplier and the

resulting frequency of operation was measured with varying control voltage VCT RL .

VCT RL was varied from 0 to 1.2 volts and the resulting oscillator gain was calculated

for each operating mode. Without sub-banding the KV CO of the VCO would have

been (5.618 GHz - 2.9586 GHz )/1.2 Volts , i.e, 2.216 GHz/V. However, by using the

sub-banding technique the KV CO has been reduced to a few hundred megahertz. This

reduction in the oscillation gain helps reduce the output jitter and reduces the phase

noise of the VCO. The results with sub-banding are shown in the following excel sheet

Figure 3-12. The effect of supply noise on frequency was also reduced considerably,

26
Figure 3.10: ICO - delay stage 1

Figure 3.11: ICO - delay stage 2

27
 L Overlap Percentage Percentage
(Multi Imin Imax Vmax Fmax-Fmin Diff Max Overlap Upper Overlap diff Overlap Lower KVCO
plier) Vmin (uA) Fmin (GHz) Fmax (GHz) (uA) (V) (GHz) Side End (%) Min side End (%) (MHz/V)
1 0 25 0.9921 1.1403 30 1.2 0.1482 no overlap 123.4895
2 0 50 1.5898 1.7794 60 1.2 0.1895 no overlap no overlap 157.9453
3 0 75 2.0202 2.2371 90 1.2 0.2169 no overlap no overlap 180.7787
4 0 100 2.3810 2.6110 120 1.2 0.2300 no overlap no overlap 191.6781
5 0 125 2.6810 2.9326 150 1.2 0.2516 no overlap no overlap 209.6551
6 0 150 2.9586 3.2258 180 1.2 0.2672 no overlap no overlap 222.6888
7 0 175 3.1746 3.4843 210 1.2 0.3097 0.2585 83.4677 0.2160 80.8390 258.0978
8 0 200 3.3784 3.6630 240 1.2 0.2846 0.1787 62.7784 0.2038 65.7939 237.1877
9 0 225 3.5714 3.8610 270 1.2 0.2896 0.1980 68.3761 0.1931 67.8261 241.3127
10 0 250 3.7313 4.0323 300 1.2 0.3009 0.1713 56.9112 0.1599 55.2239 250.7623
11 0 275 3.8911 4.2017 330 1.2 0.3106 0.1694 54.5416 0.1597 53.0739 258.8584
12 0 300 4.0486 4.3668 360 1.2 0.3182 0.1651 51.8908 0.1575 50.7138 265.1910
13 0 325 4.1841 4.4843 390 1.2 0.3002 0.1175 39.1376 0.1355 42.5848 250.1704
14 0 350 4.3103 4.6083 420 1.2 0.2980 0.1240 41.6143 0.1262 42.0528 248.2918

28
15 0 375 4.4248 4.7170 450 1.2 0.2922 0.1087 37.1955 0.1144 38.4071 243.5020
16 0 400 4.5249 4.8077 480 1.2 0.2828 0.0907 32.0755 0.1001 34.2599 235.6712
17 0 425 4.6296 4.9020 510 1.2 0.2723 0.0943 34.6154 0.1047 37.0370 226.9426
18 0 450 4.7393 4.9505 540 1.2 0.2112 0.0485 22.9847 0.1097 40.2844 175.9655
19 0 475 4.8077 5.0505 570 1.2 0.2428 0.1000 41.1881 0.0684 32.3718 202.3440
20 0 500 4.8544 5.0505 600 1.2 0.1961 0.0000 0.0000 0.0467 19.2235 163.4464
21 0 525 4.9505 5.1282 630 1.2 0.1777 0.0777 43.7229 0.0961 49.0098 148.0917
22 0 550 5.0000 5.1813 660 1.2 0.1813 0.0531 29.3040 0.0495 27.8571 151.1226
23 0 575 5.0251 5.2356 690 1.2 0.2105 0.0543 25.7772 0.0251 13.8550 175.3971
24 0 600 5.0761 5.3191 720 1.2 0.2430 0.0835 34.3805 0.0510 24.2386 202.5057
25 0 625 5.1282 5.3476 750 1.2 0.2194 0.0284 12.9654 0.0521 21.4245 182.8237
26 0 650 5.1813 5.4054 780 1.2 0.2241 0.0578 25.8021 0.0531 24.2228 186.7152
27 0 675 5.2033 5.4054 810 1.2 0.2021 0.0000 0.0000 0.0220 9.8127 168.3934
28 0 700 5.2632 5.4945 840 1.2 0.2313 0.0891 38.5135 0.0598 29.6056 192.7897
29 0 725 5.3191 5.5249 870 1.2 0.2057 0.0304 14.7567 0.0560 24.2021 171.4275
30 0 750 5.3191 5.5249 900 1.2 0.2057 0.0000 0.0000 0.0000 0.0000 171.4275

Figure 3.12: Reduction in KV CO due to sub-banding

31 0 775 5.3763 5.5556 930 1.2 0.1792 0.0307 17.1271 0.0572 27.8034 149.3429
32 0 800 5.4054 5.5556 960 1.2 0.1502 0.0000 0.0000 0.0291 16.2162 125.1251
33 0 825 5.4348 5.6180 990 1.2 0.1832 0.0624 34.0741 0.0294 19.5652 152.6624
as shown below in Table 3.1. However, even better supply rejection is acheived using

the proposed architecture as discussed in Chapter 4.

VSU P (V) Itail KF V SU P Sensitivity

1.1 1.2 1.3 (µA) (MHz/V) (percentage/V)
1.3262 1.3245 1.3210 219.72 26 0.66
1.5723 1.5673 1.5698 259.72 12.34 0.78
1.8050 1.7985 1.7985 305 32 1.8
2.0325 2.0161 2.0161 350 81 4.065
Freq (GHz) 2.2421 2.2271 2.2222 412.5 99 4.48
2.4330 2.4213 2.4213 450 58.9 2.43
2.6109 2.6041 2.6109 500 33 1.3
2.7777 2.7855 2.7932 550 77 2.78
2.9201 2.9480 2.9600 600 200 6.77

Table 3.1: Effect of supply variation on frequency (KF V SU P )

29
 CHAPTER 4

VOLTAGE-CONTROLLED OSCILLATOR DESIGN AND

ANALYSIS

The VCO, with the overall block diagram as shown in Figure 4-1, is composed

of the voltage-controlled oscillator block, the bias voltage generation block and the

digital calibration block. The VCO, a ring oscillator, consists of three differential

Figure 4.1: Overall VCO block diagram

delay stages connected in a loop. The output of each delay stage is followed by

a capacitor and a resistor before feeding the output to the input of the next delay

stage, as shown in Figure 4-2. The capacitor is used to remove the DC from the output

and the resistor is used to fix the DC of the output to 0.6 volts. This ensures that

30
 Figure 4.2: Delay stages followed by RC

variation in the common-mode value of the output, with supply voltage fluctuations,

does not effect the DC value of the input of the next stage. The capacitor and resistor

values are chosen very carefully, to make sure that they do not attenuate the output

signal being fed into the next stage.

The concept is that the slope KF V SU P , i.e, the maximum variation in oscillation

frequency with respect to the worst case variation in supply volatge needs to be

measured and fed into the digital calibration block at VCO start-up. Next the control

voltage VCT RL , for example the output voltage of the loop filter in a PLL, is added

to the VREF voltage in the VBIAS Generation block. VBIAS is generated in this block,

by using the equation 4.1,

VBIAS = (VSU P − 1.1)KF V SU P + VCT RL (4.1)

where, VSU P , is the varying supply voltage. The derivation of this equation is dis-

cussed in detail in section 4.2. VBIAS , the ”tuning voltage”, is then used to vary the

frequency of oscillation of the VCO.

The first section describes the simple VCO core, with VBIAS as the voltage input

and FOU T as the output oscillation frequency. Section 4.2 presents the simulation

31
curves which lead to the derivation of equation (4.1). Section 4.3 discusses the cal-

ibration block in detail. Section 4.4 discusses another possible architecture for the

VCO. Finally, the simulation results are presented and discussed in Section 4.5. Some

of the ideas for the implementation of the calibration and bias generation blocks are

also presented in detail in this chapter.

4.1 VCO Block

The VCO is a ring oscillator and consists of three delay stages connected in a

loop. In the preliminary design the delay stage was implemented in the form of

a source degenerated common-source amplifier with a resistive load RP and source

degeneration resistance RN as shown in the figure 4-3. The complete VCO diagram

Figure 4.3: Delay Stage with RP and RN

is shown in Figure 4-4.

32
Figure 4.4: Three Stage Ring Oscillator

33
 However, the frequency of oscillation varies with change in supply voltage. This

happens due to the change in current through the delay stage with supply variation.

Therefore, an additional input is required to tune the circuit to negate the effect of

supply voltage variation.

To this effect, we vary the resistance RP to make sure that the current flowing

through the delay stage in independent of supply fluctuation. Thus, the load resis-

tance RN is modeled as a PMOS with a voltage control VBIAS applied at its gate, as

shown in Figure 4-5. The proposed voltage-controlled oscillator diagram is presented

Figure 4.5: Delay stage with PMOS load

in Figure 4-6.

34
Figure 4.6: Three Stage Ring Oscillator

35
 Since the current through a MOSFET in saturation is:

1 W
ID = µCox (VGS − Vth )2 (4.2)
2 L

Thus, if VBIAS biases the gate voltage of the PMOS such that VGS remains con-

stant, the current through the delay stage would remain constant, making the oscil-

lation frequency, FOU T supply insensitive. The bias voltage follows a linear pattern

with supply variation as shown in Section 4.2. This helps formulate the effect of

supply fluctuation on the VCO output frequency in the form of the linear equation

(4.1).

The following figure and table show the effect of variation in frequency when the

supply is varied from 1.1 volts to 1.3 volts in linear steps of 0.02 volts, while VBIAS

is fixed at 0 volts. To negate this effect the bias generation and digital calibration

Figure 4.7: Effect of variation in supply voltage @ fixed VBIAS - Frequency spectrum
(DFT using hamming window) @ VBIAS = 0 V,

36
 VSU P (V) 1.10 1.12 1.14 1.16 1.18 1.20
Freq (MHz) 373.33 381.4 390.1 400 411.5 423.33

VSU P (V) 1.20 1.22 1.24 1.26 1.28 1.30

Freq (MHz) 423.33 435 446.7 460.3 476.7 491.6

Table 4.1: Variation of frequency with change in supply @ VBIAS = 0 volts

blocks are introduced. These blocks help vary the VBIAS with variation in supply

and hence maintain fixed oscillation frequency, thus enabling the design of the novel

power supply insensitive VCO. These blocks are discussed in detail in the following

sections of this Chapter.

4.2 Filtering effect

In this voltage-controlled oscillator design, each delay stage if followed by a capac-

itor and resistor as shown in Figure 4-8. The capacitor and resistor are introduced

Figure 4.8: Delay stage followed by resistor and capacitor (Filter effect)

37
to remove the DC component of the output signal of the delay stage, and DC bias

it to 0.6 volts before it is fed into the input of the following stage. The values of

capacitor and resistor are calculated with careful analysis. The two effects that need

to be taken into consideration while deciding these values are explained below.

4.2.1 Path from the output of the first stage to the input of
the second stage:

When following this path, the capacitor CB and resistor RB act like a high-pass

Filter (HPF), as shown below in Figure 4-9. The transfer function of this filter is

Figure 4.9: High-pass filter effect

given in equation (4.3).

VOU T sCB RB
= (4.3)
VIN 1 + sRB (CB + Cgmos )

The VOU T versus VIN characteristics with varying resistor and capacitor values are

plotted as shown in Figure 4-10. From the plot, it can be seen that if R1 and C1

are too low then the output signal gets completely attenuated, and the VCO stops

oscillating.

38
Figure 4.10: HPF - Effect of varying RB and CB

39
4.2.2 Path from the supply to the input of the delay stage:

When following this path, the resistor RB and capacitor CB act like a low-pass

filter (LPF) as shown in Figure 4-11. The transfer function of this filter is given in

Figure 4.11: Low-pass filter effect

equation (4.4). A step input was applied at the supply and the transient response at

the output was plotted, for varying resistor and capacitor values, as shown in Figure

4-12. From the plot it can be seen that, if the resistance and capacitance are too

high it takes longer for the DC of the output voltage to settle at 0.6 volts, since the

settling time is directly proportional to RB and CB .

VOU T 1
= (4.4)
VSU P 1 + sRB (CB + Cgmos )

Thus taking the two effects into consideration the resistor value RB was fixed at 10

kilo ohms. Similarly, the capacitor value CB was fixed at 20 femtofarads.

40
Figure 4.12: LPF - Effect of varying RB and CB

41
4.3 Bias Parameters

The complete schematic of the VCO core, with VBIAS as voltage input and FOU T

as the output oscillation frequency is presented in Figure 4-6. The bias values of the

transistors and resistors and capacitors are enlisted in Table 4-2.

RB 10KΩ
RN 100Ω
CB 100f F
CN 20f F
CP 20f F
WM 1,P 2,P 3 10µm
WM 4,P 5,P 6 10µm
WP 1,P 2,P 3 5µm
WP 4,P 5,P 6 5µm
LM 1,P 2,P 3 130ηm
LM 4,P 5,P 6 130ηm
LP 1,P 2,P 3 130ηm
LP 4,P 5,P 6 130ηm

Table 4.2: Bias Parameters

4.4 Bias Generation Block

The bias generation block is used to generate the voltage VBIAS that controls the

gate of the PMOS, and thus varies the load resistance. The resistance is varied such

that the current through the delay stage remains fixed, even when the supply voltage

fluctuates. The bias voltage VBIAS was varied, along with the supply voltage and the

simulated results are enlisted in Table 4-3, as shown below. These values were then

plotted with VBIAS as y axis, and VSU P as x-axis, as shown in Figure 4-13.

42
 VSU P 1.1 V 1.15 V 1.2 V 1.25 V 1.3 V VCT RL mV freq (MHz)
0 26.5 60 86.5 116 0 373.33
50 80 110 140 170 50 336.6
100 130 160 190 220 100 310
VBIAS (mV) 150 180 210 240 270 150 286.66
200 230 260 290 320 200 266.67
250 280 310 340 370 250 250
310 330 360 390 420 310 236.66

Table 4.3: Bias voltage variation to maintain constant oscillation frequency

Figure 4.13: Bias voltage VBIAS variation with VSU P

43
 VCT RL , the voltage from the output of the loop filter, enables the VCO to change

the frequency of oscillation, i.e, it enables the VCO to jump from one frequency curve

to the other as shown in the plot. As VCT RL increases, the frequency of oscillation of

the VCO decreases. The supply voltage VSU P was varied from 1.1 volts to 1.2 volts

in linear steps of 0.02 volts.

It can be seen from the above plot that, the curves are linear. This means that the

slope KF V SU P is constant, i.e, for an increment δVSU P there is a linearly proportional

increase in δVBIAS . Thus, a linear relationship can be derived between VBIAS , VDD −

VREF ; the difference in supply voltage from the reference voltage VREF , KF V SU P and

VCT RL .

4.4.1 Derivation

A common form of linear equation in the two variables a and y is

y = mx + b

where m and b are designate constants. The constant m determines the slope or

gradient of the line, and the constant term b determines the point at which the line

crosses the y-axis.

The above linear curves, can be defined by a similar linear equation where,

b = VCT RL , (4.5)

m = KF V SU P , (4.6)

y = VBIAS , (4.7)

VBIAS = (VDD − VREF )KF V SU P + VCT RL (4.8)

44
From the above plotted curves, the slope KF V SU P is calculated to be 0.6 V/V. The

reference voltage VREF was fixed at 1.1 volts. Hence, the equation defining the above

plot, can be written as

VBIAS = (VDD − 1.1)0.6 + VCT RL (4.9)

4.4.2 Implementation

The above equation was implemented using an opamp with closed loop gain

0.6V /V and an open loop gain of 10,000. The circuit is presented in Figure 4-14.

where,

Figure 4.14: (VDD − 1.1)0.6 + VCT RL Implementation

R1 = R5 = 600Ω,

R2 = R3 = 1KΩ,

R4 = R6 = 1KΩ,

45
4.5 Digital Calibration Block

The digital calibration block as shown in Figure 4-15 is used to find the value of

KF V SU P . After the VCO is powered up, the input VREF is swept from 0.9 volts to

Figure 4.15: Digital calibration block

1.1 volts in linear steps of 0.1 volts, the supply voltage VSU P is kept constant at 1.1

volts, and the control voltage input VCT RL is kept fixed at 0 volts. Firstly, VREF is

fixed at 1.1 volts, thus generating a bias voltage VBIAS equal to 0 volts. Then the

oscillation frequency of the voltage controlled oscillator is measured.

Next, VREF is changed to 1.0 volts and the same process is repeated. The frequency

of oscillation is measured. However, since this frequency from the one obtained when

VREF was 1.1 volts, the resistor in the opamp is varied till the time the oscillation

frequencies of the VCO in the two different steps match.

The same steps are repeated for VREF equal to 0.9 volts. Finally, the KF V SU P

is measured by divided the value of the varied resistor by 1000, as explained in the

following eqautions.

The above discussed steps are presented in the form of a digital calibration algo-

rithm as shown below in Figure 4-16.

46
Figure 4.16: Digital Calibration Algorithm
47
 The opamp with resistor R1, R2, R3, R4, R5 and R6 is shown below, in Figure

4-17. The transfer function can be written as:

Figure 4.17: Resistor tunability

VCT RL VSU P 1 1 1 1 VREF

VOU T = ( + )( + + )( 1 1 1 − (4.10)
R6 R4 R1 R5 R3 R6 + R4 + R2
) R3

if, R1 = R6 = R (4.11)

and, R2 = R3 = R4 = R5 = R0 (4.12)
R
VOU T = VCT RL + (VSU P − VREF ) (4.13)
R0
R
T hus, KF V SU P = (4.14)
R0
If, R0 = 1000Ω (4.15)
R
KF V SU P = (4.16)
1000

Thus, by varying R to maintain the same frequency of oscillation with supply

variation, we can calculate the required slope KF V SU P .

48
4.6 Simulation Results

The proposed voltage-controlled oscillator discussed in this chapter was imple-

mented in cadence 130-µ m CMOS technology. The bias control voltage was varied

along with supply variation, according to the proposed bias voltage generation equa-

tion 4.1. The supply voltage was varied from 1.1 volts to 1.3 volts in steps of 0.05

volts, and the voltage-controlled oscillator output was plotted.

4.6.1 Simulation @ VCT RL = 50 mV

Figure 4.18: VCO - voltage output @ VCT RL = 50mV

49
 The frequency of each of the above waveforms in the plot was calculated, and is

presented below in Table 4.4.

VSU P (V) VBIAS (mV) Freq (MHz)

1.1 50 337.325
1.15 80 337.031
1.2 110 337.470
1.25 140 337.109
1.3 170 337.710

Table 4.4: Variation of frequency with change in supply @ VCT RL = 50 mV

Figure 4.19: Frequency spectrum (DFT using hamming window) @ VCT RL = 50mV

Inference: The variation in frequency with supply voltage is almost

negligible.

50
4.6.2 Simulation @ VCT RL = 200 mV

Similarly, at VCT RL = 200 mV, the frequency of oscillation at different supply

voltages is calculated and is presented in the table below.

VSU P (V) VBIAS (mV) Freq (MHz)

1.1 200 265.928
1.15 230 265.767
1.2 260 265.778
1.25 290 265.989
1.3 320 266.102

Table 4.5: Variation of frequency with change in supply @ VCT RL = 200 mV

Figure 4.20: Frequency spectrum (DFT using hamming window) @ VCT RL = 50mV

Inference: The variation in frequency with supply voltage is almost

negligible.

51
4.7 Conclusion

Since the change in frequency of oscillation with variation in supply voltage is

almost negligible, we conclude that the voltage-controlled oscillator presented in this

chapter is power supply insensitive.

52
 CHAPTER 5

FUTURE WORK AND CONCLUSION

This chapter summarizes the design and results of the voltage-controlled oscillator.

It then presents some future extensions using the ideas presented in this thesis. In

the end, the major contributions of the presented work are highlighted.

5.1 Design Summary

This thesis presented a novel architecture for the design of a ring voltage-controlled

oscillator based on a series of coupled differential delay stages that can provide better

supply noise immunity. VCOs are very critical components in a PLL, and are a

major contributor of output jitter. They experience large supply noise because of

digital switching activities , impact the clock’s timing jitter and thus limit system

performance.

In particular, for ring VCOs, supply noise is a major design concern as the oscil-

lation frequency of a ring VCO is highly dependent on the supply voltage. In case of

LC-VCOs the oscillation frequency is a function of the discrete inductor and capac-

itor values and thus have high supply noise immunity. However, inductors are large

consumers of silicon area, and are thus less suitable for very large scale integration.

53
 The proposed work generates a bias voltage VBIAS to control the gate of the

PMOS load of the differential delay stage. In order to negate the effect of the supply

fluctuation on the VCO, VBIAS is varied accordingly, to ensure a supply independent

bias current through the delay stage. The variation in VBIAS with supply voltage

followed a linear pattern and hence this behavior was characterized in the form of a

linear equation. The bias voltage, VBIAS , was generated in the bias generation block.

The control voltage, VCT RL , which is the input to the VCO, was used to change the

frequency of operation of the VCO. One of the key elements to generate the bias

voltage was to find the slope of the linear curves, i.e,KF V SU P . For the simulated

design the slope was found out to be 0.06 V/V. The bias voltage was generated using

an operational amplifier and a couple of resistors with closed loop gain of KF V SU P .

However, due to temperature and process variations, the frequency curves may

shift or change. This may lead to a change in slope KF V SU P . In order to find the

slope KF V SU P , of the linear curves, a digital calibration algorithm was presented.

This algorithm calculates the new slope, anytime there is a change in the frequency

curves due to temperature, supply or process variations. To incorporate the changes

in the slope, VBIAS was generated using an operational amplifier, some fixed resistors

and some tunable resistors. The slope KF V SU P , is modeled as a ratio of two resistors.

Hence, any change in KF V SU P , is reflected by varying the value of the resistor used

in the bias generation block.

Some ideas to vary the resistor value are presented in the next section. The

voltage-controlled ring oscillator presented in this design operates from 236.6 MHz to

373.3 MHz. Some ideas to increase the frequency of operation are also presented in

the next section.

54
5.2 Future Extensions and Major Contributions

5.2.1 Resistor tun-ability

To incorporate changes in KF V SU P with temperature and process variations can

be achieved by using a digitally controlled array of resistors, as shown below in Figure

5-1. A control word, controlling the switches, can then be generated in the digital

calibration algorithm. Lower sensitivity to the variations can be attained by using a

higher number of resistors and a wider control word.

R1X
Figure 5.1: Resistor tun-ability (KF V SU P = R0
)

5.2.2 Increasing the frequency of operation

The major contributor to the delay of the VCO To increase the frequency of

operation of the VCO, is the RB -CB network. It acts like a high pass filter and

55
introduces phase delay of approximately 90 degrees. Since we have three stages of

this network it adds a delay of 270 degrees. However, if we add another stage of RB -

CB network, the phase shift will wrap around and produce only 90 degrees (360-270

degrees) of phase delay, as explained below in Figure 5-2 . This may help the VCO

oscillate at a higher frequency.

Figure 5.2: Ring oscillator - adding another stage of RB-CB network

The oscillation frequency may also be increased by increasing the bandwidth of

the individual delay stage. This will help reduce the delay of each stage at the

operating frequency of oscillation. If the frequency of operation is much lower than

the bandwidth, only the switching delay of the inverter will contribute to the delay,

and the delay contributed by RC of the inverter will be neglible.

5.2.3 Sub-banding

The sub-banding technique as discussed in chapter 3, can also be implemented in

this design to reduce the oscillator gain of the proposed voltage-controlled oscillator.

This further helps reduce the output jitter and improve the supply noise rejection. An

additional control word can be generated in the proposed digital calibration algorithm,

56
to facilitate sub-banding. Thus digital calibration to generate VBIAS and the sub-

banding technique, can together help design a highly robust and supply insensitive

VCO.

In summary, this thesis makes a valuable contribution by proposing a simple

supply insensitive architecture for the ring VCO. It helps model the effect of supply

variation , in an uncomplicated linear expression , and generates a bias voltage to

negate this effect. It also discusses the concept of digital calibration to help counter

process and temperature variations.

57
 APPENDIX A

COMPLETE CIRCUIT SCHEMATICS

58
Figure A.1: Manetais VCO with symmetric loads and replica-feedback

59
Figure A.2: Voltage-controlled oscillator - Wilson and Moon

60
Figure A.3: Voltage-current converter

61
Figure A.4: Current multiplier - Wilson and Moon

62
Figure A.5: ICO - delay stage1

63
Figure A.6: ICO - delay stage2

64
Figure A.7: Proposed voltage-controlled oscillator

65
 BIBLIOGRAPHY

[1] J. G. Maneatis and M. A. Horowitz, “Precise Delay Generation Using Coupled

Oscillators,” IEEE Journal of Solid-State Circuits, Vol. 28 , No. 12, December
1993.

[2] J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, and M. Shankaradas, “Self-

Biased High-Bandwidth Low-Jitter 1-to-4096 Multilpier Clock Generator PLL,”
IEEE Journal of Solid-State Circuits, Vol. 38 , No. 11, November 2003.

[3] J. Carnes, I. Vytyaz, P. K. Hanumolu, K. Mayaram, and U.-K. Moon, “Design

and Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells,”
IEEE International Conference on Electronics, Circuits and Systems, 2007.

[4] W. B. Wilson, U.-K. Moon, K. R. Lakshmikumar, and L. Dai, “A CMOS

Self-Calibrating Frequency Synthesizer,” IEEE Journal of Solid-state Circuits,
Vol.35, No.10, October 2000.

[5] A. Hajimiri, S. Limotyrakis, and T. H. Lee, “Jitter and Phase Noise in Ring
Oscillators,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 6, June 1999.

[6] B. Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE Journal of

Solid-State Circuits, Vol. 31 , No. 3, March 1996.

[7] B. Razavi, Design of analog CMOS Integrated Circuits. 2001.

[8] A. Aktas and M. Ismail, CMOS PLLs and VCOs for 4G Wireless. 2004.

[9] I.-C. Hwang and S.-M. Kang, “A self-regulating VCO with supply sensitivity of
¡0.15February 2002.

[10] M. Brownlee, P. Hanumolu, K. Mayaram, and U.-K. Moon, “A 0.5 to 2.5GHz

PLL with Fully Differential Supply-Regulated Tuning,” IEEE International
Solid-state Circuits Conference, February 2006.

[11] T. Wu, K. Mayaram, and U.-K. Moon, “An On-chip Calibration Technique for
Reducing Supply Voltage Sensitivity in Ring Oscillators,” IEEE Journal of Solid-
State Circuits, Vol. 42 , No. 4, April 2007.

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[12] P.-H. Hsieh, J. Maxey, and C.-K. Yang, “Minimizing the Supply Sensitivity
of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control
Voltages,” IEEE Journal of Solid-State Circuits, Vol. 44 , No. 9, September
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67