Clock Strategy

• Clocked Systems
• Latch and Flip-flops
• System timing
• Clock skew
• High speed latch
design
• Phase locked loop
• Dynamic logic
• Multiple phase clock
• Clock distribution
VLSI System Design NCKUEE-KJLEE
 Clocked Systems

Most VLSI systems are a combination of

− pipelines and
− finite state machines(FSM)

Pipelined systems
Input D Q D Q ... D Q output
Logic Logic

CLK CLK

Finite state machine Comb.

Logic

QD
CLK or CLKS
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 Single-phase clock timing
waveforms
Cycle Time (Tc)
Tc: clock cycle time (period) D Q
Clock

CLK
Setup Time (Ts)
Ts: setup time -- the time before
the clock edge during which
data the data input (D) has to be
stable
Hold Time (Th) Th: hold time -- the time after the
clock edge during which the
data input (D) has to remain
stable
Q Tq: clock-to-Q delay -- The delay
Clock-to-Q Delay (Tq) from the clock edge to the Q
output

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 Latches and flip-flops
D 0
Q clk
1 D
s
Q
CLK

(a) Negative Latch (Level sensitive)

clk
0 D
Q
D Q
1
s
CLK

(b) Positive Latch (Level sensitive)

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 Latches and flip-flops
clk
D
0 D
0
1 Q QM
QM
s 1
CLK s Q
CLK
master slave
(c) Positive edge-triggered register(single-phase clock)

clk=0

clk=1
master slave
(d) Pass transistor/inverter implementation

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 System timing
(A) Positive-edge triggered

Tc
Tq Combinational Ts
Register Register
Logic
clock A B
Td
Tq Td Ts

Tc >Tq + Td + Ts

(B) Alternatively, one may use latches as storage elements to save area.

Tq Combinational Ts
Latch Latch
Logic
clock A B
Td

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 System timing (con’t)

(C)
A B

Tq Combinational Ts Combinational
Latch Latch Latch
Logic Logic
clock A B c
Tda Tdb

Tc1 Tco
Tc1>Tqa+Tda+Tsb Tco>Tqb+Tdb+Tsc
If Tc=Tc1+Tco and Tc1=Tco, Tqa=Tqb,
Tsb=Tsc
Tqa Tda Tsb Tqb Tdb Tsc
=> The limit is Tc = Tda + Tdb + 2(Tq+Ts)

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 Racing due to clock skew

Td 2 1. If Tc2 > Tc1 + tq1 + td2

REG REG
1
1-bit Logic
0
1-bit − M2 may sample a wrong
d q d q
data (current data)
M2
− Transparency problem
M1

clk Tc1 Tc2

delay delay

2. If Tc1 + tq1 + td2 >Tc (cycle time)

clk − M2 cannot sample the
previous data
Tc1

Td 2 Old Data New Data

Tc2

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 Single-phase clock using D-FF
C1 L1 C2 L2
1) C2=C1

C2 C1 C1
C2
C1 = C2 or C2 = C1 Wrong data Correct
in L2 data
C2 C1 C1 C2
2) C1=C2

C1
C2
Comb
L1 L2
Wrong
only if
Comb.
CLK Logic
FSM --> "feedback" or
Pipeline --> "feedthrough"

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 To eliminate (reduce) time skew
(clock skew)
1.Balanced delay clock driver 2.Use buffers where necessary
clk clk
clk-in clk
Large Load

clk clk
clk

clk-in clk
3.Very careful simulation(HSPICE)
4.Very small rise and fall time on
clk the clock-- large buffer for large
load
5.Multiple clocking strategies
usually slightly smaller than the inverter

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 Some Implementations of clocked
latches
• Use a weak trickle inverter D
-ck Î eliminate a metal
clk clk connection
D Q Q Î smaller area
clk clk
ck
small inverter
(low-gain, smaller
W or large L)
or
• Transmission-gate latch
Q D

D c lk
c lk

c lk c lk
buffered
input
compared with a tri-state buffer
VLSI System Design NCKUEE-KJLEE
 Typical symbolic layouts for
latches
(a) (b) (c)
V V V
DD DD DD

D Q D Q D Q

V clk -clk clk -clk

clk -clk SS V V
SS SS

-clk -clk
D

clk clk
Q clk clk clk clk
clk clk
D Q D Q

-clk -clk

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 logic gate based latches
(a) Level sensitive
clk
D
Q

-Q Q

D
clk
(b) Edge triggered
D
Q

-Q

clk

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 Asynchronously settable and
resettable F/Fs
-clk -reset
(a)
Q

clk clk -clk clk

-clk clk -clk

-clk -reset
(b)
Q

clk clk -clk clk

-clk clk
-set -clk
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 Dynamic single clock latches

• The feedback inverter and transmission gate are eliminated.

• The latched value is stored on the capacitance of the input to
the inverter (mainly gate capacitance)
• Clock-to-Q (Tq) is very small need to be very careful to
prevent transparency problem.
• Internal inversion of the clock is often necessary.
• Dynamic nodes should be always refreshed or clamped to a
known state when in stand-by or low-power mode.
clk clk

D -Q D

-clk -clk
(a) (b)

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 Dynamic single clock latches (con’t)

clk -clk
clk clk -clk
D
D Q D Q
-clk -clk clk
-clk clk

(c)Tristate inverter (d)master-slave F/F (e)

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 Refreshing for Dynamic latches

• Dynamic storage nodes are • Even if the storage of the

usually a gate capacitance. correct state is unimportant,
• Assume the leakage the leakage may cause the
current= 1 nA storage node to assume a level
that causes the inverter to
and the storage draw significant current.
capacitance = 0.02PF
large current
ΔV 5
C× = 0.02 × 10 −12 × −9 = 100μs 5V -> 2.5V
Δi 10
must refresh every 100μs

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 Phase locked loop (PLL) clock
techniques
(1) To synchronize internal and external clocks.
(2) To synchronize data transfers between chips.
(3) To operate the internal clock at a higher rate.
(1) clock clock

clock chip clock

pad clock PLL pad clock
dclk dclk
clock clock
route data out route data out

dclk dclk

output pad output pad

dclk+dpad dclk+dpad

(a) Without PLL (a) With PLL

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 PLL techniques

(2) high speed (3) clock

bus tristate bus
chip clock
PLL pad clock

/4 clock d
clk
route
clock clock
PLL PLL
dclk

system clock output pad

dclk+dpad
To ensure the output of chips
are synchronized with each Clock rate at d clk
other.
4
= clock
⇒ d clk = 4 × clock

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 Block diagram of a PLL circuit
÷n
Ffb U
Phase Charge
Filter VCO
Detector D pump
n*Fin
reference
clock(Fin)

Phase detector: detect the difference between Ffb and Fin.

If Ffb > Fin =>D pulse
If Ffb > Fin =>U pulse
Charge pump: charge or Discharge a capacitor according to D and U.
Filter: filter the capacitor output (smoother).
VCO: Change the oscillation frequency depending on the control voltage.
(Voltage Control Oscillator)

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 Phase Detector
16/8 16/8 16/8
F1 UP
F1 16/8
16/8 16/8
F2

16/8
16/8
If F1 falls before F2
=> UP=1
16/8 16/8 16/8
F2 16/8 DN
If F2 falls before F1
16/8 16/8
=> DN=1

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 Charge Pump

P-REF P1 SW0
40/2
P1 P-REF 40/2
N1
2/5 P-SWITCHSW0
CHGUP
N2 SW1
2/5 CAP
40/2 8/1
N4 CHGDN P-SWITCH SW0 IN
N3 10/2
N-REF SW1 16/1 10/2
10/2
N5
N-REF
SW1
40/2

CAP charges when CHGUP=1

Bias circuit
discharge when CHGDN=1

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 Filter
VCO

in
out 32/1 32/1 32/1
2/6 4/6
32/1 32/1 32/1
13stages
16xFsc
2400/6 2400/6 control 16/1 16/1
16/1
voltage

16/1 16/1 16/1

in out
VCO

VLSI System Design NCKUEE-KJLEE

 Metastability Problem
clock
4ns data
D Q Q
delay
2ns
clk Q
No
clk Problem
-Q
delay=2.2ns
If the setup or hold time is not
satisfied, I.e., D changes at the Q
metastable
activation edge of the clock, then point
Long delay
the output Q will have a state -Q
delay=2.3ns
depending on the timing relation
between D and CLK Q Output
metastable
point error
-Q
delay=2.4ns

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 Metastable state in a pair of
inverters
Inv1
A B To Solve the metastability
problem:
− Setup time is shorter than
the clock-to-Q delays in a
synchronization system.
− For asynchronous input :
Inv2
VB need a special circuit
Inv1 called synchronizer.

metastable
point

Inv2

VA
0V 2.5V 5V

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 Single-phase N-P CMOS dynamic
logic
− Combine N-P section of domino logic with clocked CMOS
(C2MOS) latch as the output stage.
clk -clk
to n-logic to p-logic
blocks blocks -clk
to -clk
to p-logic to n-logic blocks clk section
blocks

clk -clk
p-logic C2MOS
n-logic block latch
-clk
to -clk section block
clk n-p CMOS -clk logic stage
(b)
Inputs from
-clk stages
-clk clk -clk clk -clk
p-logic C2MOS latch logic logic logic 0 1
n-logic block 1 0
evaluation Precharge evaluation
block From n or buffered p-logic Precharge evaluation Precharge
n-p CMOS clk logic stage
(a) (c)

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 Design rules for N-P CMOS
dynamic logic
Two problems to be solved R1: During precharge, logic-
1.Each section must be blocks must be switched
internally race free. off.
2.When different section are
cascaded to from pipelined R2: During evaluation,
system, clock skew should internal inputs can make
not cause a problem. only one transition.
clk
clk

When a static logic is used in

a N-P CMOS dynamic logic, it
should be placed after
dynamic logic (I.e., one
should keep the static logic
up to the C2MOS latch.
Reason: static logic after
creates a glitch at its output.

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 R3: There exists in each logic block Reason:
at least one dynamic gate
that is separated from 0 0
1 1
the previous C2MOS or
2
output stage by an even number C MOS
of inventions.
or clk clk C2MOS
clk clk

R4: The total number of inversions or Domino The same evaluation

between two consecutive phase in a section
C2MOS stage is even.
-clk clk

clk -clk

at least one C2MOS latch

even number of dynamic stage (clk section)
inversions
C2MOS latch
output stage OR
(-clk section)
even umber of inversions

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 Two phase clocking

phi1
phi1 phi1 logic skewed
phi2
phi phi2 logic clokcs
2
overlap
-phi1 -phi2 (c) small dealy
D Q
phi phi2 DFF1
1
(a)

slow rise
phi1=1 time
phi2=0
overlap
C1 C2 phi1=1
phi =0 phi2=0
1
C1 C2
phi =1
2 (d)
C C2
(b) 1

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 Two phase clock generation

1. Globally distribute two clocks Two-phase clock generator

with or without their
complements. clk φ1
3. A single global clock and locally
generated two-phase clocks
φ2

Delay for non-overlap

period

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 Two phase registers

high level =V -V
-phi1 DD tn
-phi
2
D Q
D Q
DEF1A
phi1 phi
(a) 2
DEF1
phi1 phi2 p leakers
-phi -phi
1 2
-phi1
-phi
D 2 n Q D Q
1 n D Q
2 (b)
phi1 phi2
phi phi2 phi DEF1B
1 1 phi
2
D Q
clk
DEF2 DEF3
Both of these dynamic registers
(c)
have to drive a local storage gate.

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 Two phase logic
1. Static logic with two phase 2. Dynamic logic
registers -phi1 -phi2
-phi1 -phi2
Logic Logic from phi2 phi1 phi1
stage n-logic n-logic to phi
phi1 phi2 1
φ1 φ2 phi2 stage
phi1

phi1 evaluate phi1 logic

precharge phi1 logic precharge phi1 logic

latch phi2 data latch phi data
2

evaluate phi2 evaluate phi2

phi2
logic logic
precharge phi2 logic
latch phi1 data

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 Four-Phase clock
φ1→φ1 Four-Phase logic clocking method
φ1→φ2
nonoverlapping
φ2→φ3
φ2→φ4 Slave Master
Logic Logic
Latch Latch
clk 1 clk 3 clk 1
clk 2 n 1 clk Q
4 clk 2 clk1 clk2 clk3 clk4
D
clk 3
clk 1 clk 3 clk 4
(a) in v1 in v2

clk 1 clk 3 clk 1

clk 12 Q clk 2
clk 34
D
clk 3
clk 1 clk 3 clk 4
(b )
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 Clock distribution
n-bit datapath
1. A single large buffer n-bit datapath
2. A distributed-clock-tree
n-bit datapath
approach
n-bit datapath

n-bit datapath

n-bit datapath
clock
n-bit datapath
delays have to match
between stages n-bit datapath

n-bit datapath

n-bit datapath

n-bit datapath

n-bit datapath

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 Trends in clock strategy

• For first-time designer, use static logic, single-phase

static registers.
• For standard cell and gate-array design, single-phase
may be the only choice.
• Two phase clocking make timing design of RAMs, ROMs
and PLAs easier.
• In modern process and circuits, cycle time is the main
concern => single phased
Processes are extremely dense => single phase

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