Intel® Core™ i7-900 Desktop Processor Extreme Edition Series and Intel® Core™ i7-900 Desktop Processor Series Datasheet, Volume 1 February 2010 Document # 320834-004‘AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING See inti ore nieie hiemoear mae ek Rake ee Ros ae in i gr oe eit yo ae nee 2 gee ec on ott SSeS uSRAa aus gee norman Sh Tele seein ec anne ta tn tre 7.0 te er yen Tounsend tae ms it seater ee se se FE eee ee eee areas Hil ices a tatters ae a aoe ie ce ee Fae rea pec ecient tag ter eee apes alate oar aoa eed ep ne oe Irerineui iene care rere seco eer empow asteag earring See ee ee er Ron re serene tame # a pees aa ae Fak emi nae a due tesco tn wn ge et on en rede en ara ns igh or ease ae ie era a i mm Sint atau at Sentence oS ln Serene erie evince esrtacouctaoe “es wane eyes cept pe mi tC geet er ec rama cee Bs ear nec fds Stat iar ey ed pein Sn tne ae ane year rma men cg sos Spans aS crea ap Se Bt ee to nn Susp ey Sansa hi en ye peta a etn. fab erie ely finn ct ee ee sao abe ee a ea re RcaaLe Mis tn tem tBoonito eerie tase aeteer oe Cpe yr sca oon pet ee ay a ot oe Sastre tet taping oa tcmnnt peas nonotseopene “coroner cna sep ober Son note sons 2 DatasetContents 1 Introduction. 1.1 Terminology 1.2 _ References 2 Electrical Specifications. 2.1 Intel® QPI Differential Signaling 212 Power and Ground Lands. 2:3 Decoupling Guidelines. 1 2.3.1 VCC, VITA, VITO, VDDQ Decoupling 24 Processor Clocking (BCLK” DP, BCLK_DN) 2.4.1 PLL Power Suppl 2.5 Voltage Identification (VID) 2.6 Reserved or Unused Signals.. 2.7 Signal Groups 23 29 Test Access Port (TAP) Connection... Platform Environmental Control Interface ( 29.4 DC Characteristics ..rnnenn 2.9.2 Input Device Hysteresis 2.10 Absolute Maximum and Minimum Ratings 2111 Processor DC Specifications 2.11.1 DC Voltage and Current Specification 2.11.2 VCC Overshoot Specification... 2.11.3 Die Voltage Validation... 3. Package Mechanical Specifications .. 3.1 Package Mechanical Drawing 3.2. Processor Component Keep-Oilt Zones. 3.3 Package Loading Specifications 3.4 Package Handling Guidelines. 35 _ Package Insertion Specifications. 3.6 Processor Mass Specification 3.7 Processor Materials. 3.8 Processor Markings. 3.9 Processor Land Coordinates 4 Land Listing Signal Descriptions: Thermal Specifications sone 6.1 Package Thermal Specifications. 6.1.1 Thermal Specifications 6.1.2 Thermal Metrology 6.2 Processor Thermal Features. 6.2.1 Processor Temperature . 6.2.2 Adaptive Thermal Monitor. 6.2.3 THERMTRIPS Signal 6.3. Platform Environment Control interface (PEC) 6.3.1 Introduction 6.3.2 _PECI Specifications . 6.4 Storage Conditions Specifications ~ Datosheet 3aa 7 Features 7.4 Power-On Configuration (POC)... 7.2 Clock Control and Low Power States. 7.2.1 Thread and Core Power State Descriptions 72.2 _ Package Power State Descriptions. 7.3. Sleep states i 7.4 ACPI P-States (Intel® Turbo Boost Technology) .. 7.5 Enhanced Intel® SpeedStep® Technology wwe 8 Boxed Processor Specifications... 8.1 Introduction. 8.2 Mechanical Specifications 8.2.1 Boxed Processor Cooling Solution Dimensions... 8.2.2 Boxed Processor Fan Heatsink Weight ... 8.2.3 Boxed Processor Retention Mechanism and Heatsin 8.3. Electrical Requirements i sitet 8.3.1 Fan Heatsink Power Supply 2... 8.4 Thermal Specifications. 8.4.1 Boxed Processor Cooling Requirements... BA.2 Variable Speed FAM .rniennenes nse ich Clip Assembly 1. High-Level View of Processor Interaces....s-ne 1. Active ODT for a Differential Link Example... -2 Input Device Hysteresis. 3 VCC Static and Transient Tolerance Load Lines 4 VT Static and Transient Tolerance Load Line... 5 VCC Overshoot Example Waveform “1 Processor Package Assembly Sketch... Processor Package Drawing (Sheet 1 of 2)» Processor Package Drawing (Sheet 2 of 2) 4 Processor Top-side Markings 5 Processor Land Coordinates and Quadrants (Bottom View) 1 Processor Thermal Profile. : : 2 Thermal Test Vehicle (TTV) Case Temperature (TCASE) Measurement Location «75 3 Frequency and Voltage Ordering 1 Power States... 4 Mechanical Representation of the Boxed Processor 2 Space Requirements for the Boxed Processor (side view) . 3 Space Requirements for the Boxed Processor (top view) 4 5 6 7 8 9 Space Requirements for the Boxed Procassor (overall view) . Boxed Processor Fan Heatsink Power Cable Connector Description... Baseboard Power Header Placement Relative to Processor Socket... Boxed Processor Fan Heatsink Airspace Keepout Requirements (top view)... Boned Processor Fan Heatsink Arspace Keepout Requirements (ide vew).. Boxed Processor Fan Heatsink Set POINtS sstsennstnntnnstnvsens en 4 Dataset2-412 2-13 26 2-415 246 BA 32 a4 42 St et 6-2 63 6-4 66 yt 73 BL Datasheet References wn. Voltage Identification Definition ‘ Market Segment Selection Truth Table for MS_ID[2:0}... Signal Groups... nse Signals with ODT... PECI DC Electrical Limits .. . Processor Absolute Minimum end Maximum Ratings... Voltage and Current Specifications. VCC Static and Transient Tolerance... VI Voltage Identification (VID) Definition . TT Static and Transient Tolerance... DDR3 Signal Group DC Specifications. RESET# Signal DC Specifications.. ‘TAP Signal Group DC Specifications .. PWRGOOD Signal Group DC Specifications: Control Sideband Signal Group DC Specifications. VCC Overshoot Specifications. Processor Loading Specifications Package Handling Guidelines. Processor Materials. Land Listing by Land Name... Land Listing by Land Number Signal Definitions ..e.n Processor Thermal Specifications. Processor Thermal Profile. ‘Thermal Solution Performance above TCONTROL Supported PECI Command Functions and Codes. GetTempd() Error Codes Seca Storage Conditions Power On Configuration Signal Options.. ‘Coordination of Thread Power States at the Core Level Processor S-States zl Fan Heatsink Power and Signal Specifications. Fan Heatsink Power and Signal Specifications..Intel® Core™ i7-900 Desktop Processor Extreme Edition Series and Intel® Core™ i7-900 Desktop Processor Series Features + Available at 3.20 GHz, 3.06 GHz, 2.93 GHz, 2.80 GHz, and 2.66 GHz (Intel Core™ 17-900 ‘desktop desktop processor series) ‘+ Available at 3.33 GHz and 3.20 Ghz (Intel Core" 17-900 desktop processor Extreme Edition series) ‘+ Enhanced Intel Speedstep® Technology ‘+ Supports Intel® 64° Architecture ‘+ Supports Intel® Virtualization Technology ‘+ Intel® Turbo Boost Technology + Supports Execute Disable Bit capability + Binary compatible with applications running ion previous members of the Intel ‘microprocessor line Inte!® Wide Dynamic Execution Very deep out-of-order execution Enhanced branch prediction Optimized for 32-bit applications running on advanced 32-bit operating systems + Intel® smart Cache + 8 MB Level 3 cache + Intel® Advanced Digital Media Boost ‘+ Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance + New accelerators for improved string and text processing operations ‘= Power Management capabilities Datasheet + System Management mode + Multiple low-power states + B-may cache associativity provides improved ‘cache hit rate on load/store operations + System Memory Interface = Memory controller integrated in processor package — 3 channels — 2 DIMMs/channel supported (6 total) — 24GB maximum memory supported — Support unbuffered DIMMs only = Single Rank and Dual Rank DIMMS supported — DDR3 speeds of 80/1066 MHz supported — 512Mb, 1Gb, 2Gb, ‘Technologies/Densities supported + Intel® QuickPath Interconnect (PI) = Fast/narrow unidirectional links = Concurrent bi-directional traffic — Error detection using CRC = Error correction using Link level retry — Packet based protocol = Point to point cache coherent Interconnect ~ Intel® Interconnect Built In Self Test (Intel® 1B1ST) toolbox built-in ‘+ 1366-land PackageRevision History a aaa a SS aa a a — 1 RESRE Svo mes ete nae oe ee =a “Set | et Oo ta ay BD § outer1 (intel Introduction Figure 1-1, Note: Note: Note: The Intel® Core™ 17-900 desktop processor Extreme Edition series and Intel® Core™ 17-900 desktop processor series are intended for high performance high-end desktop, Uni-processor (UP) server, and workstation systems. Several architectural and microarchitectural enhancements have been added to this processor including four processor cores in the processor package and Increased shared cache. The Intel® Core™ 17-900 desktop processor Extreme Edition series and Intel® Core™ 17-900 desktop processor series are the first desktop multi-core processor to implement key new technologies: + Integrated memory controller + Point-to-point link interface based on Intel QPI Figure 1-1 shows the interfaces used with these new technologies. High-Level View of Processor Interfaces 1 | System Processor — Memory cue 5} (o0R3) Intof* QuickPatn onnect (Init QP) In this document the Intel® Core™ 17-900 desktop processor Extreme Edition series and Intel® Core™ 17-900 desktop processor series will be referred to as "the processor” ‘The Intel Core™ 17-900 desktop processor series refers to the Intel Core™ 17-900, ‘desktop processors 17-960, |7-950, 17-940, 17-930, and i7-920. ‘The Intel Core™ i7-900 desktop processor Extreme Edition series refers to the Intel Core™ 17-800 desktop processor Extreme Ecition 17-875 and 17-965. ‘The processor is optimized for performance with the power efficiencies of a low-power rmicroarchitecture. This document provides DC electrical specifications, differential signaling specifications, pinout and signal definitions, package mechanical specifications and thermal requirements, and additional features pertinent to the implementation and operation of the processor: For information on register descriptions, refer to the Intel® Core"™ i7= ‘900 Desktop Processor Extreme Eaition Series and Intel® Core™ i7-900 Desktop Processor Series Datasheet, Volume 2.aoe 10 The processor Is a multi-core processor built on the 45 nm process technology, that Uses up to 130 W thermal design power (TDP). The processor features an Intel QPI Point-to-point link capable of up to 6.4 GT/s, 8 MB Level 3 cache, and an integrated memory controller. ‘The processor supports all the existing Streaming SIMD Extensions 2 (SSE2), ‘Streaming SIMD Extensions 3 (SSE3) and Streaming SIMD Extensions 4 (SSE4). The processor supports several Advanced Technologies: Intel® 64 Technology (Intel® 64), Enhanced Intel SpeedStep® Technology, Intel® Virtualization Technology (Intel® VT), Intel® Turbo Boost Technology, and Intel® Hyper-Threading Technology. Terminology A" symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is lov, a reset has been requested. Conversely, when VITPWRGOOD is ‘high, the Vrr power rail Is stable. “Nand \ P’ after @ signal name refers to a differential pal ‘Commonly used terms are explained here for clarification: + Intel® Core™ 17-900 Desktop Processor Extreme Edition Series and Intel® Core™ 17-900 Desktop Processor Series — The entire product, Including processor substrate and integrated heat spreader (THS).. ‘+ 1366-land LGA package — The Intel Core™ 17-900 desktop processor Extreme Edition series and Intel Core™ 17-900 desktop processor series are available in 2 Flip-Chip Land Grid Array (FC-LGA) package, consisting of the processor mounted fon a land grid array substrate with an integrated heat spreader (IHS). ‘+ LGA1366 Socket — The processor (In the LGA 1366 package) mates with the system board through this surface mount, 1366-contact socket. ‘+ DDR3 — Double Data Rate 3 Synchronous Dynamic Random Access Memory (SDRAM) is the name of the new DDR memory standard that is being developed as the successor to DDR2 SRDRAM. + Intel® QuickPath Interconnect (Intel QPI)— Intel QPIis a cache-coherent, point-to-point link based electrical interconnect specification for Intel processors ‘and chipsets. + Integrated Memory Controller — A memory controller that Is Integrated Into the processor die. + Integrated Heat Spreader (IHS) — A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface. + Functional Operation — Refers to the normal operating conditions in which all processor specifications, including DC, AC, signal quality, mechanical, and thermal, are satisfied + Enhanced Intel Speedstep® Technology — Enhanced Intel SpeedStep Technology allows the operating system to reduce power consumption when performance is not needed. + Execute Disable Bit — Execute Disable allows memory to be marked as executable or non-executable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit Buffer overrun vulnerabilities end can thus help improve the overall Datasheetae Table 1-1. Datasheet ‘security ofthe system. See the Intel® Architecture Software Developer's Manual for more detailed information. Refer to ht:p://developer.intel.comy for future reference on up to date nomenclatures. + Intel® 64 Architecture — An enhancement to Intel's 14-32 architecture, allowing the processor to execute operating systems and applications written to take ‘advantage of Intel® 64. Further details on Intel® 64 architecture and programming ‘model can be found at http: //developerintel.com/technology/intel64/, + Intel® virtualization Technology (Intel® VT) — A set of hardware enhancements to Intel server and client platforms that can improve virtualization solutions. Intel® VT provides a foundation for widely-deployed virtualization Solutions and enables a more robust hardware assisted virtualization solution. More information can be found at: http://wnw.intel.com/technology/ virtualization? + Unit Interval (UI) — Signaling convention that is binary and unidirectional. In this binary signaling, one bit is sent for every edge of the forwarded clock, whether itis a rising edge or a falling edge. If a number of edges are collected at instances ty ta tyyeny then the UI at Instance "n” Is defined as: Ul get y= tana ‘= Jitter — Any timing variation of a transition edge or edges from the defined Unit Interval. Storage Conditions — Refers to a non-operational state. The processor may be Installed ina platform, in a tray, oF loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any 1/Os biased, or receive any clocks. ‘+ OEM — Original Equipment Manufacturer. References Material and concepts available in the following documents may be beneficial when reading this document. References Document Location [ ipget® Core™ 7-300 Geattp Processor Extreme Eton Saves and Intel® Nap downoadintal amy aar| Coser 500 Desttp Procturor Sores Speceation Uodsts procesorepecipa 320836 pet a on ee Tpta Core™ 17-900 Deskiop acess Biren Fain and Int Tip [donna ital conv desin? Core™ 7500 Desktop Proceso Series Datasheet Volume 2 processor datasht 320835 pa | ret core 7-500 Desktop Processor extreme Eton Series snd itel® Wp/dowrisad tel conv aesgn | ore e800 beektop Processor Sees nd {Gate cass Phermal and" ocessoycespnex/ S208 pa hrachanical Design Guide | intl x58 Express Chipset Datashect Rp Trt coy SeTPOFT Setashet/ 52088 pat {P-HRS, Tetl® Processor [donation and he CRUD Inirudion ‘HD wn ete com/Sesarproe ‘esorfoppnets/ 241618. [32 Intel® Archkectre Software Developers Nenu Volume 1: Basic Arcitectre + Volume 2A: inrucion Set Retererce, AM etme intel com/ produce fpr + Volume 28: instruction Set Reerence, WZ ceeston/menuas) + Volume A: System Programming Guide, Part 1 Volume 38: Systems Programming Gul, Part 2 nDatasheetElectrical Spe Electrical Specifications 2.1 Figure 2-1, 2.2 2.3 Datasheet Intel® QPI Differential Signaling The processor provides an Intel QPT port for high speed serial transfer between other Intel QPI-enabled components. The Intel QPI port consists of two unidirectional links (for transmit and receive). Intel QPI uses a differential signalling scheme where pairs of ‘opposite-polarity (D_P, D_N) signals are used. (On-die termination (ODT) is provided on the processor silicon and termination isto Vs. Intel chipsets also provide ODT; thus, eliminating the need to terminate the Intel QP links on the system board. Intel strongly recommends performing analog simulations of the Intel® QPI interface. Figure 2-1 illustrates the active ODT. Signal listings are included in Table 2-3 and ‘Table 2-4. See Chapter 5 for the pin signal definitions. All Intel QPI signals are in the differential signal group. Active ODT for a Differential Link Example ty ‘Signal Ry ‘signal 11 th ek Power and Ground Lands For clean on-chip processor core power distribution, the processor has 210 VCC pads ‘and 119 VSS pads associated with Vcc; 8 VITA pads and 5 VSS pads associated with \Vera3 28 VITD pads and 17 VSS pads associated with Vrrp, 28 VDDQ pads and 17 VSS pads associated with Vogq; and 3 VCCPLL pads. All VCCP, VITA, VTTD, VDDQ and VCCPLL lands must be connected to their respective processor poner planes, while all VSS lands must be connected to the system ground plane. The processor VCC lands ‘must be supplied with the voltage determined by the processor Voltage IDentification (VID) signals. Tabie 2-1 species the voltage level for the various VIDs. Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is ‘capable of generating large current swings between low and full power states. This may ‘cause voltages on power planes to sag below their minimum values if bulk decoupling is, ot adequate. Larger bulk storage (Cayxx), Such as electrolytic capacitors, supply ‘current during longer lasting changes in current demand; such as, coming out of an idle condition. Similarly, capacitors act as a storage well for current when entering an idle ‘condition from a running condition. Care must be taken in the baseboard design to a2.4 241 2.5 Electrical Specifications ‘ensure that the voltage provided to the processor remains within the specifications listed in Table 2-7. Failure to do so can result in timing violations or reduced lifetime of the processor. Vee: Vita Vip Voog Decoupling Voltage regulator solutions need to provide bulk capacitance and the baseboard designer must assure a low interconnect resistance from the regulator to the LGA1366 socket, Bulk decoupling must be provided on the baseboard to handle large current swings. The power delivery solution must insure the voltage and current specifications {are met (2s defined in Table 2-7). Processor Clocking (BCLK_DP, BCLK_DN) ‘The processor core, Intel QPI, and Integrated memory controller frequencies are ‘generated from BCLK_DP and BCLK_DN. Unlike previous processors based on front side bus architecture, there is no direct link between core frequency and Intel QPI link frequency (such as, no core frequency to Intel QPI mulplier). The processor maximum ‘core frequency, Intel QPI link frequency and integrated memory controller frequency, are set during manufacturing. Its possible to override the processor core frequency setting using software. This permits operation at lower core frequencies than the factory set maximum core frequency. ‘The processor's maximum non-turbo core frequency Is configured during power-on reset by using values stored internally during manufacturing, The stored value sets the highest core multiplier at which the particular processor can operate. If lower max non- turbo speeds are desired, the appropriate ratio can be configured using the CLOCK”FLEX_MAX MSR. The processor uses cifferential clocks (BCLK_DP, BCLK_DN). Clock multiplying within, the processor Is provided by the internal phase locked loop (PLL), which requires 2 ‘constant frequency 8CLK_DP, BCLK_DN input, with exceptions for spread spectrum Clocking. The processor core frequency Is determined by multiplying the ratio by 133 MH, PLL Power Supply ‘An on-die PLL filter solution is implemented on the processor. Refer to Table 2-7 for DC specifications. Voltage Identification (VID) ‘The voltage set by the VID signals is the reference voltage regulator output voltage to be delivered to the processor VCC pins. VID signals are CMOS push/pull drivers. Refer to Table 2-15 for the DC specifications for these signals. The VID codes will change due to temperature and/or current load changes in order to minimize the power of the part. voltage range Is provided in Table 2-7. The specifications have been set such that one voltage regulator can operate with all supported frequencies. Individual processor VID values may be set during manufacturing such that two devices at the same core frequency may have different default VID settings. This is reflected by the VID range values provided in Table 2-1. Datosneet“The processor uses eight voltage identification signals, VID[7:0], to support automatic ‘selection of voltages. Table 2-1 specifies the voltage level corresponding to the state of \VID{7:0}. 4" in this table refers to a high voltage level and a0" refers to 2 low voltage level. If the processor socket is empty (VID[7:0] = 11111111), or the voltage regulation circult cannot supply the voltage that is requested, the voltage regulator must disable itself ‘The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (Vcc). This will represent a DC shift in the loadline. It should be noted that a low-to-high or high-to-low voltage state change wil result in as many VIO transitions as necessary to reach the target core voltage. ‘Transitions above the maximum specified VID are not permitted. Table 2-8 includes VID_ step sizes and DC shift ranges. Minimum and maximum voltages must be maintained {as shown in Table 2-8. ‘The VR used must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 2-7 and Table 2-8 Table 2-1. Voltage Identification Definition (Sheet 1 of 3) vio] vio] vio] vio] vio] vio] vio | vio] y, vid] vio] vio |wio| vio] vio] vio] vio] y, 9] Ma] MEP | MAP| MIPL IP TMETMEPL voce] | M7) ¥4?| MSP) MEP] MSL YEP] MIO) YEP | Vc noe cporete of elepol oF] Core italy oli] 1 lamar] oper o. ao} oli} olism) “oa ei tay iyo] 1 aos) op oo) ao} ol] 1) 4 fissrs| 0 101 }a) a} 4 | 0 | 4.02s00) ope) o) a) o;1]o)1fisezs| 01 io} oo} 0] 0 40260 op oy; o) a1} oo} ofiseso| 0 1 io} ol] 01] 1 loses ope; o. a1} oli} ois] “017i oo] i} o| 1 loses] ope; o) sata] o}1fisszs| 0 1 i o}i} 0} 0 | 0 jossaso) ope. oa) ati [1 }afisiers| 01 iota] 0} 1] 0 | o.s000) of oo) 1,0} 0] 1) 0|1s0000) 0 1 i o}1] 1} o| 1 jossis| ope; oa) of1] ol} ofiss] “0 1 iota] i} 4| 4 joss] Dopeto Tato frye ls fies) “or 1 af} o| ©) 0 josis0) op oo. 1 ofa] 1) 1 frases) 0 1 11 fo} 0} 1 | 0 1030000: ope) oa 1} oo} 1 frases) 0 1 i 1 to] i} 0] 0 jo.serso Pepe a pepo tiers) Hoa a apo pa Tr foes) popes tape fi fo fies) oa i a fe fo Fr fossens} Datasheet 15Electrical Specitieations Voltage Identification Definition (Sheet 2 of 3) Table 2-1 ° usr ‘i300 ore fo tps ‘rs ‘i500 us ses 0.66375 ° ° ° ° ° ° ° 1063750 0.82500 ‘061250 ‘0.60625 ‘050375 ‘os8125 ‘057500 ‘0.56250 Vez nme 125625. ° 12475. 122500 121250 1.20625. 119975 1.17500 1.16250 ° ° 114975 1a 1 i ° Dotasheat 16Table 2-1. Voltage Identification Definition (Sheet 3 of 3) ofatetatol of of} olin) ite) afofifo| 1] + loss of apoio} ol 1} rio} “1 ea ofi[1{ 1] 0 {osesmo ofa ora ofa | ©} 1 {ions} “1a 1{o| | «| 0 {ost epee tepe ete fiame| Cte eta poet ofr fame ctrtete tre] ef opi Cet apap er tt ef on of ato tata} of 1 | 0 {i0so00 Table 2-2. Market Segment Selection Truth Table for MS_ID[2:0} wsioz | wsio1 | 5100 | Description! a © | Resened rt 1 (© | tres Core™ 7-900 desitonarceasor Exrone Elon sees nd Inte Core™ 7-900 dest processor serch 3 3 1 | Reserves 1. The MSIO{2:0 las af provided to inceate the Markt Segment for to proeseor and maybe ued for Fire processor Compatbiy or for keying 2.6 Reserved or Unused Signals Datasheet Al Reserved (RSVD) signals must remain unconnected. Connection of these signals to Vcc. Vira. Vito. Vow Vecett, Vss, oF to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all Reserved signals. For reliable operation, always connect unused inputs or bi-directional signals to an appropriate signal level, except for unused Integrated memory controller inputs, ‘outputs, and bi-directional pins which may be left floating. Unused active high inputs should be connected through a resistor to ground (Ves). Unused outputs maybe left unconnected; however, this may Interfere with some Test Access Port (TAP) functions, ‘complicate debug probing, and prevent boundary scan testing. A resistor must be used ‘when tying bi-directional signals to power or ground. When tying any signal to power or ‘ground, 2 resistor will also allow for system testability. ”Table 2-3. a Signal Groups ‘Signals are grouped by buffer type and Electrical Specifications ilar characteristics as listed in Table 2-3. The buffer type indicates which signaling technology and specifications apply to the signals. Ail the differential signals, and selected DDR3 and Control Sideband signals have On- Die Termination (ODT) resistors. There are some signals that do not have ODT and heed to be terminated on the board. The signals that have ODT are listed in Table 2-4. Signal Groups (Sheet 1 of 2) ‘Signal Group Tyee System Reference Cock Diferenl lock input tk br, BCK_ON Intel® QP Signal Groups "Differential J fetel QPF tnput Dierental ‘es QP Output ‘Tort bax otweinisn), ar aK oF, Grr euee oH BORE} GPL CLE = ‘BRE Output oR(Or/a)_CLMOFPIESOT DORI Command Signals "Single nae ‘CHOS Output DOR(O//2) BASe, DORIA) case, Bow{ori/2} wee, oomto/4/2) Bais, Bonto//a}-anis-oy ‘Silo ended ‘Asynchronous Output DDORCOVi/2)- RESET ORS Control Sionals ‘Sle ended ‘m0 output DoRCovi/2)_cse{s:4}, ODR(0/1/2)-cS#i1-0), BoRCOri/2}-o0Tt3:0), BORCO/1/2}-CKELS:0) ‘Sings ended (GHOS Brarectonal ‘oRo/2} Das) Diteren (CHO B-directonsl DDoRCovi/2}_Das_IW/PII7:0} TAP ‘Single ended “Ta Tope ‘Te, To, 145, TAST# ‘Single ended ori ouput 00 ‘Single ended Dsypetonous GTL Output | PROS ‘Single ended ‘Asynchronous GTL input | PREOW ‘Single ended GT. Briectonal CcaT_enR, BPMaI70) ‘Sine Ended Asynchronous Brarecsonal | PECT ‘Single Ende ‘Analog Input ‘Convo, QPi_cwero}, DOR_cOMP(2-0) ‘Shale ended ‘Asvnehronous GTLB Prochore Setcions ‘Single ended ‘Asynchronous GTL Output | THERMTRIPE ‘Sine ended ‘CHS put/Outt woir6} ipts:3}esc(2:0) spje:0}s10(2:0) umr_vipje:2} Detashestaa se (intel Table 2-3, Table 2-4, 2.8 Datasheet Signal Groups (Sheet 2 of 2) Siar Grove Tyee Siena Sigieendes | C105 Output re 042) Seale nde | Aion out [soot Stgieendes [fast pit [Rese Pw Rco00 signals Sig ends -eyeron pt \ECPARGO00,VTPWRGDOD, VODPWRGOOD Power/ other ic VE, VITA VITO, VEER, VOOR "poretanous GHGS Ott | Pate Peseeesese 7229] Ober teeer server serea] etooee, oon teneeerenenIeTCarg| 1. Refer to crancer 5 for signal desenptons 2. BOR(H/72} refers to OORS Channa 0, BORS Channel 1, and ODRS Channel 2 Signals with ODT "QPL BEXDRTg 1 GFL_BRK BNGB-1 GPL_BPX PLS], GPE PNB: QPCR BINA + Bowser), Dees), A0//2).09s_ {WF DOR(/2)_PAR_ERRIO:2), VODHWRCODD + Bux ITP EWr] rect BpMs(7:0), PREQS, TASTE, VCCFWRGOOD, VTTPWRGCOD "Gress clnervise specie signals have OOT in the package wth 50 0 plow t Vs rEg, Bent7:0) Tl, TH and BCLK TTP DIN) have OUT In palage with 350 fuiup to Vee ‘Veetnincads, VoDPURGOOD, and VITPVINCOOD have ODT in package wah a 10 ka t220 kl uldown ‘TRSTY has ODT in package with 91 ka to 5 ka pulp to Vir ‘ALDOR slat are torinsteg to VDDQ) ‘DOR V/2) rear to BOR channa 0; DORS Channel 1, ané DDRS Chanel 2 Wate TMS and TDL do ret Rave On-DIs Termination, thse ial are west) pula up using 9 1-5 ka {iio Se at have Ome Temirsn, th soa sweaty pled donning a 1-5 rao ko All Control Sideband Asynchronous signals are required to be asserted/de-asserted for at least eight BCLKs for the processor to recognize the proper signal state. See ‘Section 2.11 for the DC specifications. See Chapter 6 for additional timing requirements for entering and leaving the low power states, Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the processor be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to ‘connect to the rest of the chain unless one of the other components Is capable of accepting an input of the appropriate voltage. Two copies of each signal may be required with each driving a different voltage level 192.9.1 Table 2-5, Platform Environmental Control Interface (PECI) DC Specifications PECI Is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature. ‘Temperature sensors located throughout the die are implemented as analog-to-digital converters calibrated at the factory. PECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control. More detailed information may be found in the Platform Environment Control Interface (PECI) Specification. DC Characteristics ‘The PECI interface operates at a nominal voltage set by Vrrp: The set of DC electrical ‘specifications shown in Table 2-5 is used with devices normally operating from @ Vrrp Interface supply. Vr nominal levels will vary between processor families. All PECI devices will operate at the Vrrp level determined by the processor installed in the system. For specific nominal Vrrp levels, refer to Table 2-7. PECI DC Electrical Limits Va |e Voge nse am [re mec | teri tive [wav Vn | Regie ied atnge 0275 vo | 0500 *Vro |v Xp Festiendnetresrlsvotane S80" Uno) O755*Yre VI gh eel output source ae caer Neowee | (gy = 0.75 * Vera) f Lem vt 025 vi) sete eeiseeeecipoee Tn | ih moses elope Vo 5 tates seek | (aah = Vou) ai | eee wa wow | Gar |Oes capactace por rode wa oe nes | Signa nie munky above 00 WH) 04* Vay | WA) pp 1 Gry euppliee the PECL interface, PECI Behavior dose ntact iro min/max spceatons. 2. Tibiakdge epciestion spats to pomered vices on the PEC ba DetashestElectrical Spe 2.9.2 Figure 2-2. 2.10 Datasheet Input Device Hysteresis ‘The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 2-2 38 a guide for input buffer design. Input Device Hysteresis oo Maximum Vp |, |, PECI HIgh Range | -Minirumm Vp Minimum |. Val Input Hysteresis” Signal Range “Notun $e Minimum Vie—— [4 | PECI Low Range | | ~PEC| Grount_—_$§#=- i = Absolute Maximum and Minimum Ratings ‘Table 2-6 specifies absolute maximum and minimum ratings, which lle outside the functional limits of the processor. Only within specified operation limits can functionality and long-term reliability be expected. ‘At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions autside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation ‘condition limits. [At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it wil either not function or its reliability will be severely degraded. [Although the processor contains protective circultry to resist damage from Electro- ‘Static Discharge (ESD), precautions should always be taken to avoid high static voltages or electric fields. aTable 2-6. 2.11 2 Processor Absolute Minimum and Maximum Ratings Symbol Parameter Min ioe | unie | Notes! Voz | Processor Core wate with respecttoVss | 0.3 as |v | ‘Vetage forte analog portion ofthe tegrated | — as [v3 Vn | memory conte QP ink and Shorea Cathe Wren reper toss | ‘Vettage forthe digtal ertion ofthe integrated | — i [v3 Yr | amery contol, QP line and Shared Cache Lint relpect to Vas | | Voog | POSES 10 suppywatage fr DDRS with = tes |v oe | Fspact oo Veou_| Processor PLL votage with respect to Vss 1.65 ie |v “Tee | POCSE0r case temperature ‘See See ase cramers | cuter F Storage temperature See se |< rome comers | coeptere notes: 1 "For fuetionl operational processor eect, lal qualy, mechanical an thermal specications mast be sats. 2, Excessive overshoot or undershooton any sine wil iy result in permanentdomoge to he racer 3, Visa and Vay shouldbe denved fom he some VR Processor DC Specifications The processor DC specifications in this section are defined at the processor pads, unless noted otherwise. See Chapter 4 for the processor land listings and Chapter § for signal definitions. Voltage and current specifications are detailed in ‘Table 2-7. For platform planning, refer to Table 2-8, which provides Vcc static and transient tolerances. This same Information is presented graphically in Figure 2-3, ‘The DC specifications for the DDR3 signals are listed in Table 2-11. Control Sideband land Test Access Port (TAP) are listed in Table 2-12 through Table 2-15. Table 2-7 through Table 2-15 list the DC specifications for the processor and are valid only while meeting specifications for case temperature (Tease 85 specified in Chapter 6, “Thermal Specifications"), clock Frequency, and input voltages. Care should be taken to read all notes associated with each parameter. Detashesttoe laren (intel 2414 Table 2-7. Datasheet DC Voltage and Current Specification Voltage and Current Specifications ‘Symbol Porameter win [tye | Nox [une] Notes vio | Wb renee ve | fas pv Processor | Vecfor pressor cre Nome 7975 aaacke 17-965 320K Voc | 1-960 520k See Table 2-3and Figure2-3 | v | 3 7-330 2.80 cHe 7920 beech Notae fo the elo porton ofthe Vem | Ineerated merery convoy GPtiing | SeeToble2-10.and Foure 2-4] vi | ne Shores ache \otage forthe aga pation ot the no | tg marry conve, Gein | see Toie29andgurea-s] v | s Voeg | Proeaitor/0 supp vatage eros | tas [is [iss |v LL auppywaltege (OC + AC ra [as] ae Yom _| Spectesny Procesor efor rocesor Rober” 7975 aaacke us 7965 3206Ke 145 Kee | 17-960 520k - | - Justa] « 7-390 2.80 Ge 145 7920 beck us Currant fr the analog pectin of the rm | Integrated emery eanwater artink | — | — | os | a Currant forthe ata pation athe to | tegated memory convoter arin | — | — | 2a | a ‘oq | Processor 170 suply caren or DRS | ea Faceor VO supa rent frboms [|| Py | Tecvecsu | PL supply urvent (OC FAC speaentony| —— | — | aa | ® Note 1. Unlasotervise noted, a spcictone nti able are basa on estimates and skultbons or emplical is reesei ea pete chr ate ser enurr ort 12, Eat processors programmed wih man vad voltage eration value (VIO) mien es at Imanvfecuning and ca ote area aca maximum v0 vues ae colbraes cng menatactrng [heh that two procesters atthe sme reauency may have afferent settnge win the Vl range ease hate ts afer From the VID employe by fe broesvor during s power ranegement event (scapeve ‘Thermal onto, Enhanced Ine Speadstepe Teccloy,o” Lew Rewer Saas) 5. The voagespetheatonrequremerts sre measured serbss VCC_SENSE ana VSS_SENSE lands atthe bees wih 3 100 be banghotheociseape, 15 pt maxim probe capoctance 2nd 1M manimum impedance m= maximum eng se pround wir on te pre seid bess than en. Enis exrana ote fom the sytem I ot coupe Ie te oscloscape probe, 44. ‘fer tole 24 and Pigure 2-2 forthe minimum, (yea a maximum Voc alowed fora ghven curert {The procesor shal nol be sunjated tw ay Vor a lg combnaton wrerain Vor exc008s Vos yay OF aguen caren 5 RENEE er tat on Vr Vtage Heaton aa le 29 and ie 2 fr a oe Vy lee ame specfeaton Is based onthe Voc ypx loadine Reter'o Faure 2- for ta BieBteton 1s based on a processor amperature, 36 reported by the DTS, of less than or equa to 2Table 2-8. Vee Static and Transient Tolerance ee (A) Vecnve(¥) Yee Veen (¥) Notes ° Vio - 0.000 wip-o.019 | vip 0.038, 42,3 Pa] wo 0.008 | ao a.027 | vanes 12,3 Cos vio-003 | vi-0.051 | vio 0.070 12,3 = vio-001 | vi-0.058 | io -0.078, 1.2.3 8 vio-0.060 | wip- 0.070 vip - 0.098 123 78 Vio - 0.082 Mio - 0.081, ip - 0100 12,3 rs Vio 0.088 vip 0.087 Vib = 0.108 12.3 °° vio -0.072 Mio - 0.091, vio - 010 1.2.3 Pas] wo0.002 | aout vip - 0130 423 120 Vio 0.056 wip 0.115, vip - 0134 1.2.3 5 Vio = 9.100 wip 0.119 vip 038 42.3 130 Vip 108 wip 0.128, wip - 0142 12.3 1 The Vex ay 206 Vex yp eanes represen tac and transient lms. Se8 Secon 2.1.2 fr Vee 2. This tane is intended to ain reading dlscrete pnts on Pure 2-5 5. Theteadines specty vonage Its at te ale measured atthe VCC_SENSE and VSS_SENSE lands. voltage {oti feedac or age eps ces must i be ian rom processor Vec_SENGE ana DatasheetElectrical Specifications Figure 2-3. Vee Static and Transient Tolerance Load Lines Bre sraruieibie tai sieiaierere 5 Table 2-9. Vr7 Voltage Identification (VID) Definition Vio? | vid6 | ios] vibs | vios]| vio2 | vioa | vioo @ epe;ofels Ta0v 1a70v T5v 1095 1s is 2 ype witage, See Tele 2-10 for VIT_Max and VIT_Min vote.(intel Table 2-10. Vyy Static and Transient Tolerance br) Nates Vor noe (¥) vio + 0.0075: io - 0.0045 | io = 0.0225 io = 0.0045 | Mio = 0.0405 vio - 0.0525 vio = 0.0705 io - 0.085 io - 0.080 vio = 0.1185 vio 0.1305 Te ad nt abl a samo 2. Tholeblinee spec voage its at ne Verne) ‘io ~ 0.0240 ‘io ~ 0.0360 ‘i = 0.0540 ‘iD = 0.0660 io - 0.0720 ‘ip ~ 0.0840 ‘ip = 0.1020 Vip = 0.1140 ‘ip = 0.1200 ‘io = 0.1500 ‘ip ~ 0.1620 and iyo Electrical Specifications nO Yen vio - 0.0555 vio - 0.0675 vio = 0.085 vio = 0.0975 vio ~ 0.1035 vio~ 0.1155 vio = 0.1335 vio = 0.1455 vio = 0.1515 vio = 0.1815 vio ~ 0.1935 Notes! 2 odsirod at he VIT_ SENSE and VSS_SENSE_VTT longs, Voltage Teguason fedcsace or vekage Teguster crcute must ls Be token irom Srocesa? VIN SENSE She BSISENSELVTT lence, DetashestFigure 2-4, Table 2-11. Datasheet Vz Static and Transient Tolerance Lead Line = y DDR3 Signal Group DC Specifications ee oe a a nko an relat ~ =| wees [= casera | | ge pn 2e,) | wf ae (RonltRon re) Sarees tT a = au a vo acme | e ~ fs vom [Rago | os : = |e presen von |B » - » | fon |poRsoae Buteron | ay - ax | a Teg | wn | a —] aa sem heieacs | eo or 1 inissotnerwise note, al specications inthis abe apy to al pracesorrequences, 2 lene emt vokage i! a ee ape ht i be pete a lng ow 3. Yl ceed a ne minimum eagle! at receng agen tat ibe trrted 5 lca oh »Table 2-12. Table 2-13. Table 2-14. 2 Electrical Specifications No may experience exrsion above Vo, However out al vers mat coms with he {CoWP resistance rust be proved onthe system boars wth 1% resistors, RESET# Signal DC Specifications Symbot Parameter win | Tye Max units | Notes! Vin Input Low Voage = 7 040% Vin |v 2 Vin | Input Fgh vokage 080*Vm = aa Ty [Input Leakage Curent = = 200 a 3 Pismo ciate corm eae ncn 3. Forvin ‘O'V and Vrq, Measured when the driver ls tistated.”” 4. Meqand Voy may expen oeersne sone Vo TAP Signal Group DC Specifications Symbot Parameter me] wax unis | Notes! [Va Jinpat tom vonage = 0.40 Vin v z Vin Input High Vokage 075" Vm) — = 2A Vor | Output Low vaage = — Timaru’) 2 nt Rasen) Vax | Opa High voage on = = v_ [2a Fon | Buf on Reistence 10 = 8 a | Iput Leakage Curent = = #200 “ 3 Gress cterwise noted al specications n this able apoly to al processor requencs 2. Thevereteneston tase spetistions retest natntancous Ver 3. For uly bawacn 0V ond Vy, Measured ten the vers sated 4. Mig and Non may exoerendl excursions above Vor PWRGOOD Signal Group DC Specifications ve [Raman sperm | eae vf es va [ig wemewwonncas gay fy ps Ve [RPE SHMEHOE a asevw| — | - «| we a Fgurorommreence gy | Taba eo fe ee ee ii “Snes oteruise note, al speciation in this table appy tal processor requencls. ‘Theva refered ton toes speciation reer to atortoneau Va For un beeen 0V ond Vy ensured when the over sated 2 5 3. Wand Vy may exon encsine ave Vi '5, This specication apptes to VECPWRGOOD ond VETPWRGOOD 6 Ths Specteton apps to VODPNAGDOD | Detashestea (intel Table 2-15, Control Sideband Signal Group DC Specifications. 2.11.2 Symbol | __ Parameter tin | te wax | Unts | notest Varo Lon ose == aan Vin Irth voeape | O78) = = v2 Nog Oat. Woe See [ oa se retealieesa haa or] Opa igh Voge a = apa tufeconnesstncefor | - ° Fon vipi7:0] =~ ‘a | opt entogeGarent [=| 200 als Unless othernise noted, al pecans in hs table aply to al processor Fequencles 2 Theva refered en thece species refers to atomaneous Urn 3. Foruth beeen OV one Vy, Heosured when te dre estate 4. Wgand Vy may expend excusing above Vr ‘5. COMP resistance must be provided on the system board with 1% resistors, Vcc Overshoot Specification ‘The processor can tolerate short transient overshoot events where Vec exceeds the VID voltage when transitioning from a high-to-low current load condition. This overshoot ‘cannot exceed VID + Vos. nix, (Vos. siax Is the maximum allowable overshoot above VID), These specifications apply to the processor die voltage as measured across the \VCC_SENSE and VSS_SENSE lands. Table 2-16. Vcc Overshoot Specifications Dotashect symbol Parameter win | Max | unke | Figure | Notes Vos max Wagrinude of Vag overanoatabovevio | - | 0 | mw | 25 Tos.nax Tive drain of Veo overshostabove id | | 25 | ws | 25 2Figure 2-5. Vcc Overshoot Example Waveform Example Overshoot Waveform VID + Vos: vip: Voltage (V) Time Tos! Overshoot time above VID Vos: Overshoot above VID 2.11.3 Die Voltage Validation Core voltage (Vec) overshoot events at the processor must meet the specifications in ‘able 2-16 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot ‘events that are < 10 ns in duration may be ignored. These measurements of processor dle level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope. § 2%” Dataset,Package Mechanica Specteatons (intel 3 Package Mechanical Specifications Figure 3-1. 3.1 Datasheet The processor Is packaged in a Flip-Chip Land Grid Array package that interfaces with the motherboard using an LGA1366 socket. The package consists of a processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) Is attached to the package substrate and core and serves as the mating surface for processor thermal solutions, such as a heatsink. Figure 3-1 shows a sketch of the processor package components and how they are assembled together. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for complete details on the LGA1366 socket. The package components showin in Figure 3-1 Include the following} + Integrated Heat Spreader (IHS) ‘+ Thermal Interface Material (TIM) + Processor core (die) + Package substrate + Capacitors Processor Package Assembly Sketch Di yM \—— canactors LGA1366 Socket "Socket and moterboard ae ncaa for reference and are ot part ofthe processor package, Package Mechanical Drawing The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include: ‘+ Package reference with tolerances (total height, length, width, etc.) + THS parallelism and tit + Land dimensions ‘+ Top-side and back-side component keep-out dimensions + Reference datums + All drawing dimensions are in mm, ‘ Guidelines on potential THS flatness variation with socket load plate actuation and installation of the cooling solution is available in the appropriate processor Thermal ‘and Mechanical Design Guidelines (see Section 1.2). aPackage Mechanical Speciications Figure 3-3. Processor Package Drawing (Sheet 2 of 2)aie Table 3-1, 3.4 Table 3-2. 3.5 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep= ‘out zone requirements, A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to elther the top-side or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keep- ‘out zones. The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep-in. Package Loading Specifications ‘able 3-1 provides dynamic and static load specifications for the processor package. These mechanical maximum load limits should not be exceeded during heatsink assembly, shipping conditions, or standard use condition. Also, any mechanical system ‘or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solution. Processor Loading Specifications Ste Compesive ied | san (2014 saa | yar cores nd | 38 0) ae eae uae compeesive dynam) 1 These specmestons appy to unform compress lescng m2 drcton normal tthe processor IHS ‘Tre minum ane maximum mt fore tat bn be apd by haar a rete son ‘The spechistong on based oy im tering for design characterization Loading lite are forthe package any and do not incuce ie ate ot process seca «Bir is ned a tn Steel speipeed one ac od Package Handling Guidelines ‘able 3-2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate, These package handling loads may be experienced during heatsink removal Package Handling Guidelines Package Insertion Specifications The processor can be inserted into and removed from an LGA1366 socket 15 times. The socket should meet the LGA1366 requirements detailed in the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) DatasheetPackage Mechanica Specations (t 3.6 ae: Table 3-3, 3.8 Figure 3-4, Dotashect Processor Mass Specification The typical mass of the processor is 35g. This mass [weight] includes all the ‘components that are included in the package. Processor Materials ‘Table 3-3 lists some of the package components and associated materials. Processor Materials Component as Integrated Hest Spreader (HS) Nick Piated Copper Substrate Foor Reinforced Resin ‘Geld Pated Copper Processor Markings Figure 3-8 shows the top-side markings on the processor. This diagram is to aid in the Identification of the processor. Processor Top-side Markings INTEL® ©°07 PROCE BRAND SLxxx [COO] SPEED/CACHE/INTC/FMB [FP0] @ackage Mechanical Specifications 3.9 Processor Land Coordinates Figure 3-5 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. Figure 3-5. Processor Land Coordinates and Quadrants (Bottom View) DOOD OOOSOCOC OOS OPOOOOOOOCO DatasheetLand Listing 4 Land Listing ‘This section provides sorted land lists in Table 4-1. and Table 4-2. Table 4-1 Is a listing of all processor lands ordered alphabetically by land name. Table 4-2 isa li processor lands ordered by land number. Table 4-1. Land Listing by Land Name (Sheet 1 of 29) Table 4-1, Land Listing by Land Name (Sheet 2 of 29) ing of all Land wame | 1208 | Buffer] oiection tana name — | tyne | Butler] ovreccon Non | "type Now | "Type Bcc Dw was [ors [7 “oro_cSat5] a7 [eros [o ecu or ss | ows | 1 ‘DoRO_Dato) war [eros [70 ‘coc TF Dw ‘aaa | Gros | 0 ;DoRO_Data) var—[ on0s_[ 10 [ecucrP_or ms | ovos [o ‘Dono _Dgt10) raz cows | v0 Bevsio] @ [en [wo ‘DoRO_Datna) asf os [10 cena] as fen} wo ‘DoRo_pgt12) ra [omos [10 ws aan] We ‘DoRo_bgts3) rai [omos [10 foro a [en | vo ‘DoRO_Dgtt4) us [es [0 wets] Bren We ‘DoRO_DgLIS) ta [eos [70 eonats) fen} v0 DoRo_Dgtt6) wai | cows | v0. Bower) 2 [en | vo ‘DoRO_DGLI7) was [coos [V0 coowerri 2 [en —} v0 ‘DoRO_OgLis) ea [ows [v0 ‘CAT_ERRE eaT_[ on] v0 ‘DoRO Dats) Bs [ows [v0 ono ‘nas | Anaiog ‘ORO _DGt2) na [ows [10 aR AIO [Reymeh [T ‘DoRO_DaL20T | ors [Wo ‘oR. CONBTO] ‘naa [analog ‘DoRO_pat24) sa | onos | v0 ‘oR CONPLE] v7 [analog ‘DoRO_Dglz2) Fa [os [10 ‘BOR CONPT>] ‘ei [analog ‘DoRO_Dg(23) Fa [ows [10 DOR VREF (3 anaiog [T ‘DoRO_Dgl24) Dao [cows [v0 ORO Baro) sxe | ows |o ‘DoRO_DgL25) ca —[ eros [0 ‘DORO-BALHY aie_—_| Gros [0 ‘DoRO_DGL26) mae | onos [V0 ;DORO_BAv2] cas | ovos fo ‘oR _Dat27) ps7 | exos | vo. “ooo_cas caz_| os [0 ;DORO Doras) bares [V0 ‘DoRO=CeEOT eat or0s fo ‘BORO _Dar2s) Daa [coos | v0 ‘DoRO-cxeLIY ms0[ ors To ;DORO Dats] Raa [ows | V0 (ono _cxet2) ss0_| ows |o (DoRO_Dar307 ‘cae | oros | v0 ‘DoRO_cxEIS) 3s1| avs fo DORO_DaDsa) B38 | HOS | V0 DoRo_cx No) KIS | cock | o ‘Dono _Dar32) 85 | cows | v0 DoRo_ax nia) ca9 | cock |o ‘DoRO_DgLs3) ‘c_—[ or0s_[10- DoRo_Gx Nia) ei | cock | o “boro_pais4l [ens [vo | DoRO_GX Nis) —e19 | aoc fo ‘oR _Dat35) [ors [v0 Done _cix_r(0] us| cock |o ‘DoRO Dare) 35 | cos | v0 ‘DoR-GxPT Dis [aoc fo ‘DoRO_DaGs7) [ones [0 ‘DoRO_Gx Ia] Fis [cock fo ‘Doro _Dar38) Blows | v0 ‘oR Cx PI] 20 | cock [o ‘DoRO_DgLs5) [ows [10 ‘ORO C540) ais [anos [o ‘BORO DO) wae | ovas [vo ‘DoRO_CS8(i] ‘10 | Gvos fo ‘DoRO_DgrAo) ia [ows [v0 ‘oRO_c5ei4] ais_| ows |o ‘DoRO_Datéa) Hi fens [70 ‘DoRO_Dacaz) a fewos [v0Table 4-1. Land Listing by Land Name (Sheet 3 0129) Table 4-1. Land Listing by Land Name (Sheet 4 0f 28) ‘ana ‘ater ‘ana ‘otter and Name tend | Butter oyrection and Name isnt | Butter] orrecton ‘oaT_OgTe3y ma [ows [ve ‘DoRO_MATLAT 72a_| cH0s [0 ‘DoRO_Dgte cr | enos [0 ‘D0RO_MALIS) 29 | ows fo ‘DORI_Dg'e5] me [ros [VO ‘D0R0-A] ca_[ ons fo ‘DoR0_091<6) is | eos | vo ‘2080_MA3] pa | ows |o ‘pad_Ogi=7] [eros [70 ‘D0R0_MAla] 23 [ows [0 ‘DoRt_09(¢8) mt [cmos | v0 ‘BORD_MA(S] naa [wos [oO ‘DDRE_DQ'«3] na [ews [v0 ‘BORO. Ale] c@e_| owos [0 ‘DORO_DgIS) waa [ons 0 ‘DORO_Al7) 225 | onos_| 0 ‘oa_DgI=Oy rf enos a0 ‘DORO_FAUS) B25 | ows TO ‘DoRe_Daist) 2 | ones | v0 (DoRO WAS] 2s | owos | 0 ‘DORE_DQIS2] re ors [Ve ‘DORO_OOTIOT Fz | ow0s_[o. ‘Doad_0g153) 13 [ewos v0 ‘DoRO_OoTLi) ‘9 | oHos | 0 ‘Doad_0a154] na [aos [vO ‘D0R0_00T12) an [ows [fo ‘BbREOQIS5] af enos [0 ‘DORD_OOTL3] @ | ov0s 0 ‘oRI_bQIS6] [ews [v0 DORD_RASH [ewes [o ‘boRo_bai57) vi__| onos_| v0 DDoRo_Resere x2 | owos | 0 ‘DORD_Dots8) ye [eros 10- (ORO. WE 31 [ ows [o ‘DoRO_b0155), ys | onos | v0 ORI _BATOT ‘cis | owos | 0 ‘DoRO_Date] vat | o10s [v0 DOR_BAII] Kia [os fo ‘Doad_Doted] vi tows [v0 ‘DoRi_BAr2] rar | ows [0 ‘DoRU_Dgi61) 05 [ ows [v0 DORI_CAS# Fs | ows To ‘poae_pal62) va | onos_| v0 Dont cxe‘o) 128 | ows |o ‘DDRU_OgI53) ‘wa —[ onos[ v0 ‘DORI_CKEL 7 | ows [o Doro_pi73 a2 | owos | v0 ‘DoRI_cxei2) var | ows fo ‘boR0_Dai8) nat [10s [v0 ‘DoRI_cKEiS} [ows [0 ‘DoRo_Dais) nas | o90s [v0 ‘DoRL_CU_MOT par | cock [o ‘DoRO_D9s_Nfa] | vas | cHos [10 ‘Doai_cuCNG | 620] ocx To owo_pes.vii] | mai_| cwos | v0 ‘oat_CuC M2) tus | cock |o ‘DoAO_D9s_Nz]___| Gti | cnos_| 10 ‘DORIC ni9[ cock To. ‘DoaO_Dgs.N(3) | 640 | cwos [v0 ‘boat cu FO} ea [ack [0 ‘DoRU_Dg5.Nie) |e | cwos [wo ‘boa CuK PI ‘cis | cock [0 ‘Doa_D95.Nis)— [x3 | cnos_ | Wo ‘DoRI_CUKPI kis | Gock [o ‘DoRT_Dgs.Ni6) | ®3 | cnOs [WO ‘oRI_CFT wis | Gock [O oao_pos.ni7} | wi | cwos | v0 ‘Dont_cs#i0) Diz | ews |. ‘DoRo_b9s.pfo) | T43__| cnos | Wo ‘ORI CS#01] 8 | Gnos_| 0 ‘oao_bgs.Fit] ai | cwos [Wo ‘Dont_csafe] ‘ar | owos | 0 ‘DoRO_Dg5.Pia]___| Fai__| cnos_| Wo ‘DoRI_C5#°51, Fo | ows [0 ‘DoRd_bgS.Pa] 639 | cnos | Wo ‘Doa_0gi0} Aa? GOS | WO ‘DoRO_DgS. Pla] [=> | cnOs [HO ‘oaI_DQiT FR | GOS [WO oao_o9s.is} | 12 | cwos | yo ‘Doa_0Q120) 29 | ows [vo ‘“Dowo-ps-pte]_—k2 | omos_ [7 ‘DoaI_DQiTET Tae [ores [V0 ‘oRo_69s.PD] [wa | ewos [yo ‘DoRI_0Qi22) maa [eos [vo ‘BDRO_ ACO) 20 | oHos| 0 ‘DoRt_Datis) nas | ews | v0 ‘DORO_MACAT Bar| Hos [0 ‘Doai_Dotis) nar | o¥0s | v0 ‘DORO_HACIOT Bia | ows [O ‘DORI_Datis) nae | oW0s [VO ‘DoRO_MACtA) 226 | cwos | 0 ‘Doat_Datte) 35 | o¥0s_| vo ‘DORO_HACIZ) B25 | oMos [0 ‘DORI_Dali7) 134 | GW0s [VO ‘DoRO_WACIS) ‘Ai | Gros | 0 ‘DoRi_Dalia) 35 | vos [vOens (intel) Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 5 of 29) Gheet 6 of 29) Lena wame | lan | Ber Torecon tana weme | fan? | Bue" or ecton STB Ts paws Po TRB aa Pons PT ‘oRi_bara “as | ows | v0 Dats wows | v0 ‘oRI-Dar21 rea vos [70 DR _baU7 va [eos [70 ‘oRi_Dara mae | eros [70 oR bare] aa enos [70 BDRI_DOL21 nas [eros [V0 DRI _ba11 vas_[enos [0 ‘RI_Dar231 we | cr0s | 70 oRi_bgs_Wal [var —|ewos | V0 DRI_Dara] 733 [ eros [70 DDRI_bGE_N] [837] OS] VO ‘oR1_Dar2s1 ta | ows | v0 oki_ogs.N2l | 36 | wos | v0 ‘RI=DALE] wa2_[ eros [70 DbRI_DGS_NG] [a | eras V0 ‘eori_paa7) 32 [owos [v0 oRi_bas.nel [67 [ews [v0 ‘RI _Dal] ae [exos | 10 DoRi_bas.sl [es | ewos | v0 ‘RI=Dar29] rea |exos | 70 DoRi_bas_Nél [ts | wos | v0 BRIDAL] at [eros [70 DoR:_bas_N7| [ve | enos [70 ‘Ri_bar01 (| os | v0 oki_ogs.rio1 | va | nos | v0 RI_DADHT Wao [eros] 70 DDRI_OgS_P]_—[ RHE HOS] TO ‘RI=Dals1 [ows [10 DoRi_ogs.ma1 [0 | eros V0 ‘{DoRI_DQI33) T= ‘anos | 1/0 DDRI_DQS_P(3} G0 | mos To ‘RI=DaLs] [eos [10 pRi_bgs.Ral fe” | wos | v0 ‘RI=DALS] 5 [eros [170 DoRI_bas=AS]— [ws | ras | V0 ‘ok!_DaIs6) Fio__| nos | v0 oki_pas.ris] | ts | nos | v0 ORI_DaI7I ‘eros [70 DOR:_bgs_A7| | va was] 70 ‘RE_Daie1 be | e105 | 10 DORE MAG nia fows To BoRi_DOL1 Fe | eros [170 ORS_MAS] nie fows To oRi_bata] ‘af ov0s | 170 DORE HALO] wnat [enes [0 Boat paro] 7 Poros 0 DORAL] =r [ores [o oat] ae [ows | 10 ons n1_|ows |o Toort=pave)———6r [ows [70 boast} aia [onos[o ‘oat 59191 na fons [70 oR aL ve [ens [o oni _pat] @fews [10 ona] ras [ews [o bai paLt 19 ows [70 Ri _WAI 17 fers fo ORI_Da6] eres [10 DRE MAT wafers [o oki_bava7 35 ews | 10 DRI mals van [ones [o RI_DaHe] va [e105 [70 DREMAL] a2 [ens [0 ‘RI_DaUo1 xs | vos [10 BDRM iy [ows fo oRI_DarS] 1636 | cros [V0 BDRM} ozz_ [ens [0 RIDA] as | exos | 70 DDR MALS =a [onos [0 RI=DaIs] 1s [ eros [10 DDR MA ca _fons To ‘oki _DaIsa1 aa ows | 10 oni 0o710] on |enes |o Ribas] 6 [ewos [70 DDR OBTLT & [ews To ‘oRI_Dars a8 [eros [70 DRY ODT] oe [eres [0 ‘[DoRi_DQIsS] TR? G05 | 1/0 DDRI_OOTT3] Fi | cmos Jo. DoRI_DaIs1 wef ows [170 DDRI_RASE ais fons fo RIDA WF [eros [170 DDR RESET? 3m [eros [o ‘R1_DaIse) ‘10 ews | 70 Doni wee aa fows |o RIDA] wid [eros [70 3 RE_BATT air [ewes [To ‘RI=Da] Tre —| ens” [170 DDRa_ BAT) nr [ows [o ‘oRI=Da‘6o1 va [exos [70 DoA2_BA2) ts [ens [o ‘RL_DaK6sl ws [eros | 10 DORE CAS ris [enos [oTable 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 7 of 29) (Sheet 8 of 28) tana name | 4804 | Buffer] oirection tananame | land [Butter] o tend | 6 isnt | Butter] orrecton ‘oaz Cee) as ons fo ‘baa DgI3B) mz | ov0s [0 ‘DoR2 Cie] ‘e2s | cnos [0 ‘DbA2_0g/39) ta [ores [70. ‘Doze 2 | oHos [O ‘D0R20QiAT Ta [ors 7 02K] 27 | ows |o ‘b0a2_gi40) ue | aves | vo ‘Doe CXK Mani | ook fo ‘Boa DQiAi) 10 | ow0s 70 oR cucMi] | a0 | cock | ‘DOR? 6Qi42] ne [eos [vo oR2_CUKN2) | G2i_| ocx | 0 ‘boa? Dass) ne | wos | v0 ORZ_CUCN) | 21 | ocx | 0 ‘DoR2_Dai44) tit | o¥0s | v0. ‘DoRZ_Clx_PO 3 __| GocK | 0 DOR2_DOIss) mid | Cvs [VO poa2 cu Pit 120 | ctock | 0 ‘Dow? Dai46) ts | evs | vo ‘DDRZ_CUC PL rar | dock |. ‘DOR DQla7) ne | vos [V0 ‘boA2_ CUP] iz tock [0 ‘DoR2 Dasa) 7 [ov0s| v0 ‘oz. C#10], ‘cis | onos | 0 ‘boa2_0gi48) ne [ovos [Wo ‘02 CeHIi) aa fos [o ‘DoR2_DgI5] vse | ows | v0 ‘DORE CSHIe] 7 [ons [0 ‘DOR? DQisOT [eros [ve oR2_c5415) ps __| cmos | o boa2_Daisi) P10 | wos | vo DORZ DIO) ‘wat | GHos 16 ‘DOR? DaIs2) ne | o¥0s_ [V0 ‘DDR? Dati) was | cros | v0 ‘DoR2 DaIs3) | evs [v0 ‘DoR2_DOt10} R39 | oH0s_| vO ‘DoR2 Dass) Rid | o¥0s | vO ‘baz DotiiT 36 | onos | 10 ‘Dow Dass) na | ows [v0 ‘DbRa Dalia] was | oW0s [V0 ‘oRA_DaIs6] us| Gros wo p0a2_09113), v39__| owos_| v0 ‘DoR2_Dais7] us| ows | vo ‘Doz_balia]| ai [ onos | v0 ‘DoR_Daise) mio ow0s[ wo “Doez_ pans) rao | cmos | v0 ‘DoR2_Da158) uo | o%0s [v0 ‘D0Rz 00116), wes cMos | v0 ‘D0R2 006] var | owos | vo ‘DbR2_Dati7] io cw0s [v0 ‘DoR2_Da(6o) 16 | ows | vo ‘DoRZ Dots) 0 | onos [v0 ‘DDR Daiei) 7 | oxos [wo ‘oR 09119), as | ows | v0 ‘D0a2 D962) ve | owos | vo DORZ DOI?) vas ons ‘oR Disa) 9 —_[ oros_[o- ‘bba2_0Q(20] pao [wos | vo ‘0082 09171 wae | ovos [v0 ‘bba2_0Q(23) nas [eos [v0 ‘B02 018) uae [os [v0 ‘bpa2_09122) ao [ens [70 ‘3082-09151 tae [owes [70 ‘bpe2_69123) aa [oes [V0 oR2_DgS.Ne]| was | Gwos [WO ooa2_batz4) ‘ceo | onos | v0 owe pas.nti) | 138 | owos_| vo ‘DOR? _baI25) Fao | 705 | VO. oR? Das.NI2]___| x39 | CHos_| WO ‘DoR2_bor26) wa | onos | v0 ‘DoR2 Dos Nis} | e40 | GHos | vo ‘DpR2_b0r271, #37 | oH0s_| vo (DoR2 Dos.Nie] [39 | cwos. | vo ‘Doaz_0gi23) We ors [v0 ‘D0a2-09S.Nis] [x7 | ows Wo ‘Dba OQi23) ea | CHS [40 ‘DoRZ_DgS.Né] [Ps | cnOs [Wo 19082 0913] was | aos | vo. 02 09s.) | 16 | cwos | vo “poaz-oais07 Fa | on0s [V0 ‘Doa2_D9s.F0]__|wa7 | Gwos[ WO- ‘B0R2_69131] ee [ers [v0 oR2.09s.Ain | 37 | owes [wo ‘boa 09132) Ki | oH0s_| v0. ‘DowDas.Fi2] | Keo | CHos| v0 ‘DoR2_Do133) 32 | onos_| 10 Dow Dos. Fis] 39 | GHos| Wo ‘DDRZ_DOT34] HIS | oHOs [VO DORE DOS.Fal | 310] Gwos_| vo ‘oa2 00135), us| 9s | vo ora pes.ris)__| 17 | ovos_| vo ‘DORZ_DQI36] ‘Git__| Gnos_| v0 ‘DOR2_DQS_pf6]___| P6__| Cwos__| Wo ‘BbRa_ba137] ‘cio | oros [10 ‘Dow D9s.e(7] | us| cwos | woLand Listing| Table 4-1. Land Listing by Land Name (Sheet 9 of 29) Table 4-1. Land Listing by Land Name (Sheet 10 of 29) Lena wame | lan | Ber Torecon tana weme | fan? | Bue" or ecton RRA mr foros To LRN ae YT oka wats) x7 [ows |o rtowcowtay [easy fart fr DRI MALOT 17 [ows To ‘PL ORONS] java [ert ‘oR MAIN vas | eras fo ‘eLowowe] jae [ert 1 Dna ¥aL2] ea | ovas fo ‘@rLoRLONT] [arse errr ‘oR_MATS] Fis | ovos [To ‘@rLowe_oWe] ——}aveo [ort ‘R_MAiA] raf eras To ‘GPL DRLONG] TAD @T—T ‘oka Malis) cas ovos [o erLowomal jars _fant |r RMA] eis oras To ‘LRL_bmA] TAUB [QT “oR2_ata} s0 [eos [o Fertomconioy faves fer fr] ‘RE_MALe] 20 | eros fo ‘prLowonin] fares [art ‘oR_MALS] x23 | nos fo ‘prioweoacial | arao [art BRE_MAIG] az [ores [To ‘grLowoAtia] Jamz [@rt—T oka MA ina ows [0 erLomconied jane [art |r BRE_MATS] Tas [eras fo “GPLORLOAS] | aneo [QP ‘R2_MAlS] a2 | ovos fo ‘erLoweonie) fanaa [ert | ‘{DoR2_oDTIo} ts | ovos Jo wLpRK_p>I7} apar [ort | ‘968200711 3 | wos fo ‘wrLowLone] jaws [ert ‘oRE_DOT] bis [eras fo ‘wr ow_oAIs] arse [art T ‘oR2_00713) 10 | emos [fo eoromonal jane [arr |r DORE EASE Dir fews fo ‘grLowLbAa] | aNa5 [errr ona. RESET? ez faws fo ‘@rLomconal jase [errr oom wee eie—fows fo ‘rome ons] [awa7_[ort—[r Fens a ‘rome ore) [rae [arr EBGE a aes YT ‘LORCA _—[Ase_[ aT ect vos [sey | 70 omcorie)——|awan [an fr ca ei fen yo TeLomcons|_——[aueo [arr eae ea —fon ft ‘qroncomoy—avoe [arr [o PROCHGTE meas fore [70 ‘eproncontiy ——[acas fart fo wie arr on0s fo ‘Lon owioy jars arto PLEURC BN Takada] “LOT OMT] ABT [OR] O aricumcor—arat_|an | economia) jacer for |o PLcURD_ON area [ano “PLONCOMIs]——] aH [eno wieumor acer fan fo ‘@Loncontie) | A029" [ero PicHrio) Aa [asp ‘LOM oMis) | aca [ert [0 iow ono aT “LON oMtie) jaca [orto @omCoNL) Asef a] “@LOMCOMI7) jase [ero qpronxcontio)—aez_| an | ewroncowie) jase ar |o GPLORCONITT] aR [OT “Lon oMis] | AMO aro Low owti2)——anao [art ‘LOMO jae foro ‘[QPI_DRX_DNI13) naz opt | 1 J ‘[QPL_DX_ONI3I 9 ort fo 7 PL_ORCOWLIa] awe AT [ LRLONTis) Awa —[T BLONDE] AeA TO] O qpromcontie) amet [aa |t wLonconte) jana [ger |o LORENA A] a PORN ONLIB) ave | HT ‘wLoncowal janes ferro @piomcontis)—yatsa [art ‘eLoncons) jase ferro cerca) aaron [1 ‘eon oro] faassen [0Table 4-1. Land Listing by Land Name (Sheet 11 of 29) and tisting Table 4-1. Land Listing by Land Name (Sheet 12 of 2) tana name | 4804 | Buffer] oirection tana name | 604 | Buffer oirection ne | wor | Type gr pre DALAT a5 _[ an] o avo a ‘gripe pe(ia) [aris _| gro sv. Fe ‘QrLppc pala) asa gato av 7S griopcpats2) aoa | gr_|o sv. ca ‘QrLppc oats) [aces _| ger o avo = ‘@roncpe(se) | aoao | ger fo Rsv ci ‘Flor etis) | acsi_| get | 0 sv 8 ‘QPl_prx patie) | Ac38_| ae | 0 vo. nas ‘OFLDrx DALIT! ABBB_| aero RSV oo ‘orton patie) | 4038 | art | 0 vo. os ‘QPL_DDXpA(I8]__ | Ae#O | QeI__| 0 SVD. De ‘9P1_0PxD(2) 737 | ant | 0 sv ” ‘QPL BKC BALa) Rie [ aero vO cs (Qp_Dr BLA] ‘anao [get [0 vo. we aeao_[ aero avo oo ‘9F1_prx pete) aua_|ae_|o avo. var ‘OF Dx DFT) axez_[ art | 0 RSV maz ‘oF ox oFI8) 23 [an | 0 vO He ‘9P_DPxDFI3) ‘c40_| ae] 0 Sv 9 RESET 429 | Aeyr [T sv. 5 RSV Das BVO H vO. be svo. a vO 6 Sv ar SVD. 3 vO. 5s RVD on RVD a7 vO @? vo. a Rsv 182 avo P36 vO. ra vO. a7, RVD 2 Rv ae Rv. 0 sv. Fe RVD. BT vO. # Rv 0 vO nSLand Listing| Table 4-1. Land Listing by Land Name (Sheet 13 of 29) = Table 4-1. Land Listing by Land Name (Sheet 14 of 29) Landname | a2 Y Balter orecton Lanaame | '822 [Bae orecion LRsvo BS RSVO_ ABEL BSD ro 150 AE ASD 20 150 net aD ee sv es ASD es v0 7 FD 7s SVD st [Rsvo oe RSD AF2. oo we SVD ar a0 oe nso ace TE a 7500 mG ASD a sv0 nce asi e V0 AG? AS in 15V0 ar BSD rar 1510 ae LRSvO. 25 RSVD_ AKL TED ra Sv TAR ro ist so Ae ASD eo n5v0 nee asi 7s S00 ne aS ce 1SV0 AD ASD ce 1510 Ae a0 act v0 Aa asi Abi v0 Aa ao aD 7500 Aa a0 03 50 As zle Table 4-1. Land Listing by Land Name (Sheet 15 of 29) and tisting Table 4-1. Land Listing by Land Name (Sheet 16 of 29) tana name | 4804 | Buffer] oirection tana name | 604 | Buffer oirection ne | wor | ype vO a8 avo 9 vO. au Sv. we Rv aN Rv ao Rv. Ande. vO. aval SVD. 2x38 vO. od RVD ane Sv NE ‘vO aN vO. 833 Sv rl vo baa SVD. ro SVD. BAS vO ARL vO BA? RVD R36 vO BAe REVO. 237 vO. Gr RVD oo BVO Gz Rsv. 185 vo. 0 vO Aus sv. 29, SVD. au? vO. us RVD Aus SVD vit vO av vO vai Rsv aT THERNTRIPe asx7_[on__|o vO. ae 1S as10_| aT RVD ANT Taste an9_—[ tar] T Rv. Ana. vee anui_| PUR RVD. ‘AND vec ‘aH33_[ PUR Rv ane vec an PURLand Listing| Table 4-1. Land Listing by Land Name (Sheet 17 of 29) = Table 4-1. Land Listing by Land Name (Sheet 18 of 29) Landname | a2 Y Balter orecton Lanaame | '822 [Bae orecion (vec aki | PWR ver Ani6 | PWR vec Kia PR wee ai POR vec Kia | vee ais | wR vec kis [rn vee aa Pw vee air vee ae vec rai Wee Tas [PW (vec: AKi9 | PWR, ver |AN27_| PWR vec reat | aa ve ar [ran | Bee [oan ee aR Wee eis vec as Pk vee ais | Pw vec alia [pe Woe ne | vee aaa [rw vee ania Pw vec rae PR Wee aR | POR (vec: Ami2 | PWR, vec ARIS | PWR, ee aia vee aie [PO vec mis” | Pk vee aie | vec ais [Pn vee ano | PR vee ais Wee fat vee ana vee az? [PR vec as [rk vee aad | PR vec aor [ rk vee ae Pw vee aoa vee ai ee 70 Wee TARP vec “aai_| pwr ver An34 | PWRle Table 4-1. Land Listing by Land Name (Sheet 19 of 29) and tisting Table 4-1. Land Listing by Land Name (Sheet 20 of 2) tana name | 4804 | Buffer] oirection tana name | 604 | Buffer oirection ne | wo. | ype vec ‘4n7 | Pu vec ‘aw2i_| PUR vee 4728 | Pu vec ‘za _| PR Vee ‘190—| PUR vec ‘25 | PR vec arai_| pwr vec fawz7_| PR Vee ara | PR vec ‘28 _| PR vec ara | ue vec ‘v0 | PR vec 00 | Pu vec iss | ik vec auia_| pwr vec awe __| PUR Ver ‘AUIS | Pu vec ‘vio | PUR vee ‘aui6 | PR vec wiz | PUR vee auie_| PR vec aia [ PUR vee ‘x09 | vec ais | PUR vee ‘xuai_| PR vec Avie | PUR vec u2e_| Pun vec aig | Pu vec avis_| pur vec aio _| pum Vee ‘Avi6_| PUR vec BAI2 | Pu vec avis | PUR vec BAL [Pu vec avio_| PUR vec Bais | PUR vec ‘5030 _| PUR vec a27 | Pu vec ‘AvSI_| PUR vec Ba28 | PUR Vee a PR vec BA00 | PUR vec aoa_| Pur vec cao [Pu Vee 09 | vec wi [Pa vec ‘aw | PR vec wis [Paens (intel) Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 21 of 29) (Sheet 22 of 29) Landname | a2 Y Balter orecton Lana ame | §822 [Bae orecion vee was oe 050 aa a vec sia__| ron vo0a ir | rw vec war [rw 950 saz Pw vec was |r 900 ‘oz? rwe vec as [rn 900 vas ra vee waar W950 a0 vec wai [a 508) 75 | Pam ver 33 | pwr vooq 8 Pwr vec wit [oe W958 323 wee nas | rw ‘000 sos ver fur [rw yo00 vas rm wee [wn 000 ‘arf rim ee supe oo0 vas im ver 33 | Pwr YOOQ us Pw ee wit pr 550 cpr vec SENSE aro | ane 908 arf ram ecru sow W950 ot? Pa Yeon was [oe 000 v7 Teor wasp ve asioeay PALI ons ‘ecrimcooo an? | yc | iiimsiort} ais |omos | 0 “Worinen0o ake sync | ‘tzinsiors) Tavs fons 6 ‘000 wot [re wisyescro) amo enos [00 900 wis rn vnoisyescriy—[anzo | onos [00 900 fat voisyescis} fon | enos | 10 558 “as rin Ie) ee [eas fo 508 no | pn voir) ave | coos | 509 aio 1 75 oho 09 a7 [oe vs '39 | cho vq azo vss aa — fon v0 a7 [ron vss Asi | ew v0 [rR 135 rs | GW [yoo e PWR VSS Asa | GND. 90 ext r 155 comic v0 eis |r 58 rome v0 eo [rn 155 isso | ev v0 asf 158 ao ev eo ctr 155 a5 | cho oo ors | rw 13s not | cho 0 ier 138 now v0 bat | rw ¥38 AB | ew v0 ba [ron v58 87 | ew v0 eur 58 ct | ev TD ier v5 GG ‘yoo Je PWR vss Acs | GND 000 eo 135 or ao Sioa ve ram ass ooh 000 mia rn vss oti | oko 00 iar vss 033 | ohle Table 4-1. Land Listing by Land Name (Sheet 23 of 29) and tisting Table 4-1. Land Listing by Land Name (Sheet 24 of 29) tana name | 4804 | Buffer] oirection tana name | 604 | Buffer oirection ne | wow | ype vss ‘635_| GHD vss aonti_| GND vss ‘698 | GN vss ‘anita | GND vss ‘AFA | GHD ves ‘17 | GND vss ass | Guo vss 20_| GN vss. ‘AGI1_| GND- ves ‘a0i22_| GND vss x63 [GND ves 023 | GND ves 63 | GND ves ‘129 |'GNO- vss ant | Gn vss a005_| GN vss ‘ax34_[ GND ves ‘9137 | GND vss ‘5137 | GND ves ‘909 | GND vss. ‘H99_| GND vss. ans_| GND vss ‘5A? [GND ves ‘9 | GND ves 234 | GH ves ‘anit_| GND vss 36_| Gn vss ania_|'cno- vss ca2_| Guo vss an? | cn vss. ‘ax38_| GND. vss ‘51 —| GND. vss ‘5x39 | GND vss 610 | GND vss. ‘x83_| GND vss. ‘apii_| GND vss ‘a2 | GN vss 3926 _| GND vss ‘AL20—| GNO- vss 929 | GND vss ‘Ala | GND ves ‘ara | GND vss ‘a23_| Gn vss 925 _| GN Ves ‘Lae | GND- ves 2936 | GND vss ‘129 | GNO- ves 3937 | GNDLand Listing| Table 4-1. Land Listing by Land Name (Sheet 25 of 29) (intel Table 4-1. Land Listing by Land Name (Sheet 26 of 29) Landname | a2 Y Balter orecton Lanaame | '822 [Bae orecion vss 5 | ex vss ves | ev 185 are | ev ¥38 vat | ew 185 anti | ev ¥38 vas | ew 85 aris | ov v58 avaa| ev v5 ani? | ov 58 aaa ev 8 ara GND v5 wit |e vss. “nao _| GND vss ‘Avai_| GND. 3 Raa oN 155 wane vss. “na2_| GND vss ‘Aw22_| GND. 3 ara ov 155 wae vs anao | ov 155 Aas | ew ws writ | ov v5 wn9 | ev 185 aro | ov vss 109 | ew 18 alr] ev 135 2 | GW Lyss Auri_| GND vss Av37_| GND. 1 avis ov 155 rad GH ve fui | ev 58 wi? | ew vs vad | ev 155 = few 3 ua ov 158 a7} ew 18 ais ov 138 Bais ew 185 aus | ev ¥38 ai? | ew 8 Avis | ovo vss 320 | ew v5 Ase | ov vss are 600 1 ADEE GND 15 309 ew vss. aus | Gno ‘vss ena | GND zce Table 4-1. Land Listing by Land Name (Sheet 27 of 29) and tisting Table 4-1. Land Listing by Land Name (Sheet 28 of 2) tana name | 4804 | Buffer] oirection tana name | 604 | Buffer oirection ne | wow | ype vss Das | GND vss 28 | GD vss een vss na | Nb vss xen ves waz | BND. vss 6 | ono vss na7_| ono, vss. esi nb ves Naz GND, vss [ono ves woo ves ra [ oo ves nas ono, vss re [eno vss ns | eno vss [en ves PT | Nb, vss ‘era | GN ves ra | en vss. ‘ez __[ Gn vss. Fa [ Nb, vss ‘G32 | GND ves 738 | GND ves ‘Ga? | Gn ves 73 | GND vss ‘e2_| eno vss re [ono vss se | cn vss ur | ow vss. xi 6nb vss ‘wid—| GNO- vss Kit 6ND vss vas [GN vss. Wa 6nd vss. ‘vea_| GNO- vss Ge enb vss vi [6x0 vss te [en vss ya [eno vss end ves yaa eno vss m2 | eno vss ye | ono Ves wit [ Cn ves vat [ eno vss is —| cn ves ye [cnLand Listing| Table 4-1. Land Listing by Land Name (Sheet 29 of 29) Lena wame | lan | Ble" Torecion RSE Tt — a ss sense VIF AES? | Aniog WF SENSE E36 [soe Wir v2 ma [ows | WF D9 a7 [ows [0 Weve ave — ows To va mio aR vin eso | am vin est [Pa vin fcae_| Pan ani aR vr ‘aii am vr aaa [ Pam vr. 035 [ram v7 m036 [aR iro ADs | PWR vr mest aR vm E35 [am vr. ree — [Pam es [ am vr are — [a vm ars [ram VITPRGOOS 035 [ Aer’ [7and tisting Table 4-2. Land Listing by Land Number _‘Table 4-2. Land Listing by Land Number (Sheet 1 of 295, (Sheet 2 of 29} Ge] pm veme | 85 orecvon ese] vimame | Ser ovacton a0 | BOREAS] | owOS TO mer |W Pa ‘ast | vooa ran Fav 75 BORO RISE ros [0 vr mR 7i6 | BDRO_ BATT ios fo wo ay ‘ai? BOR2-BALOT wos [0 TPES Raye ‘ib DOR HAO] wos fo om_DOts) eves [16 Ai9 | VOOR or ss oo ‘a0 | o5Ro af] eves [6 erLoncowtiny foro at VOOR aR ‘arLoncpti7] Tero 725 | boR0 a7] os |e 35 exo. ‘a6 | bowo_yatit] | ewos | 0 Wes oo 727 RSV conto ag ‘as [oono-vatiay | ovo To vss eo i23__| voog Pan QoL BCONTS]— foro 30 boro CT ros 10 FSV at) RSV Rsv a5 [VS5 oo vss ae ae RSV vrio Pan 7a RSV wre Pan zan_| powo_pataei | ews | wo ‘oR COMPRA — | eg aS wo man ma ao wn 7 BPTI on 1 wre ma aT woROLeETE] [evo To ro Par a bowi-csels] [ews [0 ss oo 73 | von a oR ERT or] Axio VO | ik gruonconiisy far fo ARSE LV or {er onc pete) | er aaa vSs oo wens maar VAD a Acad | gPLERLBWR] |S aaa | VSS oo cai jgnoncortis) [at |o A435 | 0DAI_BaLAL ros | 1 ca2-| QB DALLA]_—_| >I 0 naa6 | DDR DaL eros {1 aca [ron prin] | ato 7837 | BDRI_DaLOL ros [1 es 55 oo aaa | VSS wo gs | RSV Aa39 [VS wo. nS ao ‘ae [cL P_BW cos fo ca _| RSV anal | RSV abt RSV WAS [BOR TTD BOTS ‘oi | vr od ‘as | voppwrcoo0 | sey | 1 ott [VSS oo ‘a7 ooRi paisa] [ows [0 ADE | RSV ‘aa Dom cONP(O) [mal 1n03|RSVD nas | V55 xo maT [WSS aw A810") Pa A034 PanLand Uisting| Toble 42. Land isting by Land Number Table 4-2. Land isting by Land Number (Sheet 3 of 29) (Sheet 4 of 295, 7 Ty Taal ar sa] rmname | 38°] ovecon Gaz] _rnname | SH] oven basses 7 as BEAT fer To pose | ran fe [eo fest Las iD Aaa op OTN] — Taw —T6 rose [eer oTconTy fen —[6 ft as oo feos [arLoncontie) [err [0 seer econ ov — [ant fo fer Tree fs cane aay — [art To fei oR OTE] —Tw—T6 fs es oo [aoa GND. ‘Af6 | RSVD 7a ets ft werte ae aa fe wr in| ies a wre om fee Pa a fain 7 mas ve = i eo ies moor oh = = fase wxcam oma—fort fo = = eae eam oui) [art i rab fet [ao ae fae ie] wR — aT iam arte aus qrancows) [ant [0 = a ica eco — Te = wmfe aa ‘eat [opLoricomin) —terrf6 fess t fear [opLOTCOMTN] Terr 16 arf (A643 | OPI_OTX_ONTI0] ori fo ‘#68 _| RSV et as a fe ae af oe fase aa ane ao fas 3 a a wae oar oon fos [we am fair i arf 7 fez [Rav fos f eco eros [1 tae fe | ee ‘eek V8 are 7 are ae ea “4 tos | gr ane ow) [grt 0 a xo mrp oo} Hew bar = ase pase t rear | wo rn fino eouane oa — [ort fer fs 3 fan econ onal — [ort Te Datasheet 2ce Table 4-2. Land Listing by Land Number (Sheet § of 29) and sting Table 4-2. Land Listing by Land Number (Sheet 6 of 28) tang] pinwame | 887] oirection tare] pinwame | S84] oirection Wo ype! wo. Type ‘asia | QOD oN) gr_|0 wear | er Pan ‘ais | QP_pDoMe] | ger fo ‘naa | ver Pa Bas FANS nas | VSS AO ‘ano TRSTe mae fT ‘aKa? | VSS ‘SRO. ‘ant | RsvO ‘a | Vee Pw AO] 700. mw Io aie | VSS NO. jan | vec Pa a5 | RSV ‘aia RSV ‘a6 [SVD ‘ni RSVO ‘a7 [arom pray ar |S 833. Ver Pai ‘Naa [QPLOMX ON] | aro ia | VES ND ae | VSS eNO 5 | BaLRDF ‘onos [T ‘ace RSV ‘rae | vss xo. ‘akeo | aPi_orx.peis) | aet_|o x7 | RSV ‘KEI OPL_OT DNS] >" | ‘a8 | OP ODA] aAT—|O ‘kez [OPL_OTX DRI] |r| 0 ‘8B9_| QPL_DMXDNES] | aPr_| 0 Kes [VSS AO. ‘aM [RVD aes [RSV a Ke SVD ‘aut | vss eno. ‘nx | RSV. ‘aw2| Qn_DDN] | ger_1 0 Ks) SENSE Tag [T [aus [an_onconal [at fo ‘ao | vss exo 6) RSV ‘ania | vipjoysibio] | cvos_| 170 KiB | vec Pa fue | vee ‘Aka | VSS ND ‘Li vec ‘KIB | Vee Pa ‘aa [vss Kis | VEC Pa ‘20_ | vss AKI? | VSS ND. fai vee ‘AKI | Ver Paik naa [vss ‘Anis | vec Pa. ‘aaa | vss ‘neal | vee Pm 126 | vss ake | VSS nD fa? vee ARE | VSS ND alae] Vee ‘as | vec Pa 12a | vss aS | VEE Pa aL RSVS a6 | VSS RO ast vee Pa Datasheet