library ieee;

use ieee.std_logic_1164.all;
entity GPIO is
port(reset,clk,ent:in std_logic;
s: out std_logic;
z: out std_logic_vector(6 downto 0);
cont : inout integer range 0 to 9
);
end GPIO;
architecture contador of GPIO is
signal t_tmp : std_logic ;
signal NK : std_logic ;
signal contador : integer range 0 to 999999999 := 0 ;
signal pulso: std_logic :='0';
begin
process (clk,reset,ent)ivs
begin

if(rising_edge(clk))then
if(contador= 12500000)then
pulso <=not(pulso);
contador <=0;
else
contador <= contador+1;
end if;
end if;
NK <= pulso;
s<= NK;

if(NK' event and NK='1')then

if(reset='1')then
if(ent='1')then
cont <=cont+1;

case cont is
when 0 => f<="0000001"; --0
when 1 => f<="1001111"; --1
when 2 => f<="0010010"; --2
when 3 => f<="0000110"; --3
when 4 => f<="1001100"; --4
when 5 => f<="0100100"; --5
when 6 => f<="0100000"; --5
when 7 => f<="0001101";
when 8 => f<="0000000";
when 9 => f<="0000100";
when others => f<="1111111";
end case;

if(cont=9)then
cont <=0;
end if;
else
cont<=cont;
end if;
else

cont<=0;
end if;
end if;
end process;
end architecture;