Tda8929t PDF

INTEGRATED CIRCUITS
DATA SHEET
TDA8929T
Controller class-D audio amplifier
Preliminary specification 2001 Dec 11
File under Integrated Circuits, IC01
Philips Semiconductors Preliminary specification
Controller class-D audio amplifier TDA8929T
CONTENTS 15 TEST AND APPLICATION INFORMATION

15.1 Test circuit
1 FEATURES
15.2 BTL application
2 APPLICATIONS 15.3 Mode pin
3 GENERAL DESCRIPTION 15.4 External clock
15.5 Reference designs
4 ORDERING INFORMATION
15.6 Reference design bill of material
5 QUICK REFERENCE DATA 15.7 Curves measured in reference design
6 BLOCK DIAGRAM 16 PACKAGE OUTLINE
7 PINNING 17 SOLDERING
8 FUNCTIONAL DESCRIPTION 17.1 Introduction to soldering surface mount
8.1 Controller packages
8.2 Pulse width modulation frequency 17.2 Reflow soldering
8.3 Protections 17.3 Wave soldering
8.3.1 Diagnostic temperature 17.4 Manual soldering
8.3.2 Diagnostic current 17.5 Suitability of surface mount IC packages for
8.3.3 Start-up safety test wave and reflow soldering methods
8.4 Differential audio inputs 18 DATA SHEET STATUS
9 LIMITING VALUES 19 DEFINITIONS
10 THERMAL CHARACTERISTICS 20 DISCLAIMERS
11 QUALITY SPECIFICATION
12 DC CHARACTERISTICS
13 AC CHARACTERISTICS
14 SWITCHING CHARACTERISTICS
14.1 Minimum pulse width
2001 Dec 11 2
1 FEATURES 3 GENERAL DESCRIPTION

• Operating voltage from ±15 to ±30 V The TDA8929T is the controller of a two-chip set for a high
• Very low quiescent current efficiency class-D audio power amplifier system. The
system is divided into two chips:
• Low distortion
• TDA8929T; the analog controller chip in a SO24
• Fixed gain of 30 dB Single-Ended (SE) or 36 dB
package
Bridge-Tied Load (BTL)
• TDA8926J/ST/TH or TDA8927J/ST/TH; a digital power
• Good ripple rejection
stage in a DBS17P, RDBS17P or HSOP24 power
• Internal switching frequency can be overruled by an package.
external clock
With this chip set a compact 2 × 50 W or 2 × 100 W audio
• No switch-on or switch-off plop noise amplifier system can be built, operating with high efficiency
• Diagnostic input for short-circuit and temperature and very low dissipation. No heatsink is required, or
protection depending on supply voltage and load, a very small one.
• Usable as a stereo Single-Ended (SE) amplifier or as a The system operates over a wide supply voltage range
mono amplifier in Bridge-Tied Load (BTL) from ±15 up to ±30 V and consumes a very low quiescent
current.
• Start-up safety test, to protect for short-circuits at the
output of the power stage to supply lines
• Electrostatic discharge protection (pin to pin).
2 APPLICATIONS
• Television sets
• Home-sound sets
• Multimedia systems
• All mains fed audio systems
• Car audio (boosters).
4 ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
TDA8929T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
2001 Dec 11 3
5 QUICK REFERENCE DATA
SYMBOL PARAMETER MIN. TYP. MAX. UNIT

General; note 1
VP supply voltage ±15 ±25 ±30 V
Iq(tot) total quiescent current − 20 30 mA
Stereo single-ended configuration
Gv(cl) closed-loop voltage gain 29 30 31 dB
Zi input impedance 45 68 − kΩ
Vn(o) noise output voltage − 220 400 µV
SVRR supply voltage ripple rejection 40 50 − dB
αcs channel separation − 70 − dB
VOO DC output offset voltage − − 150 mV
Mono bridge-tied load configuration
Vn(o) noise output voltage − 280 − µV
SVRR supply voltage ripple rejection − 44 − dB
VOO DC output offset voltage − − 200 mV
Note
1. VP = ±25 V.
2001 Dec 11 4
6 BLOCK DIAGRAM
handbook, full pagewidth VSS1 VDD1
1 3
R fb
20
PWM1
4 WINDOW
IN1−
COMPARATOR 21
V/I EN1
5
IN1+
24
2 SW1
mute
SGND1
SGND 23
SGND REL1
7 SGND
OSC OSCILLATOR 19
STABILIZER STAB
15
mute MANAGER DIAGTMP
22
DIAGCUR
6
MODE MODE
SGND TDA8929T
16
EN2
SGND
SGND
11
SGND2 mute 13
SW2
8
IN2+
V/I 14
9 WINDOW REL2
IN2− COMPARATOR
17
PWM2
R fb
12 10 18
MGW148
VSS2(sub) VDD2 VSSD
Fig.1 Block diagram.
2001 Dec 11 5
7 PINNING
SYMBOL PIN DESCRIPTION

VSS1 1 negative analog supply voltage
channel 1
SGND1 2 signal ground channel 1 handbook, halfpage
VSS1 1 24 SW1
VDD1 3 positive analog supply voltage
channel 1 SGND1 2 23 REL1
IN1− 4 negative audio input channel 1 VDD1 3 22 DIAGCUR
IN1+ 5 positive audio input channel 1
IN1− 4 21 EN1
MODE 6 mode select input
IN1+ 5 20 PWM1
(standby/mute/operating)
OSC 7 oscillator frequency adjustment, or MODE 6 19 STAB
TDA8929T
tracking input OSC 7 18 VSSD
IN2+ 8 positive audio input channel 2 IN2+ 8 17 PWM2
IN2− 9 negative audio input channel 2
IN2− 9 16 EN2
VDD2 10 positive analog supply voltage
channel 2 VDD2 10 15 DIAGTMP
SGND2 11 signal ground channel 2 SGND2 11 14 REL2
VSS2(sub) 12 negative analog supply voltage VSS2(sub) 12 13 SW2

channel 2 (substrate)
MGW149
SW2 13 digital switch output channel 2
REL2 14 digital control input channel 2
DIAGTMP 15 digital input for temperature limit
error report from power stage
EN2 16 digital control output for enable
Fig.2 Pin configuration.
channel 2 of power stage
PWM2 17 input for feedback from PWM
output power stage channel 2
VSSD 18 negative digital supply voltage;
reference for digital interface to
power stage
STAB 19 pin for a decoupling capacitor for
internal stabilizer
PWM1 20 input for feedback from PWM
output power stage channel 1
EN1 21 digital control output for enable
channel 1 of power stage
DIAGCUR 22 digital input for current error report
from power stage
REL1 23 digital control input channel 1
SW1 24 digital switch output channel 1
2001 Dec 11 6
8 FUNCTIONAL DESCRIPTION The amplifier system can be switched in three operating

modes via the mode select pin:
The combination of the TDA8926J and the TDA8929T
produces a two-channel audio power amplifier system • Standby: with a very low supply current
using the class-D technology (see Fig.4). • Mute: the amplifiers are operational, but the audio signal
at the output is suppressed
In the TDA8929T controller device the analog audio input
signal is converted into a digital Pulse Width Modulation • On: amplifier fully operational with output signal.
(PWM) signal. The digital power stage (TDA8926) is used
for driving the low-pass filter and the loudspeaker load. It For suppressing pop noise the amplifier will remain
performs a level shift from the low-power digital automatically for approximately 220 ms in the mute mode
PWM signal, at logic levels, to a high-power PWM signal before switching to operating mode. In this time the
that switches between the main supply lines. coupling capacitors at the input are fully charged.
A second-order low-pass filter converts the PWM signal
into an analog audio signal across the loudspeaker. Figure 3 shows an example of a switching circuit for driving
pin MODE.
For a description of the power stage see the specification
of the TDA8926.
The TDA8926 can be used for an output power of
2 × 50 W. The TDA8927 should be used for a higher
+5 V
output power of 2 × 100 W. handbook, halfpage
standby/ mute/on
mute
8.1 Controller
R
The controller contains (for two audio channels) two Pulse
Width Modulators (PWMs), two analog feedback loops MODE
and two differential input stages. This chip also contains
R
circuits common to both channels such as the oscillator, all
reference sources, the mode functionality and a digital SGND
MGW150
timing manager.
The pinning of the TDA8929T and the power stage devices Fig.3 Mode select switch circuitry.
are designed to have very short and straight connections
between the packages. For optimum performance the
interconnections between the packages must be as short
as possible.
Using this two-chip set an audio system with two
independent amplifier channels with high output power,
high efficiency (90%) for the system, low distortion and a
low quiescent current is obtained. The amplifiers channels
can be connected in the following configurations:
• Mono Bridge-Tied Load (BTL) amplifier
• Stereo Single-Ended (SE) amplifier.
2001 Dec 11 7
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2001 Dec 11
Philips Semiconductors
VDDA
VSSA VDDA VDDD
+25 V
VSS1 VDD1 VDD2 VDD1
1 3 13 5
R fb TDA8926J 6 BOOT1
TDA8929T 20 PWM1
IN1− 4
23 REL1 REL1 2 DRIVER
Vi(1) INPUT PWM HIGH
STAGE 24 SW1 SW1 1 CONTROL
MODULATOR 7
IN1+ 5 AND
21 EN1 EN1 4 HANDSHAKE OUT1
DRIVER
SGND1 2 LOW
mute 19 STAB
STABI
STAB 9
SGND
22 VSS1
ROSC DIAGCUR
VSSA OSC 7
OSCILLATOR MANAGER 15 DIAGTMP TEMPERATURE SENSOR
AND
DIAG 3 VDD2
CURRENT PROTECTION
MODE 6
VMODE MODE 12 BOOT2
8
POWERUP 15
SGND
SGND2 11
mute 16 EN2 EN2 14 DRIVER SGND
IN2+ 8 HIGH (0 V)
CONTROL
13 SW2 SW2 17 11 OUT2
AND
Vi(2) INPUT PWM HANDSHAKE
STAGE MODULATOR 14 REL2 REL2 16 DRIVER
IN2− 9 LOW
17 PWM2
R fb
12 10 18 8 10
VSS2(sub) VDD2 VSSD VSS1 VSS2
VSSA VDDA
−25 V
Preliminary specification
VSSD
VSSA
MGU387
handbook, full pagewidth
TDA8929T
Fig.4 Typical application schematic of the class-D system using TDA8929T and the TDA8926J.
8.2 Pulse width modulation frequency 8.3.2 DIAGNOSTIC CURRENT

The output signal of the power stage is a PWM signal with This input is intended to protect against short-circuits
a carrier frequency of approximately 300 kHz. Using a across the loudspeaker load. In the event that the current
second-order LC demodulation filter in the application limit in the power stage is exceeded, pin DIAGCUR must
results in an analog audio signal across the loudspeaker. be pulled to a LOW level. A LOW level on the diagnostic
This switching frequency is fixed by an external resistor current input will immediately force the output pins EN1
ROSC connected between pin OSC and VSS. With the and EN2 to a LOW level. The power stage will shut down
resistor value given in the application diagram, the carrier within less than 1 µs and the high current is switched off.
frequency is typical 317 kHz. The carrier frequency can be In this state the dissipation is very low. Every 220 ms the
9 controller will attempt to restart the system. If there is still
9 × 10
calculated using: f osc = ------------------- [Hz] a short-circuit across the loudspeaker load, the system is
R OSC
switched off again as soon as the maximum current is
If two or more class-D systems are used in the same audio exceeded. The average dissipation will be low because of
application, it is advised to have all devices working at the this low duty factor. The actual current limiting value is set
same switching frequency. This can be realized by by the power stage.
connecting all OSC pins together and feed them from an Depending on the type of power stage which is used,
external oscillator. Using an external oscillator it is several values are possible:
necessary to force pin OSC to a DC-level above SGND for
• TDA8926TH: limit value can be externally adjusted with
switching from the internal to an external oscillator. In this
a resistor; maximum is 5 A
case the internal oscillator is disabled and the PWM will
switch on the external frequency. The frequency range of • TDA8927TH: limit value can be externally adjusted with
the external oscillator must be in the range as specified in a resistor; maximum is 7.5 A
the switching characteristics. • TDA8926J and TDA8926ST: limit value is fixed at 5 A
Application in a practical circuit: • TDA8927J and TDA8927ST: limit value is fixed at 7.5 A.
• Internal oscillator: ROSC connected between pin OSC
and VSS
• External oscillator: connect oscillator signal between
pin OSC and pin SGND; delete ROSC.
8.3 Protections
The controller is provided with two diagnostic inputs. One
or both pins can be connected to the diagnostic output of
one or more power stages.
8.3.1 DIAGNOSTIC TEMPERATURE

A LOW level on pin DIAGTMP will immediately force both
pins EN1 and EN2 to a LOW level. The power stage shuts
down and the temperature is expected to drop. If
pin DIAGTMP goes HIGH, pins EN1 and EN2 will
immediately go HIGH and normal operation will be
maintained.
Temperature hysteresis, a delay before enabling the
system again, is arranged in the power stage. Internally
there is a pull-up resistance to 5 V at the diagnostic input
of the controller. Because the diagnostic output of the
power stage is an open-drain output, diagnostic lines can
be connected together (wired-OR). It should be noted that
the TDA8929T itself has no temperature protection.
2001 Dec 11 9
8.3.3 START-UP SAFETY TEST 8.4 Differential audio inputs

During the start-up sequence, when pin MODE is switched For a high common mode rejection and a maximum
from standby to mute, the condition at the output terminals flexibility of application, the audio inputs are fully
of the power stage are checked. These are the same lines differential. By connecting the inputs anti-parallel the
as the feedback inputs of the controller. In the event of a phase of one of the channels is inverted, so that a load can
short-circuit of one of the output terminals to VDD or VSS be connected between the two output filters. In this case
the start-up procedure is interrupted and the system waits the system operates as a mono BTL amplifier (see Fig.5).
for non-shorted outputs. Because the test is done before
Also in the stereo single-ended configuration it is
enabling the power stages, no large currents will flow in the
recommended to connect the two differential inputs in
event of a short-circuit. This system protects against
anti-phase. This has advantages for the current handling
short-circuits at both sides of the output filter to both supply
of the power supply at low signal frequencies.
lines. When there is a short-circuit from the outputs of the
power stage to one of the supply lines, before the
demodulation filter, it will also be detected by the start-up
safety test. Practical use from this test feature can be
found in detection of short-circuits on the printed-circuit
board.
Remark: this test is only operational prior to or during the
start-up sequence, and not during normal operating.

TDA8929T
IN1 + REL1
OUT1
SW1
IN1 −
EN1
Vi
POWER
EN2 SGND
IN2 + STAGE
SW2
IN2 − REL2
OUT2
MGW185
CONTROLLER
Fig.5 Mono BTL application.
2001 Dec 11 10
9 LIMITING VALUES
In accordance with the Absolute Maximum Rate System (IEC 60134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VP supply voltage − ±30 V
VMODE(sw) mode select switch voltage referenced to SGND 0 5.5 V
Tstg storage temperature −55 +150 °C
Tamb ambient temperature −40 +85 °C
Tvj virtual junction temperature − 150 °C
Ves(HBM) electrostatic discharge note 1
voltage (HBM) all pins with respect to VDD (class A) −500 +500 V
all pins with respect to VSS (class A1) −1000 +1000 V
all pins with respect to GND (class B) −2500 +2500 V
all pins with respect to each other −2000 +2000 V
(class B)
Ves(MM) electrostatic discharge note 2
voltage (MM) all pins with respect to VDD (class A) −100 +100 V
all pins with respect to VSS (class B) −100 +100 V
all pins with respect to GND (class B) −300 +300 V
all pins with respect to each other −200 +200 V
(class B)
Notes
1. Human Body Model (HBM); Rs = 1500 Ω and C = 100 pF.
2. Machine Model (MM); Rs = 10 Ω; C = 200 pF and L = 0.75 µH.
10 THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) thermal resistance from junction to ambient in free air 65 K/W
11 QUALITY SPECIFICATION
In accordance with “SNW-FQ611-part D” if this device is used as an audio amplifier.
2001 Dec 11 11
12 DC CHARACTERISTICS
VP = ±25 V; Tamb = 25 °C; measured in Fig.10; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply
VP supply voltage note 1 ±15 ±25 ±30 V
Iq(tot) total quiescent current − 20 30 mA
Istb standby current VMODE = 0 V − 30 100 µA
Offset
VOO output offset voltage in system on and mute − − 150 mV
∆VOO delta output offset voltage in on ↔ mute − − 80 mV
system
Mode select input (pin MODE); see Figs 6, 7 and 8
VMODE input voltage note 2 0 − 5.5 V
IMODE input current VMODE = 5.5 V − − 1000 µA
Vth1+ positive threshold voltage 1 standby → mute; − 1.6 2.0 V
note 2
Vth1− negative threshold voltage 1 mute → standby; 0.8 1.0 − V
note 2
VMODE(hys1) hysteresis voltage 1 (Vth1+) − (Vth1−) − 600 − mV
Vth2+ positive threshold voltage 2 mute → on; − 3.8 4.0 V
note 2
Vth2− negative threshold voltage 2 on → mute; 3.0 3.2 − V
note 2
VMODE(hys2) hysteresis voltage 2 (Vth2+) − (Vth2−) − 600 − mV
Audio inputs (pins IN1+, IN1−, IN2+ and IN2−)
VI DC input voltage note 2 − 0 − V
Internal stabilizer (pin STAB)
VO(STAB) stabilizer output voltage mute and on; 11 13 15 V
note 3
ISTAB(max) maximum current on pin STAB mute and on 10 − − mA
Enable outputs (pins EN1 and EN2)
VOH HIGH-level output voltage referenced to VSS VSTAB − 1.6 VSTAB − 0.7 − V
VOL LOW-level output voltage referenced to VSS 0 − 0.8 V
Current diagnose input (pin DIAGCUR with internal pull-up resistance)
VIH HIGH-level input voltage no errors; note 3 − VSTAB − V
VIL LOW-level input voltage note 3 0 − 1.5 V
Rpu(int) internal pull-up resistance to − 12 − kΩ
internal digital supply
Temperature diagnose input (pin DIAGTMP with internal pull-up resistance)
VIH HIGH-level input voltage no errors; note 3 4 5.5 V
VIL LOW-level input voltage note 3 0 − 1.5 V
2001 Dec 11 12

Rpu(int) internal pull-up resistance to − 12 − kΩ
internal digital supply
Switch outputs (pins SW1 and SW2)
VOH HIGH-level output voltage note 3 VSTAB − 1.6 VSTAB − 0.7 − V
VOL LOW-level output voltage note 3 0 − 0.8 V
Control inputs (pins REL1 and REL2)
VIH HIGH-level input voltage note 3 10 − VSTAB V
VIL LOW-level input voltage note 3 0 − 2 V
Notes
1. The circuit is DC adjusted at VP = ±15 to ±30 V.
2. Referenced to SGND (0 V).
3. Referenced to VSS.
13 AC CHARACTERISTICS

Stereo single-ended application; note 1
THD total harmonic distortion Po = 1 W; note 2
fi = 1 kHz − 0.01 0.05 %
fi = 10 kHz − 0.1 − %
SVRR supply voltage ripple rejection on; fi = 100 Hz; note 3 − 55 − dB
on; fi = 1 kHz; note 3 40 50 − dB
mute; fi = 100 Hz; note 3 − 55 − dB
standby; fi = 100 Hz; note 3 − 80 − dB
Vn(o) noise output voltage on; Rs = 0 Ω; B = 22 Hz to 22 kHz − 220 400 µV
on; Rs = 10 kΩ; B = 22 Hz to 22 kHz − 230 − µV
mute; note 4 − 220 − µV
αcs channel separation Po = 10 W; Rs = 0 Ω − 70 − dB
∆Gv channel unbalance − − 1 dB
Vo output signal mute; Vi = Vi(max) = 1 V (RMS) − − 400 µV
CMRR common mode rejection ratio Vi = 1 V (RMS) − 75 − dB
Mono BTL application; note 5
THD total harmonic distortion Po = 1 W; note 2
fi = 1 kHz − 0.01 0.05 %
fi = 10 kHz − 0.1 − %
2001 Dec 11 13

SVRR supply voltage ripple rejection on; fi = 100 Hz; note 3 − 49 − dB
on; fi = 1 kHz; note 3 36 44 − dB
mute; fi = 100 Hz; note 3 − 49 − dB
standby; fi = 100 Hz; note 3 − 80 − dB
Vn(o) noise output voltage on; Rs = 0 Ω; B = 22 Hz to 22 kHz − 280 500 µV
on; Rs = 10 kΩ; B = 22 Hz to 22 kHz − 300 − µV
mute; note 4 − 280 − µV
Vo output signal mute; Vi = Vi(max) = 1 V (RMS) − − 500 µV
CMRR common mode rejection ratio Vi = 1 V (RMS) − 75 − dB
Notes
1. VP = ±25 V; fi = 1 kHz; Tamb = 25 °C; measured in Fig.10; unless otherwise specified.
2. THD is measured in a bandwidth of 22 Hz to 22 kHz. When distortion is measured using a low-order low-pass filter
a significantly higher value will be found, due to the switching frequency outside the audio band.
3. Vripple = Vripple(max) = 2 V (p-p); Rs = 0 Ω.
4. B = 22 Hz to 22 kHz and independent of Rs.
5. VP = ±25 V; fi = 1 kHz; Tamb = 25 °C; measured in reference design in Fig.12; unless otherwise specified.

on
mute
standby
Vth1− Vth1+ Vth2− Vth2+ VMODE
VMODE(hys1) VMODE(hys2) MGW334
Fig.6 Mode pin selection.
2001 Dec 11 14
handbook, full pagewidth audio
switching
VEN
VSTAB
VSS
VMODE
on
4V
mute
2V
standby
0 V (SGND)
110 ms >110 ms
MGW152
When switching from standby to mute there is a delay of 110 ms before the output starts switching. The audio signal is
available after the mode pin has been set to on, but not earlier than 220 ms after switching to mute.
Fig.7 Mode pin timing from standby to on via mute.
handbook, full pagewidth audio
switching
VEN
VSTAB
VSS
VMODE
on
4V
standby
0 V (SGND)
110 ms 110 ms
MGW151
When switching from standby to on there is a delay of 110 ms before the output starts switching.
After a second delay of 110 ms the audio signal is available.
Fig.8 Mode pin timing from standby to on.
2001 Dec 11 15
14 SWITCHING CHARACTERISTICS
VP = ±25 V; Tamb = 25 °C; measured in Fig.10; unless otherwise specified.

Switching frequency
fosc oscillator frequency ROSC = 30.0 kΩ 309 317 329 kHz
ROSC = 27 kΩ; − 360 − kHz
see Fig.12
fosc(r) oscillator frequency range note 1 210 − 600 kHz
VOSC maximum voltage at pin OSC frequency tracking − − SGND + 12 V
VOSC(trip) trip level at pin OSC for tracking frequency tracking − SGND + 2.5 − V
ftrack frequency range for tracking frequency tracking 200 − 600 kHz
VOSC(ext) voltage at pin OSC for tracking note 2 − 5 − V
Notes
1. Frequency set with ROSC, according to the formula in the functional description.
2. For tracking the external oscillator has to switch around SGND + 2.5 V with a minimum voltage of VOSC(ext).
14.1 Minimum pulse width

The minimum obtainable pulse width of the PWM output signal of a class-D system, sets the maximum output voltage
swing after the demodulation filter and also the maximum output power. Delays in the power stages are the main cause
for the minimum pulse width being not equal to zero. The TDA8926 and TDA8927 power stages have a minimum pulse
width of tW(min) = 220 ns (typical). Using the TDA8929T controller, the effective minimum pulse is reduced by a factor of
two during clipping. For the calculation of the maximum output power at clipping the effective minimum pulse width during
clipping is 0.5tW(min).
For the practical useable minimum and maximum duty factor (δ) which determines the maximum output power:
t W(min) × f osc t W(min) × f osc

------------------------------- × 100% < δ <  1 – ------------------------------- × 100%
2 2
Using the typical values of the TDA8926 and TDA8927 power stages:
3.5% < δ < 96.5%.
2001 Dec 11 16
15 TEST AND APPLICATION INFORMATION The low-pass filter performs the demodulation, so that the
audio signal can be measured with an audio analyzer. For
15.1 Test circuit
measuring low distortion values, the speed of the level
The test diagram in Fig.10 can be used for stand alone shifter is important. Special care has to be taken at a
testing of the controller. Audio and mode input pins are sufficient supply decoupling and output waveforms without
configured as in the application. For the simulation of a ringing.
switching output power stage a simple level shifter can be
The handshake with the power stage is simulated by a
used. It converts the digital PWM signal from the controller
direct connection of the release inputs (REL1 and REL2)
(switching between VSS and VSS + 12 V level) to a
with the switch outputs (SW1 and SW2) of the controller.
PWM signal switching between VDD and VSS.
The enable outputs (EN1 and EN2) for waking-up the
A proposal for a simple level shifting circuit is given power stage are not used here, only the output level and
in Fig.9. timing are measured.

VDD
2 kΩ
10 Ω
BST82 33 Ω
PHC2300 PWM
+5 V
10 nF 42 Ω
1.33 kΩ
20 kΩ 10 Ω
switch
0/12 V
74LV14
10 kΩ
VSS VSS
MGW154
Fig.9 Level shifter.
2001 Dec 11 17
dbook, full pagewidth

2001 Dec 11
100 nF
VSS VDD
47 µF
VSS1 VDD1
1 3
R fb PWM1
20
220 nF IN1− 4
WINDOW VDD
COMPARATOR 21 EN1
Vi(L) V/I V
IN1+ 5
24 SW1 LEVEL SHIFTER 30 kHz audio left
220 nF
SGND1 2 mute LOW-PASS audio
0/12 V −30 V/+30 V PWM analyzer
V
SGND 23 REL1
SGND
VSS
100 nF SGND
V
OSC 7 SGND 100 nF

VSS OSCILLATOR 19 STAB VDD
30 kΩ STABILIZER
VSS Vp
15 DIAGTMP
mute MANAGER SGND
22 DIAGCUR
MODE 6 Vp
18
MODE
VSS
SGND TDA8929T
VMODE
16 EN2 VDD
V
SGND
SGND
SGND2 11
SGND mute SW2 LEVEL SHIFTER PWM audio right
13 30 kHz
220 nF LOW-PASS audio
IN2+ 8 0/12 V −30 V/+30 V analyzer
V
Vi(R) V/I 14 REL2
IN2− 9 WINDOW
COMPARATOR VSS
220 nF SGND
17 PWM2
R fb MGW153
12 10 18
VSS2(sub) VDD2 VSSD
47 µF
VSS
TDA8929T
VDD VSS
100 nF
Fig.10 Test diagram.

15.2 BTL application 15.4 External clock

When using the system in a mono BTL application (for Figure 11 shows an external clock oscillator circuit.
more output power), the inputs of both channels must be
connected in parallel. The phase of one the inputs must be 15.5 Reference designs
inverted (see Fig.5). In principle the loudspeaker can be
The reference design for a two-chip class-D audio
connected between the outputs of the two single-ended
amplifier for TDA8926J or TDA8927J and TDA8929T is
demodulation filters. For improving the common mode
shown in Fig.12. The Printed-Circuit Board (PCB) layout is
behavior of the filter, the configuration in Fig.12 is advised.
shown in Fig.13. The bill of materials is given in Table 1.
15.3 Mode pin The reference design for a two-chip class-D audio
amplifier for TDA8926TH or TDA8927TH and TDA8929T
For correct operation the switching voltage on pin MODE
is shown in Fig.14. The PCB layout is shown in Fig.15.
should be de-bounced. If this pin is driven by a mechanical
switch an appropriate de-bouncing low-pass filter should
be used. If pin MODE is driven by an electronic circuit or
microcontroller then it should remain, for at least 100 ms,
at the mute voltage level (Vth1+) before switching back to
the standby voltage level.
handbook, full pagewidth VDDA
J1 R19
5 kΩ
120 pF C3
1 14 mode select
R1 R20
2 13
9.1 kΩ 39 kΩ
3 12
on S1
MODE
4 HEF4047B 11 mute 6
off
5 10 D1
5V6
6 9 C44
220 nF
7 8 TDA8929T
GND
OSC
external clock 7
MGW155
Fig.11 External oscillator circuit.
2001 Dec 11 19
2001 Dec 11
VDDA mode select C1 220 nF
VDDD VSSD
VDDA C2 220 nF VSSA
R19 R20 C10 C11
39 kΩ 560 pF 560 pF
VDD1 VDD2 VSS2 VSS1 QGND
39 kΩ
on 3 10 12 1 R11 R12
MODE PWM2 C18
D1 mute 6 17 5.6 Ω 5.6 Ω
SW2 SW2 L2 1 nF OUT2−
(5.6 V) off S1 C44
220 nF 13 17 11
REL2 REL2 OUT2 Sumida 33 µH 1
14 16 C8 4 or 8 Ω
15 nF CDRH127-330 SE
R1 EN2 EN2 2
GND OSC 16 14
7 U2 VDDD U1 12 R15
BOOT2 OUT2+
27 kΩ 24 Ω C19
VSSA C14 1 nF
C3 R24 VDD1 470 nF
TDA8929T STAB 200 kΩ TDA8926J 5 VDDD C15 QGND
220 nF 19 POWERUP VDD2 220 nF
15 or OUT2−
SGND1 C4 D2 13
2 220 nF (7.5 V) C5
TDA8927J 2
GND
VSSD STAB C7 C6
GND 8Ω
SGND2 18 VSSA VSSD 9 220 nF 220 nF BTL
11 C43 220 nF VSS2 1
180 pF R10 DIAG 10 OUT1+
22 3 VSS1 C17
IN1+ DIAGCUR 1 kΩ QGND
5 8 VSSD 220 nF
CONTROLLER POWER STAGE
C22 C16
470 nF C20
330 pF IN1− BOOT1 R16 1 nF OUT1−
4
21
EN1 EN1 6 24 Ω
4 2
IN2+ REL1 REL1 C9 Sumida 33 µH 4 or 8 Ω
8 23 2 15 nF CDRH127-330 SE
C23 SW1 SW1 OUT1 1
J5 24 1 7
330 pF IN2− PWM1 L4 OUT1+
C21
J6 9 20 R13 R14 1 nF
15 5.6 Ω 5.6 Ω
C25 C24 C26 C27 QGND outputs
C12 C13
470 nF 470 nF 470 nF 470 nF n.c. 560 pF 560 pF
20
R5 R4 R6 R7 VDDD VSSD
QGND L7
10 kΩ 10 kΩ 10 kΩ 10 kΩ bead
C28 C29 C30 L5 VDDA
1 nF bead
1 nF 1 nF VDDD C40
C36 C37 47 µF
+25 V VDD C34 220 nF 220 nF
R21 C32 1500 µF (35 V)
1 10 kΩ 220 nF (35 V)
input 1 input 2 GND 2 GND
J1 J3 J4 3 C35
R22 C33 1500 µF C41
−25 V VSS 9.1 kΩ 220 nF (35 V) C38 C39 47 µF
QGND QGND 220 nF 220 nF
J2 VSSD (35 V)
C31 bead
1 nF L6 VSSA
inputs
VSS
QGND power supply MLD633
TDA8929T
R21 and R22 are only necessary in BTL applications with asymmetrical supply.
BTL: remove R6, R7, C23, C26 and C27 and close J5 and J6.
C22 and C23 influence the low-pass frequency response and should be tuned with the real load (loudspeaker).
Inputs floating or inputs referenced to QGND (close J1 and J4) or referenced to VSS (close J2 and J3) for an input signal ground reference.
Fig.12 Two-chip class-D audio amplifier application diagram for TDA8926J or TDA8927J and TDA8929T.

2001 Dec 11
TDA8926J/27J & TDA8929T
U1 D1
C24
C16 C40
C34 C25
C35 C26
C14 C41
L7 C27
state of D art
D2 Version 21 03-2001
L6
Out1 Out2 L5
ON
S1 MUTE
OFF
VDD
GND
VSS
In1 In2
Silk screen top, top view Copper top, top view

21
L4
R19 C1
C6
R20 C44
C43 C38
C9
R16 C13 R10
C32 C12 R14 C36
R13
C17
U2 C22
C5 J5
C23
C15
R11 R12 J6
C33 C10 C37
R15 C11 C4 C3
C8
C7 C39
R1 C2
R24
In1 In2
L2 R5 R7
R21 R22
Out1 Out2 C28 R4 R6
C29
VDD VSS
C21 C19
GND J2 J3
J1 J4
TDA8929T
C20 C18 C30 C31
QGND
MLD634
Silk screen bottom, top view Copper bottom, top view
Fig.13 Printed-circuit board layout for TDA8926J or TDA8927J and TDA8929T.

2001 Dec 11
VDDA mode select C11 100 nF
VDDD VSSD
VDDA C12 100 nF VSSA
R1 R2 C24 C25
30 kΩ 560 pF 560 pF
VDD1 VDD2 VSS2 VSS1 QGND
39 kΩ VSS(sub)
on 3 10 12 1 VSSD R12 R13
MODE PWM2 19 L1 C40
D1 mute 6 17 5.6 Ω 5.6 Ω
bead L2 1 nF OUT2−
(5.6 V) off S1 C1 SW2 SW2
220 nF 13 16 9
REL2 REL2 OUT2 Sumida 33 µH 1
14 15 C26 4 or 8 Ω
15 nF CDRH127-330 SE
R3 EN2 EN2 2
GND OSC 16 13
7 U2 VDDD 10 C36 R16
U1 BOOT2 OUT2+
27 kΩ 470 nF 5.6 Ω C41
VSSA R18 1 nF
C2 VDD1
200 kΩ VDDD
TDA8929T STAB POWERUP 2 C38 QGND
220 nF 19 14 TDA8926TH VDD2 C31 220 nF
D2 or C29 OUT2−
SGND1 C13 C14
11 1500 µF
2 (7.5 V) 100 nF
100 nF STAB TDA8927TH C28 (35 V) 2
GND
VSSD VSSD 6 C27
100 GND 8Ω
SGND2 18 VSSA 100 nF STAB 100 nF BTL
11 7 VSS2 nF C32 1
C15 8 C30 1500 µF
180 pF 100 nF OUT1+
DIAGCUR R8 DIAG (35 V) C39
IN1+ VSS1 QGND
22 23 5 220 nF
5 CONTROLLER VSSD
1 kΩ POWER STAGE
C3 C42
330 pF C37 R17 1 nF
IN1− BOOT1 OUT1−
4
21
EN1 EN1 3 470 nF 5.6 Ω
24 2
IN2+ REL1 REL1 C33 L3 Sumida 33 µH 4 or 8 Ω
8 23 22 15 nF CDRH127-330 SE
OUT1 bead
C4 SW1 SW1 1
J5 24 21 4
22
330 pF IN2− PWM1 L4 OUT1+

C43
J6 9 20 LIM R14 R15
VSSD 1 nF
15 17 1, 12, 18, 20 5.6 Ω 5.6 Ω
C5 C6 C7 C8 QGND outputs
C34 C35
1 µF 1 µF 1 µF 1 µF n.c. n.c. 560 pF 560 pF
R4 R5 R6 R7 VDDD VSSD
10 kΩ 10 kΩ 10 kΩ 10 kΩ QGND L7
C9 C10 bead R11
C16 L5 VDDA
1 nF bead 5.6 Ω
1 nF 1 nF
VDDD C22
C18 C19 47 µF
+25 V VDD
R9 100 nF 100 nF (35 V)
1 10 kΩ
input 1 input 2
GND 2 GND
J1 J3 J4
3 R10
QGND C23
QGND QGND −25 V VSS 9.1 kΩ C20 C21 47 µF
J2 100 nF 100 nF (35 V)
VSSD
C17 bead
inputs 1 nF L6
VSS VSSA
QGND power supply MGW232
TDA8929T
R9 and R10 are only necessary in BTL applications with asymmetrical supply.
BTL: remove R6, R7, C4, C7 and C8 and close J5 and J6.
Demodulation coils L2 and L4 should be matched in BTL.
Inputs floating or inputs referenced to QGND (close J1 and J4) or referenced to VSS (close J2 and J3).
Fig.14 Two-chip class-D audio amplifier application diagram for TDA8926TH or TDA8927TH and TDA8929T.
dbook, full pagewidth

2001 Dec 11
TDA8926TH/27TH
C37 C31 TDA8929T
L3
C22
D1
L1 State of D art C23

C36 C32
L6 Version 2CTH1
L5
Out1 Out2 S1
ON
MU
OFF
VDD GND VSS In2 In1
Silk screen top, top view Copper top, top view

23
C34
Jan 2001 C1 C15 C11 C20
R14 R8
C33 R1 R2
R15
L4 C35
C29 U1 U2
C28 C3 C18
C14
C27 C4
C30
L5 C12 C19
C25
R13 C26 C13 C2
R12 C21
C24 J6
L7 R11 R3 C8
J5
C7
R17 C39 C38 R16 R9 R10 C10 C9
C5
R7 R4
R6 R5 C6
J2
C43 C42 C41 C40 C16 C17 J3
J4 J1
QGND
MGW147
Silk screen bottom, top view Copper bottom, top view
TDA8929T
Fig.15 Printed-circuit board layout for TDA8926TH or TDA8927TH and TDA8929T.
15.6 Reference design bill of material

Table 1 Two-chip class-D audio amplifier PCB (Version 2.1; 03-2001) for TDA8926J or TDA8927J and TDA8929T
(see Figs 12 and 13)
COMPONENT DESCRIPTION VALUE COMMENTS
In1 and In2 Cinch input connectors 2 × Farnell: 152-396
Out1, Out2, VDD, supply/output connectors 2 × Augat 5KEV-02;
GND and VSS 1 × Augat 5KEV-03
S1 on/mute/off switch PCB switch Knitter ATE 1 E M-O-M
U1 power stage IC TDA8926J/27J DBS17P package
U2 controller IC TDA8929T SO24 package
L2 and L4 demodulation filter coils 33 µH 2 × Sumida CDRH127-330
L5, L6 and L7 power supply ferrite beads 3 × Murata BL01RN1-A62
C1 and C2 supply decoupling capacitors for 220 nF/63 V 2 × SMD1206
VDD to VSS of the controller
C3 clock decoupling capacitor 220 nF/63 V SMD1206
C4 12 V decoupling capacitor of the 220 nF/63 V SMD1206
controller
C5 12 V decoupling capacitor of the power 220 nF/63 V SMD1206
stage
C6 and C7 supply decoupling capacitors for 220 nF/63 V SMD1206
VDD to VSS of the power stage
C8 and C9 bootstrap capacitors 15 nF/50 V 2 × SMD0805
C10, C11, snubber capacitors 560 pF/100 V 4 × SMD0805
C12 and C13
C14 and C16 demodulation filter capacitors 470 nF/63 V 2 × MKT
C15 and C17 resonance suppress capacitors 220 nF/63 V 2 × SMD1206
C18, C19, common mode HF coupling capacitors 1 nF/50 V 4 × SMD0805
C20 and C21
C22 and C23 input filter capacitors 330 pF/50 V 2 × SMD1206
C24, C25, input capacitors 470 nF/63 V 4 × MKT
C26 and C27
C28, C29, common mode HF coupling capacitors 1 nF/50 V 2 × SMD0805
C30 and C31
C32 and C33 power supply decoupling capacitors 220 nF/63 V 2 × SMD1206
C34 and C35 power supply electrolytic capacitors 1500 µF/35 V 2 × Rubycon ZL very low ESR (large
switching currents)
C36, C37, analog supply decoupling capacitors 220 nF/63 V 4 × SMD1206
C38 and C39
C40 and C41 analog supply electrolytic capacitors 47 µF/35 V 2 × Rubycon ZA low ESR
C43 diagnostic capacitor 180 pF/50 V SMD1206
C44 mode capacitor 220 nF/63 V SMD1206
D1 5.6 V zener diode BZX79C5V6 DO-35
D2 7.5 V zener diode BZX79C7V5 DO-35
R1 clock adjustment resistor 27 kΩ SMD1206
2001 Dec 11 24
COMPONENT DESCRIPTION VALUE COMMENTS

R4, R5, input resistors 10 kΩ 4 × SMD1206
R6 and R7
R10 diagnostic resistor 1 kΩ SMD1206
R11, R12, snubber resistors 5.6 Ω; >0.25 W 4 × SMD1206
R13 and R14
R15 and R16 resonance suppression resistors 24 Ω 2 × SMD1206
R19 mode select resistor 39 kΩ SMD1206
R20 mute select resistor 39 kΩ SMD1206
R21 resistor needed when using an 10 kΩ SMD1206
asymmetrical supply
R22 resistor needed when using an 9.1 kΩ SMD1206
asymmetrical supply
R24 bias resistor for powering-up the power 200 kΩ SMD1206
stage
15.7 Curves measured in reference design
MLD627 MLD628
102 102
handbook, halfpage handbook, halfpage
THD+N THD+N
(%) (%)
10 10
1 1
(1)
(1)
10−1 10−1
(2)
10−2 10−2 (2)
(3)
10−3 −2 10−3
10 10−1 1 10 102 103 10 102 103 104 105
Po (W) f i (Hz)
2 × 8 Ω SE; VP = ±25 V:
(1) 10 kHz. 2 × 8 Ω SE; VP = ±25 V:
(2) 1 kHz. (1) Po = 10 W.
(3) 100 Hz. (2) Po = 1 W.
Fig.16 THD + N as a function of output power. Fig.17 THD + N as a function of input frequency.
2001 Dec 11 25
MLD629 MLD630
102 102
THD+N THD+N
(%) (%)
10 10
1 1
(1) (1)
10−1 10−1
(2)
(2)
10−2 (3) 10−2
10−3 −2 10−3
10 10−1 1 10 102 103 10 102 103 104 105
Po (W) f i (Hz)
2 × 4 Ω SE; VP = ±25 V:
(1) 10 kHz. 2 × 4 Ω SE; VP = ±25 V:
(2) 1 kHz. (1) Po = 10 W.
(3) 100 Hz. (2) Po = 1 W.
MLD631 MLD632
102 102
THD+N THD+N
(%) (%)
10 10
1 1
(1) (1)
10−1 10−1
(2)
(2)
10−2 10−2
(3)
10−3 −2 10−3
10 10−1 1 10 102 103 10 102 103 104 105
Po (W) f i (Hz)
1 × 8 Ω BTL; VP = ±25 V:
(1) 10 kHz. 1 × 8 Ω BTL; VP = ±25 V:
(2) 1 kHz. (1) Po = 10 W.
(3) 100 Hz. (2) Po = 1 W.
2001 Dec 11 26
MLD609 MLD610
25 100
(3)
P η (1)
(W) (%)
(2)
20 80
15 60
(1) (2)
10 40
(3)
5 20
0 0
10−2 10−1 1 10 102 103 0 30 60 90 120 150
Po (W) Po (W)
VP = ±25 V; fi = 1 kHz:
(1) 2 × 4 Ω SE. VP = ±25 V; fi = 1 kHz:
(2) 1 × 8 Ω BTL. (1) 2 × 4 Ω SE.
(3) 2 × 8 Ω SE. (2) 1 × 8 Ω BTL.
(3) 2 × 8 Ω SE.
Fig.22 Power dissipation as a function of output
power. Fig.23 Efficiency as a function of output power.
MLD611 MLD612
200 200
Po Po (2)
(W) (W)
160 160
(2)
120 120
(1)
(1) (3)
80 80
(3)
(4)
(4)
40 40
0 0
10 15 20 25 30 35 10 15 20 25 30 35
VP (V) VP (V)
THD + N = 0.5%; fi = 1 kHz: THD + N = 10%; fi = 1 kHz:

(1) 1 × 4 Ω BTL. (1) 1 × 4 Ω BTL.
(2) 1 × 8 Ω BTL. (2) 1 × 8 Ω BTL.
(3) 2 × 4 Ω SE. (3) 2 × 4 Ω SE.
(4) 2 × 8 Ω SE. (4) 2 × 8 Ω SE.
Fig.24 Output power as a function of supply Fig.25 Output power as a function of supply
voltage. voltage.
2001 Dec 11 27
MLD613 MLD614
0 0
αcs αcs
(dB) (dB)
−20 −20
−40 −40
−60 (1)
−60
(1)
−80 (2) −80 (2)
−100 −100
10 102 103 104 105 10 102 103 104 105
f i (Hz) f i (Hz)
2 × 8 Ω SE; VP = ±25 V: 2 × 4 Ω SE; VP = ±25 V:

(1) Po = 10 W. (1) Po = 10 W.
(2) Po = 1 W. (2) Po = 1 W.
Fig.26 Channel separation as a function of input Fig.27 Channel separation as a function of input
frequency. frequency.
MLD615 MLD616
45 45
G G
(dB) (dB)
40 40
(1)
35 35
(1)
(2)
30 30
(2)
(3)
25 (3) 25
20 20
10 102 103 104 105 10 102 103 104 105
f i (Hz) f i (Hz)
VP = ±25 V; Vi = 100 mV; VP = ±25 V; Vi = 100 mV;

Rs = 10 kΩ/Ci = 330 pF: Rs = 0 Ω:
(1) 1 × 8 Ω BTL. (1) 1 × 8 Ω BTL.
(2) 2 × 8 Ω SE. (2) 2 × 8 Ω SE.
(3) 2 × 4 Ω SE. (3) 2 × 4 Ω SE.
Fig.28 Gain as a function of input frequency. Fig.29 Gain as a function of input frequency.
2001 Dec 11 28
MLD617 MLD618
0 0
SVRR SVRR
(dB) (dB)
−20 −20
−40 −40
(1)
(1)
−60 −60 (2)
(2)
(3)
(3)
−80 −80
−100 −100
10 102 103 104 105 0 1 2 3 4 5
f i (Hz)
Vripple (V)
VP = ±25 V; Vripple = 2 V (p-p) with respect to GND: VP = ±25 V; Vripple with respect to GND:
(1) Both supply lines in anti-phase. (1) fripple = 1 kHz.
(2) Both supply lines in phase. (2) fripple = 100 Hz.
(3) One supply line rippled. (3) fripple = 10 Hz.
Fig.30 SVRR as a function of input frequency. Fig.31 SVRR as a function of Vripple (p-p).
MLD619 MLD620
100 380
Iq fclk
(mA) (kHz)
80 372
60 364
40 356
20 348
0 340
0 10 20 30 37.5 0 10 20 30 40
VP (V) VP (V)
RL = open. RL = open.
Fig.32 Quiescent current as a function of supply Fig.33 Clock frequency as a function of supply
voltage. voltage.
2001 Dec 11 29
MLD621 MLD622
5 5
Vripple
SVRR
(V) (%)
4 4
3 3
(1)
(1)
2 2
1 (2) 1
(2)
0 0
10−2 10−1 1 10 102 10 102 103 104
Po (W) f i (Hz)
VP = ±25 V; 1500 µF per supply line; fi = 10 Hz:

(1) 1 × 4 Ω SE. VP = ±25 V; 1500 µF per supply line:
(2) 1 × 8 Ω SE. (1) Po = 30 W into 1 × 4 Ω SE.
(2) Po = 15 W into 1 × 8 Ω SE.
Fig.34 Supply voltage ripple as a function of output
power. Fig.35 SVRR as a function of input frequency.
MLD623 MLD624
10 50
Po
THD+N
(W)
(%)
40
1
(1)
30
10−1
(2) 20
(3)
10−2
10
10−3 0
100 200 300 400 500 600 100 200 300 400 500 600
fclk (kHz) fclk (kHz)
VP = ±25 V; Po = 1 W in 2 × 8 Ω:
(1) 10 kHz.
VP = ±25 V; RL = 2 × 8 Ω; fi = 1 kHz; THD + N = 10%.
(2) 1 kHz.
(3) 100 Hz.
Fig.37 Output power as a function of clock
Fig.36 THD + N as a function of clock frequency. frequency.
2001 Dec 11 30
MLD625 MLD626
150 1000
Iq Vr(PWM)
(mA) (mV)
120 800
90 600
60 400
30 200
0 0
100 200 300 400 500 600 100 200 300 400 500 600
fclk (kHz) fclk (kHz)
VP = ±25 V; RL = open. VP = ±25 V; RL = 2 × 8 Ω.
Fig.38 Quiescent current as a function of clock Fig.39 PWM residual voltage as a function of clock
frequency. frequency.
2001 Dec 11 31
16 PACKAGE OUTLINE
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
D E A
X
y HE v M A
24 13
Q
A2 A
A1 (A 3)
pin 1 index
θ
Lp
L
1 12 detail X
e w M
bp
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z
(1)
θ
max.
0.30 2.45 0.49 0.32 15.6 7.6 10.65 1.1 1.1 0.9
mm 2.65 0.25 1.27 1.4 0.25 0.25 0.1
0.10 2.25 0.36 0.23 15.2 7.4 10.00 0.4 1.0 0.4 8o
0.012 0.096 0.019 0.013 0.61 0.30 0.419 0.043 0.043 0.035 0o
inches 0.10 0.01 0.050 0.055 0.01 0.01 0.004
0.004 0.089 0.014 0.009 0.60 0.29 0.394 0.016 0.039 0.016
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION
97-05-22
SOT137-1 075E05 MS-013
99-12-27
2001 Dec 11 32
17 SOLDERING If wave soldering is used the following conditions must be

observed for optimal results:
17.1 Introduction to soldering surface mount
packages • Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
This text gives a very brief insight to a complex technology. smooth laminar wave.
A more in-depth account of soldering ICs can be found in
• For packages with leads on two sides and a pitch (e):
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011). – larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
There is no soldering method that is ideal for all surface transport direction of the printed-circuit board;
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch – smaller than 1.27 mm, the footprint longitudinal axis
SMDs. In these situations reflow soldering is must be parallel to the transport direction of the
recommended. printed-circuit board.
The footprint must incorporate solder thieves at the
17.2 Reflow soldering downstream end.
Reflow soldering requires solder paste (a suspension of • For packages with leads on four sides, the footprint must
fine solder particles, flux and binding agent) to be applied be placed at a 45° angle to the transport direction of the
to the printed-circuit board by screen printing, stencilling or printed-circuit board. The footprint must incorporate
pressure-syringe dispensing before package placement. solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example, During placement and before soldering, the package must
convection or convection/infrared heating in a conveyor be fixed with a droplet of adhesive. The adhesive can be
type oven. Throughput times (preheating, soldering and applied by screen printing, pin transfer or syringe
cooling) vary between 100 and 200 seconds depending dispensing. The package can be soldered after the
on heating method. adhesive is cured.
Typical reflow peak temperatures range from Typical dwell time is 4 seconds at 250 °C.
215 to 250 °C. The top-surface temperature of the A mildly-activated flux will eliminate the need for removal
packages should preferable be kept below 220 °C for of corrosive residues in most applications.
thick/large packages, and below 235 °C for small/thin
packages. 17.4 Manual soldering
Fix the component by first soldering two
17.3 Wave soldering diagonally-opposite end leads. Use a low voltage (24 V or
Conventional single wave soldering is not recommended less) soldering iron applied to the flat part of the lead.
for surface mount devices (SMDs) or printed-circuit boards Contact time must be limited to 10 seconds at up to
with a high component density, as solder bridging and 300 °C.
non-wetting can present major problems. When using a dedicated tool, all other leads can be
To overcome these problems the double-wave soldering soldered in one operation within 2 to 5 seconds between
method was specifically developed. 270 and 320 °C.
2001 Dec 11 33
17.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE REFLOW(1)
BGA, HBGA, LFBGA, SQFP, TFBGA not suitable suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS not suitable(2) suitable
PLCC(3), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(3)(4) suitable
SSOP, TSSOP, VSO not recommended(5) suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2001 Dec 11 34
18 DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS(1) DEFINITIONS
STATUS(2)
Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
19 DEFINITIONS 20 DISCLAIMERS
Short-form specification  The data in a short-form Life support applications  These products are not
specification is extracted from a full data sheet with the designed for use in life support appliances, devices, or
same type number and title. For detailed information see systems where malfunction of these products can
the relevant data sheet or data handbook. reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
Limiting values definition  Limiting values given are in
for use in such applications do so at their own risk and
accordance with the Absolute Maximum Rating System
agree to fully indemnify Philips Semiconductors for any
(IEC 60134). Stress above one or more of the limiting
damages resulting from such application.
values may cause permanent damage to the device.
These are stress ratings only and operation of the device Right to make changes  Philips Semiconductors
at these or at any other conditions above those given in the reserves the right to make changes, without notice, in the
Characteristics sections of the specification is not implied. products, including circuits, standard cells, and/or
Exposure to limiting values for extended periods may software, described or contained herein in order to
affect device reliability. improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
Application information  Applications that are
the use of any of these products, conveys no licence or title
described herein for any of these products are for
under any patent, copyright, or mask work right to these
illustrative purposes only. Philips Semiconductors make
products, and makes no representations or warranties that
no representation or warranty that such applications will be
these products are free from patent, copyright, or mask
suitable for the specified use without further testing or
work right infringement, unless otherwise specified.
modification.
2001 Dec 11 35
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825

For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2001 SCA73

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands 753503/01/pp36 Date of release: 2001 Dec 11 Document order number: 9397 750 08189

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INTEGRATED CIRCUITS

Controller class-D audio amplifier TDA8929T

CONTENTS 15 TEST AND APPLICATION INFORMATION

Controller class-D audio amplifier TDA8929T

1 FEATURES 3 GENERAL DESCRIPTION

Controller class-D audio amplifier TDA8929T

5 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

Controller class-D audio amplifier TDA8929T

handbook, full pagewidth VSS1 VDD1

VSS2(sub) VDD2 VSSD

Fig.1 Block diagram.

Controller class-D audio amplifier TDA8929T

SYMBOL PIN DESCRIPTION

SGND2 11 signal ground channel 2 SGND2 11 14 REL2

VSS2(sub) 12 negative analog supply voltage VSS2(sub) 12 13 SW2

Controller class-D audio amplifier TDA8929T

8 FUNCTIONAL DESCRIPTION The amplifier system can be switched in three operating

Controller class-D audio amplifier TDA8929T

8.2 Pulse width modulation frequency 8.3.2 DIAGNOSTIC CURRENT

8.3.1 DIAGNOSTIC TEMPERATURE

Controller class-D audio amplifier TDA8929T

8.3.3 START-UP SAFETY TEST 8.4 Differential audio inputs

handbook, full pagewidth

Fig.5 Mono BTL application.

Controller class-D audio amplifier TDA8929T

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Controller class-D audio amplifier TDA8929T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Controller class-D audio amplifier TDA8929T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Controller class-D audio amplifier TDA8929T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

handbook, full pagewidth

VMODE(hys1) VMODE(hys2) MGW334

Fig.6 Mode pin selection.

Controller class-D audio amplifier TDA8929T

handbook, full pagewidth audio

Fig.7 Mode pin timing from standby to on via mute.

handbook, full pagewidth audio

Fig.8 Mode pin timing from standby to on.

Controller class-D audio amplifier TDA8929T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

14.1 Minimum pulse width

t W(min) × f osc t W(min) × f osc

Controller class-D audio amplifier TDA8929T

handbook, full pagewidth

Fig.9 Level shifter.

dbook, full pagewidth

OSC 7 SGND 100 nF

Fig.10 Test diagram.

Controller class-D audio amplifier TDA8929T

15.2 BTL application 15.4 External clock

handbook, full pagewidth VDDA

Fig.11 External oscillator circuit.

handbook, full pagewidth

Silk screen top, top view Copper top, top view

Fig.13 Printed-circuit board layout for TDA8926J or TDA8927J and TDA8929T.

330 pF IN2− PWM1 L4 OUT1+

dbook, full pagewidth

L1 State of D art C23

Silk screen top, top view Copper top, top view