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13.clock Stand07 PDF
13.clock Stand07 PDF
• Clocked Systems
• Latch and Flip-flops
• System timing
• Clock skew
• High speed latch
design
• Phase locked loop
• Dynamic logic
• Multiple phase clock
• Clock distribution
VLSI System Design NCKUEE-KJLEE
Clocked Systems
Pipelined systems
Input D Q D Q ... D Q output
Logic Logic
CLK CLK
QD
CLK or CLKS
VLSI System Design NCKUEE-KJLEE
Single-phase clock timing
waveforms
Cycle Time (Tc)
Tc: clock cycle time (period) D Q
Clock
CLK
Setup Time (Ts)
Ts: setup time -- the time before
the clock edge during which
data the data input (D) has to be
stable
Hold Time (Th) Th: hold time -- the time after the
clock edge during which the
data input (D) has to remain
stable
Q Tq: clock-to-Q delay -- The delay
Clock-to-Q Delay (Tq) from the clock edge to the Q
output
clk
0 D
Q
D Q
1
s
CLK
clk=0
clk=1
master slave
(d) Pass transistor/inverter implementation
Tc
Tq Combinational Ts
Register Register
Logic
clock A B
Td
Tq Td Ts
Tc >Tq + Td + Ts
(B) Alternatively, one may use latches as storage elements to save area.
Tq Combinational Ts
Latch Latch
Logic
clock A B
Td
(C)
A B
Tq Combinational Ts Combinational
Latch Latch Latch
Logic Logic
clock A B c
Tda Tdb
Tc1 Tco
Tc1>Tqa+Tda+Tsb Tco>Tqb+Tdb+Tsc
If Tc=Tc1+Tco and Tc1=Tco, Tqa=Tqb,
Tsb=Tsc
Tqa Tda Tsb Tqb Tdb Tsc
=> The limit is Tc = Tda + Tdb + 2(Tq+Ts)
Tc2
C2 C1 C1
C2
C1 = C2 or C2 = C1 Wrong data Correct
in L2 data
C2 C1 C1 C2
2) C1=C2
C1
C2
Comb
L1 L2
Wrong
only if
Comb.
CLK Logic
FSM --> "feedback" or
Pipeline --> "feedthrough"
clk clk
clk
clk-in clk
3.Very careful simulation(HSPICE)
4.Very small rise and fall time on
clk the clock-- large buffer for large
load
5.Multiple clocking strategies
usually slightly smaller than the inverter
D c lk
c lk
c lk c lk
buffered
input
compared with a tri-state buffer
VLSI System Design NCKUEE-KJLEE
Typical symbolic layouts for
latches
(a) (b) (c)
V V V
DD DD DD
D Q D Q D Q
-clk -clk
D
clk clk
Q clk clk clk clk
clk clk
D Q D Q
-clk -clk
-Q Q
D
clk
(b) Edge triggered
D
Q
-Q
clk
-clk clk
-set -clk
VLSI System Design NCKUEE-KJLEE
Dynamic single clock latches
D -Q D
-clk -clk
(a) (b)
clk -clk
clk clk -clk
D
D Q D Q
-clk -clk clk
-clk clk
dclk dclk
/4 clock d
clk
route
clock clock
PLL PLL
dclk
16/8
16/8
If F1 falls before F2
=> UP=1
16/8 16/8 16/8
F2 16/8 DN
If F2 falls before F1
16/8 16/8
=> DN=1
P-REF P1 SW0
40/2
P1 P-REF 40/2
N1
2/5 P-SWITCHSW0
CHGUP
N2 SW1
2/5 CAP
40/2 8/1
N4 CHGDN P-SWITCH SW0 IN
N3 10/2
N-REF SW1 16/1 10/2
10/2
N5
N-REF
SW1
40/2
in
out 32/1 32/1 32/1
2/6 4/6
32/1 32/1 32/1
13stages
16xFsc
2400/6 2400/6 control 16/1 16/1
16/1
voltage
metastable
point
Inv2
VA
0V 2.5V 5V
clk -clk
p-logic C2MOS
n-logic block latch
-clk
to -clk section block
clk n-p CMOS -clk logic stage
(b)
Inputs from
-clk stages
-clk clk -clk clk -clk
p-logic C2MOS latch logic logic logic 0 1
n-logic block 1 0
evaluation Precharge evaluation
block From n or buffered p-logic Precharge evaluation Precharge
n-p CMOS clk logic stage
(a) (c)
clk -clk
phi1
phi1 phi1 logic skewed
phi2
phi phi2 logic clokcs
2
overlap
-phi1 -phi2 (c) small dealy
D Q
phi phi2 DFF1
1
(a)
slow rise
phi1=1 time
phi2=0
overlap
C1 C2 phi1=1
phi =0 phi2=0
1
C1 C2
phi =1
2 (d)
C C2
(b) 1
high level =V -V
-phi1 DD tn
-phi
2
D Q
D Q
DEF1A
phi1 phi
(a) 2
DEF1
phi1 phi2 p leakers
-phi -phi
1 2
-phi1
-phi
D 2 n Q D Q
1 n D Q
2 (b)
phi1 phi2
phi phi2 phi DEF1B
1 1 phi
2
D Q
clk
DEF2 DEF3
Both of these dynamic registers
(c)
have to drive a local storage gate.
n-bit datapath
n-bit datapath
clock
n-bit datapath
delays have to match
between stages n-bit datapath
n-bit datapath
n-bit datapath
n-bit datapath
n-bit datapath