Experiment 3

Aim:
To design and analyze the Common Source MOS Amplifier
and plot the following curves:
I. Vout v/s Vin
II. Transient Output
III. Frequency Response
and observe variation in frequency response and transient
output when

i. is varied
ii. RD is increased

Theory:
By virtue of its transconductance, a MOSFET converts
changes in its gate-source voltage to a small-signal
drain current, which can pass through a resistor to generate
an output voltage.
The input impedance of the circuit is very high at low
frequencies.

Figure: Common-source stage

If the input voltage increases from zero, M1 is off and 𝑉 =
𝑉 . As 𝑉 approaches 𝑉 , M1 begins to turn on, drawing
current from 𝑅 and lowering 𝑉 . Transistor M1 turns on
in
saturation regardless of the values of 𝑉 and 𝑅 , and we
have
1 𝑊
𝑉 =𝑉 − 𝑅 𝜇 𝐶 (𝑉 − 𝑉 )
2 𝐿

where channel-length modulation is neglected.

With further increase in 𝑉 , 𝑉 drops more, and the
transistor continues to operate in saturation until 𝑉
exceeds 𝑉 by 𝑉 .
A further increase in 𝑉 causes the MOSFET to enter the
triode region.

Procedure:
1. Setup up a circuit as shown below in the Virtuoso
schematic environment.
2. The required MOS can be found in the ‘gpdk180’ library.
3. After properly setting up the circuit, run the simulation.
4. Plot variation of and Vout vs Vin, Vout & Vin vs time and
Gain in dB.
Observation:

1. 𝑉 required to bias the transistor into saturation region

= 1.5 V
2. 𝑅 = 4kΩ
3. A phase difference of 180° can be observed between the
input and output waveforms.
4. Gain= 5.6 dB
5. In the Frequency response we see that the gain drops at
4 × 107 Hz indicating the presence of a pole.

Result:
Hence, we successfully simulated and observed the
behaviour of a Common Source Amplifier.
 Experiment 4
Aim:
To design and analyze the Common Source MOS Amplifier
with
I. PMOS diode connected load
II. Current Mirror load
III. Ideal Current Source load
and plot the following curves:
I. Vout v/s Vin
II. Transient Output
III. Frequency Response

Theory:
1. Diode connected PMOS Load
A MOSFET can operate as a small-signal resistor if its
gate and drain are shorted.

Figure: (a) Diode-connected NMOS and PMOS devices; (b) small-signal equivalent circuit

Called a “diode-connected” device in analogy with its

bipolar counterpart, this configuration exhibits small-
signal behaviour like that of two-terminal resistor.
The transistor is always in saturation because the drain
and the gate have the same potential.
 Using the small-signal equivalent to obtain the
impedance of the device, we get
1
𝑅 ≈
𝑔

Figure CS stage with diode-connected load. Figure CS stage with diode connected PMOS load.

2. Ideal Current Source Load

In applications requiring a large voltage gain in a single
stage, the relationship 𝑅 = −𝑔 𝑅 suggests that we
should increase the load impedance of the CS stage.

With a resistor or diode-connected load, however,

increasing the load resistance translates to a large dc
drop across the load, thereby limiting the output voltage
swing.
A more practical approach is to replace the load with a
device that does not obey Ohm’s law, e.g., a current
source.

3. Current Mirror Load

Since realisation of an ideal current source is practically
impossible, one may use the current mirror circuit in
place of the current source.
Observation:
1. Diode Connected PMOS Load

1. 𝑉 required to bias the transistor into saturation region

= 1.5 V
2. A phase difference of 180° can be observed between the
input and output waveforms.
3. Gain= 10.9 dB (approx.)
4. In the Frequency response we see that the gain drops at
103 Hz indicating the presence of a pole.
2. Ideal Current Source Load

1. 𝑉 required to bias the transistor into saturation

region = 0.1 V
2. A phase difference of 180° can be observed between
the input and output waveforms.
3. Gain= 69 dB (approx.)
4. In the Frequency response we see that the gain drops
at 2 × 105 Hz indicating the presence of a pole.
5.
 3. Current Mirror Load

1. 𝑉 required to bias the transistor into saturation

region = 0.6 V
2. A phase difference of 180° can be observed between
the input and output waveforms.
3. Gain= 41 dB (approx.)
4. In the Frequency response we see that the gain drops
at 2 × 105 Hz indicating the presence of a pole.

Result:
Hence, we successfully simulated and observed the Common
Source MOS Amplifier with
I. PMOS diode connected load
II. Current Mirror load
III. Ideal Current Source load