LINT CHECK:

In general Lint tools that flag suspicious and non- portable usage of
language construct in any programming language. It points out the code where it
likely to be bugs. In chip design world Lint tools (some time referred as Design
Rule Checker) check the cleanness and portability of the HDLs code for various EDA
tools. Usually compiler does not show the errors and warnings which detected by
lint tools. There are many advantages of it, for example when design style enforced
by lint tool it avoids a situation where the synthesis tools implements something
different than expected from RTL code.
For example consider the following Verilog code

Lint Check example

module lint_check(a,b,c);

input a;

input b;

output c;

assign c= a+b;

endmodule

This example is completely ok with compiler. Complier does not generate warning. In
the above code by default the output variable �c� is a wire. It is not necessary
declare it as a wire. But some (not every) synthesis tools may need it to be
declared it as a wire.

If Lint tool applied on the code before the synthesis, it points out the above
mistake. This is just one example. There are many standards and lint check rules
are available. Here are some example for rules, coding style, DFT, design style,
language constructs, synthesis and also possible to include custom rule checking.
It is possible to select/deselect the rules/standards during lint checking. It
completely depends on the need of the particular environment and design.
Lint check rule can be stand alone or it can be integrated with come verification
environment. Spyglass is a stand alone Lint tool, nLint integrated with Veridi and
Debussy debug systems. Leda (synopsys call it �RTL checker�) BlackTie from cadence
are some other Lint tools in the market.